JP2001144592A - Phase comparison circuit with lock detection function - Google Patents

Abstract

(57) [Object] The present invention provides a data signal and a clock without increasing the circuit scale even when using a phase comparator having a plurality of output terminals such as a Bang-Bang type phase comparator. An object of the present invention is to configure a phase comparison circuit with a lock detection function that can stop the output of the phase comparison circuit when a signal is in an unlocked state. According to the present invention, D-type flip-flop circuits for retiming an output signal of a phase comparison circuit are provided.
The clock signal 6 input to the clock input is latched or passed through by the lock detection output signal 8 in the latch circuit 3. As a result, the number of necessary latch circuits can be reduced in the entire circuit.
Generation of the clock signal 6 input to the flip-flop circuits 10a and 10b is stopped, and the phase comparison detection signal 7
The outputs of a and 7b can be stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparison circuit, and more particularly to a phase comparison circuit having a lock detection function and having a lock detection function.

[0002] Generally, a phase comparison circuit is a phase locked loop (P
LL) circuit. In recent years, a lock detection circuit has been added to a phase comparison circuit in order to reduce a synchronization pull-in time in a PLL circuit.

On the other hand, when a transmission / reception unit for data communication is formed using a PLL circuit, a phase comparison circuit used for the PLL circuit is used from the viewpoint of ensuring the reliability of data by preventing transmission / reception of signals other than the intended data signal. There is a case where a function of stopping output of a data signal in an unlocked state using an output of a lock detection circuit is added to a circuit in some cases.
In this case, the lock detection circuit is a separate circuit from the phase comparison circuit, and a part of the PLL circuit is configured by combining the two circuits.

[0004]

2. Description of the Related Art FIG. 7 is a configuration diagram of a conventional phase comparison circuit with a lock detection circuit function. In the figure, reference numeral 21 denotes a Hogge type (Motorola type) phase comparison circuit, 22 denotes a lock detection circuit, 23 denotes a latch circuit, 24 denotes a data signal, 25 denotes a clock signal, 26 denotes a phase comparison output signal, 27 denotes a lock detection output signal, 28 is a D-type flip-flop circuit, 29
Represents a delay circuit.

In the circuit of FIG. 7, the Hogge type phase comparator 21 outputs a pulse signal having a length corresponding to the phase difference between the data signal 24 and the clock signal 25 as a Phase Out signal. When the phase difference of the clock signal 25 is large (in the unlocked state)
Is configured not to output the Phase Out signal as the phase comparison output signal 26 by the latch circuit 23.

FIG. 8 is a timing chart showing signal waveforms at respective nodes in the conventional phase comparator with lock detection circuit function shown in FIG. Symbol (a) in FIG.
To (g) are the respective nodes (a) to in FIG.
This corresponds to the signal waveform of (g).

FIG. 9 shows a circuit configuration of the Hogge type phase comparator 21 in FIG. 7, and FIG. 10 is a timing chart showing signal waveforms at each of the nodes (a) to (d) in FIG.

FIG. 11 shows a specific circuit configuration of the lock detection circuit 22 in FIG. 7, and FIG. 12 is a timing chart showing signal waveforms at each of the nodes (a) to (e) in FIG.

Here, the signal delay τ shown in FIGS. 8 to 12 is caused by a D-type flip-flop circuit which is a component of each circuit. This corresponds to the signal delay per unit. “MS” and “M” in FIGS. 7 to 12 are an abbreviation of Master-Slave and Master, respectively, and refer to a master-slave D-type flip-flop circuit and a master-type D-type flip-flop circuit, respectively. Is represented.

The operation of the conventional phase comparison circuit having a lock detection circuit function shown in FIG. 7 will be described with reference to a timing chart shown in FIG. The lock detection circuit 22 of the conventional phase comparison circuit with a lock detection circuit function shown in FIG.
And the clock signal 25 have a phase difference Δθ of Δθ = 0
The locked state is determined when π / 2 <Δθ <+ π / 2.

First, in the circuit of FIG. 7, the data signal 24 (FIG. 8A) and the clock signal 25 (FIG. 8B) are Hog.
The signals are input to the ge type phase comparison circuit 21 and the lock detection circuit 22, respectively. Here, a case where the frequency of the clock signal 25 is lower than the bit rate of the data signal 24 and the clock signal 25 continues to be delayed with respect to the data signal 24 will be described. The same applies to the case where the clock signal 25 continues to advance with respect to the data signal 24.

The circuit configuration and operation of the Hogge type phase comparator 21 are as shown in FIGS. In the Hogge type phase comparison circuit 21, the phase relationship between each data transition point (rising point and falling point) of the data signal 24 and the falling point of the clock signal 25 is monitored.

Then, a high-level signal having a length proportional to the magnitude of the mutual phase shift (phase difference) is output as an output signal Phase Out indicating a phase delay. (Figure 1
0 (d)) Note that the Hogge type phase comparator 21 is configured as shown in FIG.
, The output signal Phase Out is output with a delay of the signal delay τ with respect to the data transition point of the data signal 24 and the falling point of the clock signal 25. You.

Here, the Hogge type phase comparator 2
In No. 1, since the phase relationship between the data signal 24 and the clock signal 25 is compared using the falling point of the clock signal 25, the phase difference corresponding to the length of the high level signal of the output signal Phase Out is obtained. From the phase difference π between the falling and rising points of the clock signal 25
Is the actual phase difference between the data signal 24 and the clock signal 25, and the phase of the clock signal 25 is delayed with respect to the data signal 24 by the phase difference.

On the other hand, the circuit configuration and circuit operation of the lock detection circuit 22 are as shown in FIGS. The lock detection circuit 22 monitors the positional relationship between each falling point of the data signal 24 and the falling point of the clock signal 25.

When the data signal 24 and the clock signal 25 are in a locked state (phase difference Δθ = 0, the position of the rising point of the data signal coincides with the position of the rising point of the clock signal), Considering that the magnitude of the phase shift between the falling point and the falling point of the clock signal 25 becomes the phase difference π, the magnitude of the mutual phase shift is determined from the phase difference π to the reference value (π / When the value falls within the range (2) (π / 2 <Δθ <3π / 2), a high-level lock detection signal is output as the locked state.

Conversely, a lock is lost, and the magnitude of the mutual phase shift is determined by the phase difference π from the reference value (π /
When the value is out of the range of (2) (π / 2 <Δθ <3π / 2), the lock detection signal becomes low level.

Returning to FIGS. 7 and 8, the output signal of the lock detection circuit 22 is output in response to the falling point of the data signal 25 in either the locked state or the unlocked state. This means that in the specific circuit of FIG.
DELAY1 in which the DELAY2 signal has delayed the data signal
This is because the timing is retimed by the D-type flip-flop circuit in synchronization with the signal. At this time, the output signal of the lock detection circuit 22 is output with a delay of twice (2τ) the signal delay τ from the falling point of the data signal 24. This corresponds to the sum of the delay time of the delay circuit (τ) and the delay time of the D-FF in FIG.

Next, the output signal of the lock detection circuit 22 is input to the data input of the D-type flip-flop circuit 28. On the other hand, the clock signal delayed by the delay circuit 29 is input to the clock input of the D-type flip-flop circuit 28. In the circuit of FIG. 7, the delay circuit 29 operates to delay the phase of the clock signal by π. (FIG. 8E) In the D-type flip-flop circuit 28, the output signal of the lock detection circuit 22 is changed by the falling point of the output signal of the delay circuit 29 (that is, the falling point of the clock signal 25). Retimed and output. (FIG. 8 (f)) At this time,
The output signal of the D-type flip-flop circuit 28 is output with a delay of the above-mentioned signal delay τ with respect to the falling point of the clock signal output as the output signal of the delay circuit 29.

Next, the output signal of the phase comparison circuit 21 is input to the data input of the latch circuit 23, and the output signal of the D-type flip-flop circuit 28 is input to the enable input of the latch circuit 23. In the latch circuit 23, the output signal (FIG. 8C) of the phase comparison circuit 21 is applied to the D-type flip-flop circuit 2.
8 (FIG. 8 (f)).

That is, in the latch circuit 23, the output signal of the D-type flip-flop circuit 28 (FIG. 8)
When (f)) is at a high level (in a locked state)
Is output when the output signal (FIG. 8 (c)) of the phase comparison circuit 21 is passed through as it is, but when the output signal (FIG. 8 (f)) of the D-type flip-flop circuit 28 is at a low level ( In the unlocked state), the output signal (FIG. 8C) of the phase comparison circuit 21 at the time of the data transition point from the high level to the low level is held and output. (FIG. 8 (g)) At this time, the output signal of the latch circuit 23 is output with a delay of the signal delay τ from the output signal of the D-type flip-flop circuit 28. The output signal of the latch circuit 23 becomes the phase comparison output signal 26. The output signal of the lock detection circuit 22 becomes a lock detection output signal 27.

With this circuit configuration, the lock detection circuit 22
In the case where the loss of lock is detected, the output signal of the lock detection circuit 22 first makes a data transition from the high level to the low level, and the output signal of the D-type flip-flop circuit 28 also makes a similar data transition. Wake up.

After the data transition point of the D-type flip-flop circuit 28, the output signal of the latch circuit 23 becomes the phase comparison circuit 2 at the time of the data transition point.
Since the output signal is held at the value of 1, the output of the phase comparison output signal can be stopped while the output signal of the latch circuit 23 is held at a value (high level or low level) representing the delay or advance of the phase. .

[0024]

By the way, as described above, the phase comparison circuit used in the PLL is a Hogge.
Although it is common to use a phase comparison circuit, a so-called Bang-Bang type phase comparison circuit is widely known as the phase comparison circuit.

The details of the Bang-Bang type phase comparison circuit are described in J. A. D. H. Alexander,
“Clock Recovery from Rando
m Binary Signals ", IEEE Ele
ctrons Letters, Vol. 11, pp.
541-542, October 1975.

FIG. 13 is a block diagram showing a Bang-Bang type phase comparator. In the figure, 31 is Bang-Ban
g-type phase comparison circuit, 32a and 32b are D-type flip-flop circuits, 34 is a data signal, 35 is a clock signal,
36 indicates a phase comparison output signal with a phase delay, 37 indicates a phase comparison output signal with a phase advance, and 38 indicates a delay circuit.

In FIG. 13, a Bang-Bang type phase comparison circuit 31 outputs a data signal 34 of a clock signal 35.
In order to output phase delay and advance output signals 36 and 37, respectively, there are two output terminals corresponding to phase delay and phase advance. Then, from each output terminal, a high-level signal having a length obtained by multiplying the length of one cycle of the clock signal by one unit in accordance with the delay or advance of the phase is output.

A D-type flip-flop circuit is generally connected to each of the output terminals of the Bang-Bang type phase comparison circuit 31 after the two output terminals corresponding to the phase advance and phase delay. For this purpose, the use of the D-type flip-flop circuit has two purposes: shaping the waveforms of the phase lag and advance output signals and synchronizing the phase of the phase lag and advance output signals with the clock signal. is there.

Here, considering the case where the Bang-Bang type phase comparator 31 is used as the phase comparator in the conventional circuit of FIG. 7 instead of the conventional Hogge type phase comparator, the configuration shown in FIG. Becomes In FIG. 14, the length of the high-level signal indicating the phase delay or the phase advance output from the Bang-Bang type phase comparison circuit 31 is equal to one cycle of the clock and one cycle of the clock signal with respect to the data to be compared with the clock. (The time required from one falling point to the next falling point), the latch circuit 23 latches the output signal of the phase comparison circuit 31 by the output signal of the lock detection circuit 22 when the loss of lock is detected. In this case, as a timing margin, the entirety of one cycle of the clock signal can be secured.

On the other hand, Hogg as a phase comparison circuit
In the conventional circuit of FIG. 7 using the e-type phase comparison circuit 21, the timing margin when the output signal of the phase comparison circuit 21 is latched by the latch circuit 23 by the output signal of the lock detection circuit 22 as shown in FIG. Inevitably, only a time shorter than one cycle of the clock signal can be secured from the operation principle of the phase comparison circuit.

The difference between the timing margins in such a latch circuit is that when the frequency of the clock signal becomes high, for example, about 10 GHz, the signal period in the D-type flip-flop circuit or the like is changed with respect to the signal cycle. This is important because the delay time becomes so large that it cannot be ignored. That is, when the clock frequency increases, for example, when the clock frequency becomes about 10 GHz, the timing margin in the latch circuit can be increased. Therefore, it is effective to configure a PLL using a Bang-Bang type phase comparison circuit. come.

Therefore, when trying to operate the phase comparison circuit using a high clock frequency, it is conceivable to use a Bang-Bang type phase comparison circuit as the phase comparison circuit as shown in FIG.

However, the phase comparison circuit is simply made Ba
In the case where the ng-Bang type phase comparison circuit is replaced, FIG.
As shown in FIG. 4, two D-type flip-flop circuits 32 are always provided on the output side of the Bang-Bang-type phase comparator.
a and 32b, and two latch circuits 23a and 23b need to be provided at the subsequent stage, which causes a problem that the scale of the entire circuit becomes large.

The present invention has been made in view of the above problems, and even when a phase comparator having a plurality of output terminals such as a Bang-Bang type phase comparator is used, the circuit scale is not increased. It is an object of the present invention to configure a phase comparison circuit with a lock detection function that can stop the output of a phase comparison circuit when a data signal and a clock signal are in an unlocked state.

[0035]

FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a phase comparison circuit, 2 is a lock detection circuit, 3 is a latch circuit, 5 is a data signal, 6 is a clock signal, 7a and 7b are output signals of phase delay and advance of the phase comparison circuit, and 8 is lock. A detection output signal 9 is a first D-type flip-flop circuit, 10a and 10b are second and third D-type circuits for separately retiming output signals corresponding to the phase delay and advance of the phase comparison circuit, respectively. A flip-flop circuit, 11 indicates a first delay circuit, and 12 indicates a second delay circuit.

In FIG. 1, the output signal of the phase comparison circuit is not directly latched or passed through the latch circuit by the lock detection output signal output from the lock detection circuit as in the conventional circuit configuration shown in FIG. , Second and third retiming of the output signal of the phase comparison circuit 1
The clock signal 6 input to the clock inputs of the D-type flip-flop circuits 10a and 10b is latched or passed through in the latch circuit 3 by the lock detection output signal.

That is, as shown in FIG. 1, the clock signal 6 is input to the data input of the latch circuit 3, the output signal of the lock detection circuit 2 is input to the enable input of the latch circuit 3, and the clock signal 6 It is latched or passed through by the output signal of the lock detection circuit 2.

Subsequently, a clock signal output as an output signal of the latch circuit 3 is input to clock inputs of the second and third D-type flip-flop circuits 10a and 10b, and a phase advance of the phase comparison circuit 1 is performed. And the phase-lagged output signals are input to the data inputs of the second and third D-type flip-flop circuits 10a and 10b, respectively.

An output signal obtained by retiming the phase delay and phase advance output signals with the clock signal output from the latch circuit 3 is a phase comparison output signal 7a,
7b.

With this circuit configuration, the latch circuit 3 latches the clock signal 6 for retiming the output signal of the phase comparison circuit 1 by using the output signal of the lock detection circuit 2, so that the conventional circuit shown in FIG. In comparison with the configuration, that is, a configuration in which a latch circuit is independently provided at a subsequent stage of a D-type flip-flop circuit provided for each output terminal of the Bang-Bang type phase comparator, one required latch circuit is provided. Can be reduced to

Therefore, according to the present invention, the number of latch circuits required for the entire circuit can be greatly reduced as compared with the prior art, so that a phase comparison circuit having a plurality of output terminals such as the Bang-Bang type phase comparison circuit is used. Even when a circuit is used, the circuit scale is not increased.

In addition, when the lock detection circuit 2 detects the loss of lock, the output signal of the lock detection circuit 2 inputs the second and third D-type flip-flop circuits 10a and 10b in the latch circuit 3. Since the generation of the clock signal 6 is stopped, the second and third D-type flip-flop circuits 10
The output of the phase comparison detection signals 7a and 7b can be stopped while the output signals a and 10b are held at values indicating the phase delay or the phase advance.

Therefore, according to the present invention, Bang-Ba
Even when a phase comparison circuit having a plurality of output terminals such as an ng-type phase comparison circuit is used, a value representing a phase delay or a phase advance when the data signal and the clock signal are in the unlocked state without increasing the circuit scale. , The output of the phase comparison circuit can be stopped.

[0044]

FIG. 2 is a circuit diagram showing a first embodiment of the present invention. In FIG. 2, a Bang-Bang type phase comparator is used as the phase comparator. In the figure, the same components as those shown in FIG. 1 are denoted by the same symbols. FIG. 3 is a timing chart showing a signal waveform of each node in the first embodiment of the present invention shown in FIG.

Here, the signal delay τ shown in FIG.
This is caused by each D-type flip-flop circuit, and corresponds to a signal delay per one D-type flip-flop circuit. “M” in FIGS. 2, 4 and 6
-S "and" M "are Master-Slave and Ma
This is an abbreviation of “ster”, which indicates a master-slave D-type flip-flop circuit and a master-type D-type flip-flop circuit.

First, before describing the circuit of FIG.
The operating principle of the Bang-Bang type phase comparator will be described with reference to FIG. In the Bang-Bang type phase comparison circuit of FIG. 4, three master slave type D-type flip-flop circuits and one master type D-type flip-flop circuit are divided into two systems and connected in two stages as illustrated. In addition, a logical operation circuit including two EXOR circuits and two AND circuits is connected to the subsequent stage.

FIG. 5 is a timing chart showing signal waveforms at the respective nodes (a) to (i) of the Bang-Bang type phase comparator of FIG.

In FIG. 4, a bang-bang type phase comparison circuit 31 has a data signal 34 and a clock signal 35.
Are respectively input. As the data signal 34, NR
A Z (Non Return to Zero) signal is assumed.

Here, a case where the frequency of the clock signal 35 is lower than the bit rate of the data signal 34 and the clock signal 35 continues to be delayed from the data signal 34 will be described. The same applies to the case where the clock signal 35 is higher than the bit rate of 34 and the clock signal 35 continues to advance with respect to the data signal 34.

First, in the Bang-Bang type phase comparison circuit 31, each data transition point (rising point and falling point) of the data signal 34 (FIG. 5A) and the clock signal 35 (FIG. 5B) Monitor the phase relationship between the falling points.

When the phase difference between the falling point of the clock signal 35 and the data transition point of the data signal 34 is smaller than the phase difference π, the phase of the clock signal 35 lags behind that of the data signal 34. Thus, a high-level signal having a length corresponding to one cycle of the clock signal is output in response to the phase-lagged output signal (FIG. 5 (h)).

On the other hand, the phase difference between the falling point of the clock signal 35 and the data transition point of the data signal 34 is a phase difference π.
If greater, the clock signal 35 becomes the data signal 34
It is determined that the phase is advanced as compared with, and a high-level signal having a length corresponding to one cycle of the clock signal is output for the output signal with the advanced phase (FIG. 5 (i)).

If the falling point of the clock signal 35 and the data transition point of the data signal 34 are out of phase with each other or by π, it is determined that the clock signal 35 and the data signal 34 are inverted or in phase. , Phase-lag and phase-lead output signals (FIGS. 5 (h) and 5 (i)) all output low-level signals.

When the data transition point of the corresponding data signal 34 does not exist within a certain range with respect to the position of the falling point of the clock signal 35, the output signal of the phase delay and the phase advance (FIG. 5) In (h) and (i), a low level signal is output.

Each output signal of phase advance and phase delay (FIG. 5)
In (h) and (i)), when one output is activated, the other is not activated, and when a high-level signal is output on one side, a low-level signal is always output on the other side. Is output. In addition, Bang-Ban
The above-described output operation in the g-type phase comparison circuit 31 is performed in response to the falling point of the clock signal in any case.

According to the above operation principle, Bang
The output signal of phase delay (FIG. 5 (h)) and the output signal of phase advance (FIG.
(I)) is output. In addition, Bang-Ban
Regarding the internal operation of the g-type phase comparison circuit, FIG.
To (g). FIG. 5 (j) shows the data signal 34 corresponding to the clock signal 35 (FIG. 5 (b)).
The phase lead amount in FIG. 5A is shown over time.

Next, based on the operating principle of the above-described Bang-Bang type phase comparator, the first embodiment of the present invention shown in FIG.
The operation of the circuit according to the first embodiment will be described with reference to the timing chart shown in FIG. 3 showing the signal waveform of each node in the first embodiment of the present invention.

First, the data signal 5 (FIG. 3A) and the clock signal 6 (FIG. 3B) are input to the Bang-Bang type phase comparator 1.

The Bang-Bang type phase comparator 1
Detects the data transition point (rising point and falling point) of the data signal 5 and the falling point of the clock signal 6 as described above, and detects each data transition point of the data signal 5 and the clock signal 6. The phase relationship between the falling points of the clock signal 6 is discriminated from the leading or lagging of the two phases, and a high-level signal is output to the falling point of the clock signal 6 with respect to the output signal of the phase delay or the output signal of the phase advance. Output in response. (FIGS. 3C and 3D) At this time, the output signals of the phase delay and the phase advance are output with a delay of the above-mentioned signal delay τ with respect to the falling point of the clock signal 6.

The phase lag output signal (FIG. 3 (c)) and the phase advance output signal (FIG. 3 (d)) of the phase comparison circuit 1
Are input to the data inputs of the second and third D-type flip-flop circuits 10a and 10b, respectively.

On the other hand, the lock detection circuit 2 outputs the data signal 5
(FIG. 3A) and a clock signal 6 (FIG. 3B) are input. Then, the lock detection circuit 2
The lock detection signal 8 (FIG. 3E) is output according to the same operation principle as that of the conventional circuit shown in FIG.

The lock detection circuit 2 detects a falling point of the data signal 5 and a falling point of the clock signal 6 and detects a transition point between each data transition point of the data signal 5 and the falling point of the clock signal 6. Monitor the phase relationship.

When the magnitude of the mutual phase shift falls within the reference value (π / 2) from the phase difference π, the data signal 5 and the clock signal 6 are determined to be in the locked state and have a high level. If the signal is separated by more than the reference value (π / 2), it is determined that the lock has been lost, and a low-level signal is output in response to the falling point of the data signal 5. (FIG. 3E) The output signal of the lock detection circuit 2 becomes the lock detection output signal 8. At this time, the output signal of the lock detection circuit 2 is output with a delay of twice (2τ) the signal delay τ described above with respect to the falling point of the data signal 5.

Next, the output signal of the lock detection circuit 2 (FIG. 3E) and the clock signal (FIG. 3F) delayed by the first delay circuit 11 are applied to a first D-type flip-flop. The data is input to the data input and the clock input of the circuit 9. At this time, the first delay circuit 11
Operates to delay the phase of the clock signal by (π / 2 + α). Here, α may be a phase difference corresponding to the setup time of the D-type flip-flop circuit, for example, α may be set to π / 4.

Then, the output signal (FIG. 3 (e)) of the lock detection circuit 2 is retimed by the clock signal from the first delay circuit 11 in the first D-type flip-flop circuit 9, and Is output as an output signal of the D-type flip-flop circuit 9 of FIG. (FIG. 3 (g)) At this time, the output signal of the first D-type flip-flop circuit 9 corresponds to the falling point of the clock signal output as the output signal of the first delay circuit 11, as described above. Is output with a delay of the signal delay τ.

Next, the clock signal (FIG. 3 (h)) delayed by the second delay circuit 12 and the output signal (FIG. 3 (g)) of the first D-type flip-flop circuit 9 are latched. 3 are input to the data input and the enable input, respectively.

At this time, the second delay circuit 12 operates to delay the phase of the clock signal by (π / 2 + β). Here, the second delay circuit 12 may be set so as to actually delay the signal to the same extent as the first delay circuit, for example, β = π / 4.

In the latch circuit 3, the clock signal (FIG. 3 (h)) from the second delay circuit 12 is output from the lock detection circuit 2 output as the output signal of the first D-type flip-flop circuit 9. 3 (g), and the latched or passed clock signal is output as an output signal of the latch circuit 3. (FIG. 3 (i)) That is, in the latch circuit 3, when the output signal (FIG. 3 (g)) of the first D-type flip-flop circuit 9 is at a high level, the second
The clock signal (FIG. 3 (h)) output as the output signal of the delay circuit 12 is passed through as it is and output, but the output signal of the first D-type flip-flop circuit 9 (FIG. 3 (g)) Is at the low level, the output signal (FIG. 3 (h)) of the second delay circuit 12 at the time of the data transition point from the high level to the low level is held and output.

At this time, the output signal of the latch circuit 3 is output with a delay of the signal delay τ from the output signal of the first D-type flip-flop circuit 9.

Next, the clock signal (FIG. 3 (i)) from the latch circuit 3 is input to the clock inputs of the second and third D-type flip-flop circuits 10a and 10b. Then, the phase-lagged output signal (FIG. 3C) and the phase-leaded output signal (FIG. 3D) of the phase comparator 1 are generated by the clock signal (FIG. 3I) latched or passed through by the latch circuit 3. )) Are retimed respectively. (FIGS. 3 (j) and (k)) The output signals of the second and third D-type flip-flop circuits 10a and 10b become the phase comparison output signals 7a and 7b.

At this time, each phase comparison output signal 7
The signals a and 7b are output with a delay of the signal delay τ with respect to the falling point of the clock signal output as the output signal of the latch circuit 3.

Here, the circuit operation of the first embodiment of the present invention shown in FIG. 2 when the lock is released in the lock detection circuit 2 and when the lock is released is described.

When the lock detection circuit 2 loses lock, first, the output signal of the lock detection circuit 2 causes a data transition from a high level to a low level in the timing chart of FIG. ((E) of FIG. 3) Next, similar data transition occurs in the output signal of the first D-type flip-flop circuit 9 due to the data transition of the output signal of the lock detection circuit 2. 3 (g)) Then, due to the data transition of the output signal of the first D-type flip-flop circuit 9, the output signal of the latch circuit 3 changes to the second delay circuit 12 at the data transition point. , And the generation of the clock signal in the latch circuit 3 is stopped (FIG. 3 (i)). The value of the output signal of the third D-type flip-flop circuit 10a, 10b is held at the value before the stop of the clock signal, and the phase advance in the second and third flip-flop circuits 10a, 10b is performed. And the generation of the output signal of the phase delay stops (FIG. 3 (j),
(FIG. 3 (k)) On the other hand, if the lock detection circuit 2 releases the lock release and returns to the locked state again, first, in the timing chart of FIG. 3, the output signal of the lock detection circuit 2 changes from low level to high level again. Cause data transition. ((E) of FIG. 3) Next, similar data transition occurs in the output signal of the first D-type flip-flop circuit 9 due to the data transition of the output signal of the lock detection circuit 2. 3 (g)) Next, due to the data transition of the output signal of the first D-type flip-flop circuit 9, the latch circuit 3 is enabled and the clock signal from the second delay circuit 12 is passed again. As a result, the clock signal is generated again in the output signal of the latch circuit 3 (FIG. 3).
(I)) With the re-generation of the clock in the latch circuit 3, the second and third D-type flip-flop circuits 10a,
The output signal of 10b is again the output signal of the phase advance circuit (FIG. 3C) and the output signal of the phase delay (FIG.
(D)) are respectively retimed signals, and again the second and third D-type flip-flop circuits 10a, 10a,
By b, the phase comparison output signals 7a and 7b are output. (FIG. 3 (j)), (FIG. 3 (k)) As described above, according to the circuit configuration of the first embodiment of the present invention, the lock detection circuit 2 detects the loss of lock and the data signal 5 When the clock signal 6 and the clock signal 6 are unlocked, the phase comparison output signals 7a and 7a are held while maintaining the values (high level) representing the phase delay or the phase advance.
The output of b can be stopped.

In addition, as is apparent from the circuit configuration of FIG. 2, in the first embodiment of the present invention, since the number of required latch circuits is one, it is necessary to increase the scale of the entire circuit. Can be prevented.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention. In the drawing, the same components as those shown in FIGS. 1 and 2 are denoted by the same symbols, 13 represents a first delay circuit, and 14 represents a second delay circuit. A Bang-Bang type phase comparison circuit is also used in the phase comparison circuit in the circuit shown in FIG.

The circuit configuration of FIG. 6 is substantially the same as the circuit configuration of FIG. 2, but in the circuit configuration of FIG. 2, the first delay circuit 11 and the second delay circuit 12 4, the second delay circuit 14 is connected in series at the subsequent stage of the first delay circuit 13 in the circuit configuration of FIG.

In the circuit configuration of FIG. 6, the first delay circuit 13
Operates to delay the phase of the clock signal input to the clock input of the first D-type flip-flop circuit 9 by (π / 2 + α), as in the case of the circuit of FIG. On the other hand, the second delay circuit 14 is operated to delay by (π / 2 + β) in the case of the circuit of FIG.
In the circuit configuration of FIG. 2, the difference of the phase difference to be delayed between the second delay circuit 12 and the first delay circuit 11 in FIG.
α).

The operation of the circuit according to the second embodiment of the present invention shown in FIG. 6 is the same as that of the first embodiment shown in FIG. 2, and therefore, the first embodiment The same effect as in the case of can be obtained.

Further, in the circuit configuration shown in FIG. 6, two delay circuits are separately arranged. Instead, only one delay circuit is arranged, and the phase difference delayed from one delay circuit is different. It is also possible to output three output signals.

In the first and second embodiments of the present invention, the D-type flip-flop circuit, the lock detection circuit, and the phase comparison circuit mainly operate at the falling point. However, the present invention is not limited to this, and it goes without saying that a D-type flip-flop circuit, a lock detection circuit, and a phase comparison circuit that operate at the rising point can be used.

[0081]

As described above, according to the present invention,
Regarding a phase comparison circuit with a lock detection function, a latch circuit uses an output signal of a lock detection circuit to latch or through a clock signal for retiming an output signal of the phase comparison circuit in a D-type flip-flop circuit. Make up. Therefore, in the present invention, the number of latch circuits required for the entire circuit can be reduced.

Therefore, even when a phase comparator having a plurality of output terminals, such as a Bang-Bang type phase comparator, is used, when the data signal and the clock signal are in the unlocked state without increasing the circuit scale, The output of the phase comparison circuit can be stopped while holding the value indicating the delay or the phase advance, which greatly contributes to the improvement of the performance of the phase comparison circuit.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention,

FIG. 2 is a circuit configuration diagram according to the first embodiment of the present invention;

FIG. 3 is a timing chart showing a signal waveform of each node according to the first embodiment of the present invention;

FIG. 4 is a specific circuit configuration diagram of a Bang-Bang type phase comparator;

FIG. 5 is a timing chart showing signal waveforms at each node of the Bang-Bang type phase comparator;

FIG. 6 is a circuit configuration diagram according to a second embodiment of the present invention;

FIG. 7 is a configuration diagram of a conventional phase comparison circuit with a lock detection function,

FIG. 8 is a timing chart showing signal waveforms at each node of a conventional phase comparison circuit with a lock detection circuit function;

FIG. 9 is a specific circuit configuration diagram of a Hogge (Motorola) phase comparison circuit;

FIG. 10 is a timing chart showing signal waveforms at respective nodes of the Hoge-type phase comparator;

FIG. 11 is a specific circuit configuration diagram of a lock detection circuit;

FIG. 12 is a timing chart showing a signal waveform of each node of the lock detection circuit;

FIG. 13 is a configuration diagram of a Bang-Bang type phase comparison circuit;

FIG. 14 is a circuit configuration diagram in the case where a Bang-Bang type phase comparator is used instead of a Hogge type phase comparator as a phase comparator;

[Explanation of symbols]

 Reference Signs List 1 phase comparison circuit, 2 lock detection circuit, 3 latch circuit, 5 data signal, 6 clock signal, 7 phase comparison output signal, 8 lock detection output signal 9 first D-type flip-flop circuit, 10a second D-type flip-flop 10b Third D-type flip-flop circuit, 11 first delay circuit, 12 second delay circuit, 13 first delay circuit, 14 second delay circuit, 21 phase comparison circuit, 22 lock detection circuit , 23 latch circuit, 24 data signal, 25 clock signal, 26 phase comparison output signal, 27 lock detection output signal 28 D-type flip-flop circuit, 29 delay circuit, 31 Bang-Bang type phase comparison circuit, 32 a D-type flip-flop circuit , 32b D-type flip-flop circuit, 34 data signal, 35 clock signal, 36 phase delay position Comparison output signal, 37 a phase advanced phase comparison output signal of 38 delay circuits

Claims (2)

[Claims] A phase comparison circuit that receives a data signal and a clock signal, performs a phase comparison between the data signal and the clock signal, and outputs a comparison output signal indicating a delay or advance of a phase; A lock detection circuit that receives a clock signal, detects whether the phase difference between the clock signal and the data signal is smaller than a predetermined value, and outputs a detection output signal indicating a locked or unlocked state. The clock signal is input, the detection output signal is input to an enable input, the clock signal is passed when the detection output signal indicates a locked state, and the clock signal is output when the detection output signal indicates an unlocked state. And a latch circuit for preventing the passage of the comparison output signal, a data input for receiving the comparison output signal, and a clock input for outputting the output of the latch circuit. No. is input, D-type flip-flop circuit and the lock detecting function phase comparison circuit, characterized in that it comprises a for outputting an output signal retiming said comparison output signal by the output signal of the latch signal. 2. The phase comparison circuit according to claim 1, wherein said phase comparison circuit is a Bang-Bang type phase comparison circuit.