JPS62256033A - Memory circuit - Google Patents

Abstract

PURPOSE:To easily constitute a memory circuit to make synchronize two signals having the same bit rates on the average, with the clock of the signal on one side, and to make a process into high speed, by using a voltage controlled type oscillation circuit for the initialization of the readout counter of a memory. CONSTITUTION:By comparing the operating phases of a write counter 5, and a readout counter 7 at a phase comparison circuit 8, a voltage controlled type oscillation circuit 9 changes a frequency of output clock (k) so as to set a phase difference appropriately. After signals A and B are inputted to the memory circuit, a PLL circuit including the oscillation circuit 9, etc., performs a phase adjustment between the write counter 5, and the readout counter 7. And after the lapse of a time required for the phase adjustment, a reading out clock (rc) is switched the clock (cb) of the signal B at a readout clock switching circuit 11 by a timer circuit 10, and after that, the write counter 5 is operated by the clock (cb) of the signal B, and the data (da) of the signal A is read out as the data synchronized with the clock (cb) of the signal B. Also, a switching means between the third clock (k) and the clock (cb) of the second signal B consists of the switching circuit 11, and the timer circuit 10.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory circuit in the field of digital communications, and particularly to a memory circuit for synchronizing two signals having the same average bit rate with the clock of one signal. The present invention relates to a memory circuit.

[Conventional technology]

In such a conventional memory circuit, data da of a signal A from a terminal 1 is synchronized with a clock cb of a signal B from a terminal 4, for example, as shown in FIG.

When the data da of the signal person and the clock Ca of the signal A are input from terminals 1 and 2, respectively, the clock C of the signal A
The data da of the signal A is written to the memory 60 location corresponding to the state of the write counter 5 operated by the signal A.

On the other hand, the clock cb of the signal B is applied to the readout counter 7 from the terminal 4, and the data dab of the signal A synchronized with the signal BK is sent from the memory 6 from the terminal 3 as the output data of the memory circuit in accordance with the read counter 7. Read out.

However, even if the signal A and signal B have the same bit rate on average, they differ transiently, so the write counter 5 operating with the signal person's clock Ca determines the location of the memory 6 to be written. , the position of the memory 6 read out by the read counter 7 operated by the clock cb of the signal B repeatedly moves away from and approaches the position of the memory 6, and in extreme cases, the position of the memory 6 is repeatedly moved away from and approached by the write counter 5.
Read the data once read by the read counter 7,
It may happen that the write counter 5 is rewritten with new data before the read counter reads the data.

To prevent this, clocks ca and cb of signal A and signal B should be
It is necessary to use a memory with a sufficient number of bits to absorb fluctuations in the number of bits, and to adjust the phases of the write counter and read counter appropriately.

Therefore, the operating phase of the write counter 5 and the read counter 7 is detected by the phase comparison circuit 8, and the phase judgment circuit 12
It is determined whether the phase needs to be adjusted or not, and the clock stop circuit 14 repeatedly stops the clock cb of the signal B bit by bit every 130 cycles of the timer circuit until the phase adjustment is completed.

[Problem that the invention seeks to solve]

The conventional memory circuit described above has a memory read counter of 1. The phase comparison between the write counter and the read counter is performed by delaying the pit until the phase of both counters is A.
Since this process is repeated until the period is shifted, there is a drawback that the time required to synchronize the two signals with the clock of one signal becomes long.

An object of the present invention is to use a voltage-controlled oscillator circuit for initializing a memory read counter, and to synchronize two signals having the same pit rate on average with the clock of one signal. We aim to provide a system circuit that can be easily and quickly operated.

[Means for solving problems]

A memory circuit of the present invention writes data of a first signal to a memory using a clock of the first signal, and reads data of the first signal written to the memory using a second clock. The clock of the first signal is set to the second clock for reading, 'i
'o Depending on the phase difference 10. ,,,=,j An oscillation circuit that sends out a third clock whose frequency changes, and an oscillation circuit that sends out a third clock whose frequency changes, and
It is characterized by comprising a switching means that transmits the clock of the second signal and then switches to and transmits the clock of the second signal. Therefore, it is possible to easily and quickly synchronize two signals having the same pit rate on average to one of the signals.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment according to the present invention. As shown in FIG. 1, an input terminal 1 for data da of the first signal A and an input terminal 2 for the clock Ca of the signal A are connected to the memory 6 via the write counter 5. A counter 7 and an output terminal 3 for memory circuit output data are connected.

A write counter 5 and a read counter 7 are connected to a phase comparator circuit 8, and the comparator circuit 80 is connected so that a phase difference signal is outputted to a voltage damped oscillation circuit 9.

The read clock switching circuit 11 includes an input terminal 4 for inputting the clock cb of the second signal B and a timer circuit 10.
is connected, the output of the voltage-controlled oscillation circuit 9 is input, and the second clock re for successive reading is output to the read counter 7.

In the above-mentioned embodiment, the second clock rc input to the readout clock rc is applied to the third clock of the voltage-controlled oscillation circuit 9 until the phase adjustment between the write counter 5 and the read counter 7 is completed.
The second signal B is added to the clock signal Cb only after the phase adjustment is completed.

Next, the operation will be explained. When the operating phases of the write counter 5 and the read counter 7 are compared by the phase comparison circuit 8, the voltage controlled oscillation circuit 9 changes the frequency of the output clock so that the phase difference becomes appropriate.

After a time period of Km has elapsed since signals A and B are input to the memory circuit, the PLL circuit including the oscillation circuit 9 adjusts the phase between the write color/return 5 and the read counter 7. After the circuit 10 switches the read clock rc to the clock cbK of the signal B in the continuous clock switching circuit 11, the write counter 7 switches to the clock cbK of the signal B.
The data da of the signal person is read out as data d synchronized with the clock cbK of the signal B.

Note that the switching circuit 11 and the timer circuit 10 constitute means for switching between the third clock and the clock cb of the second signal B.

〔Effect of the invention〕

As explained above, the present invention synchronizes two signals having the same bit rate on average with the clock of one signal by using a voltage-controlled oscillator circuit for the initial setting of a memory read counter. This has the effect that the memory circuit can be configured easily and at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a block diagram showing a conventional example. 1...Data input terminal, 2...Clock input terminal, 3...Data output terminal, 4...Clock input terminal, 5...Write counter, 6...Member
Memory, 7... Readout counter, 8... Phase comparison circuit. 9...Voltage controlled oscillation circuit, 10...Tie
Ma circuit, 11... Read clock switching circuit.

Claims (1)

[Scope of Claim] In a memory circuit that writes data of a first signal to a memory using a clock of the first signal, and reads data of the first signal written to the memory using a second clock. , an oscillation circuit that sends out a third clock whose frequency changes according to a phase difference between the first signal clock and the second reading clock, and the second reading clock; A memory circuit characterized in that it is provided with a switching means that first transmits the third clock and then switches to and transmits the clock of the second signal.