JP2005056975A - Magnetic memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a magnetic memory device wherein processing is eased and wiring is protected during manufacturing and that is provided with a highly reliable wiring structure, and to provide its manufacturing method. <P>SOLUTION: The upper surfaces of lower layer wirings 33 and 34 in a peripheral circuit B are covered with the same material as at least the base metal layer 26a of a pin layer 26 comprising a TMR device 10, so that the lower layer wirings 33 and 34 can be protected during etching when the device is divided, and they are hard to be exposed. Therefore, the wiring resistance of the lower layer wiring can be kept lower, and connection with the upper layer wiring is made appropriate, and furthermore a copper as wiring material can be prevented from being dispersed upward or downward. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  In the present invention, a magnetic memory element is constituted by a tunnel magnetoresistive effect element formed by laminating a magnetization fixed layer with a fixed magnetization direction, a tunnel barrier layer, and a magnetic layer capable of changing the magnetization direction. A magnetic memory device having a memory part composed of memory elements and a peripheral circuit part of the memory part, in particular a magnetic random access memory, a magnetic memory device configured as a so-called nonvolatile memory MRAM (Magnetic Random Access Memory), and It relates to the manufacturing method.

  With the rapid spread of information communication devices, especially small personal devices such as mobile terminals, the elements such as memory and logic that make up these devices have higher performance such as higher integration, higher speed, and lower power consumption. Is required.

  In particular, increasing the density and capacity of non-volatile memories is becoming increasingly important as a technology for replacing hard disks and optical disks that are essentially impossible to downsize due to the presence of moving parts.

  Examples of the nonvolatile memory include a flash memory using a semiconductor and an FRAM (Ferroelectric Random Access Memory) using a ferroelectric.

  However, the flash memory has a drawback that it is difficult to achieve high integration due to its complicated structure, and the access time is as slow as about 100 ns. On the other hand, in FRAM, a problem that the number of rewritable times is small has been pointed out.

  For example, Wang et al., IEEE Trans. Magn. 33 (1997), 4498 are attracting attention as non-volatile memories with high speed, large capacity (high integration), and low power consumption. Is a magnetic memory called MRAM (Magnetic Random Access Memory) or MR (Magnetoresistance) memory, and has been attracting attention due to the recent improvement in properties of TMR (Tunnel Magnetoresistance) materials. ing.

  In addition, since the MRAM has a simple structure, it can be easily integrated, and since the recording can be performed by rotating the magnetic moment, the number of rewrites is large, and the access time is very high. Expected.

  As described above, the TMR element used in MRAM attracting attention in recent years has a structure in which a tunnel oxide film is sandwiched between two magnetic layers, and flows through the tunnel oxide film depending on the spin direction of the two magnetic layers. It is used as a memory element by utilizing the fact that the current intensity changes.

  Describing in more detail about such an MRAM, as illustrated in FIG. 13, a TMR element 10 serving as a memory element of an MRAM memory cell is a memory layer provided on a support substrate 9 and having a magnetization that rotates relatively easily. 2 and the magnetization fixed layers 4 and 6.

  The magnetization fixed layer has two magnetization fixed layers of a first magnetization fixed layer 4 and a second magnetization fixed layer 6, and a conductor layer in which these magnetic layers are antiferromagnetically coupled between them. 5 is arranged. The memory layer 2 and the magnetization fixed layers 4 and 6 are made of a ferromagnetic material made of nickel, iron, cobalt, or an alloy thereof, and the material of the conductor layer 5 is ruthenium, copper, chromium, gold, silver Etc. can be used. The second magnetization fixed layer 6 is in contact with the antiferromagnetic material layer 7, and the second magnetization fixed layer 6 has a strong unidirectional magnetic anisotropy due to the exchange interaction acting between these layers. . As a material for the antiferromagnetic material layer 7, manganese alloys such as iron, nickel, platinum, iridium, and rhodium, cobalt, nickel oxide, and the like can be used.

  In addition, a tunnel barrier layer 3 made of an insulator made of an oxide or nitride such as aluminum, magnesium, or silicon is sandwiched between the storage layer 2 that is a magnetic layer and the first magnetization fixed layer 4. In addition to cutting off the magnetic coupling between the storage layer 2 and the fixed magnetization layer 4, it plays a role for flowing a tunnel current. Although these magnetic layers and conductor layers are mainly formed by sputtering, the tunnel barrier layer 3 can be obtained by oxidizing or nitriding a metal film formed by sputtering. The topcoat layer 1 has a role of preventing mutual diffusion between the TMR element 10 and wiring connected to the TMR element, reducing contact resistance, and preventing oxidation of the memory layer 2, and is usually made of a material such as Cu, Ta, or TiN. Can be used. The base electrode layer 8 is used for connection with a switching element connected in series with the TMR element. The underlayer 8 may also serve as the antiferromagnetic layer 7.

  In the memory cell configured as described above, as described later, information is read out by detecting a tunnel current change due to the magnetoresistive effect, and the effect depends on the relative magnetization directions of the storage layer and the magnetization fixed layer.

  FIG. 14 is an enlarged perspective view showing a part of a general MRAM in a simplified manner. Here, the read circuit portion is omitted for simplification, but includes, for example, nine memory cells, and has a bit line 11 and a write word line 12 that intersect each other. The TMR element 10 is disposed at these intersections, and writing to the TMR element 10 causes a current to flow through the bit line 11 and the write word line 12, and the bit line 11 is generated by a combined magnetic field generated therefrom. Is written with the magnetization direction of the storage layer 2 of the TMR element 10 at the intersection of the write word line 12 parallel or antiparallel to the magnetization fixed layer.

  FIG. 15 schematically shows a cross section of the memory cell. For example, a gate insulating film 15, a gate electrode 16, and a source region 17 formed in a p-type well region 14 formed in a p-type silicon semiconductor substrate 13. The n-type read field effect transistor 19 including the drain region 18 is disposed, and the write word line 12, the TMR element 10, and the bit line 11 are disposed thereon. A sense line 21 is connected to the source region 17 through a source electrode 20. The field effect transistor 19 functions as a switching element for reading, and a read wiring 22 drawn from between the word line 12 and the TMR element 10 is connected to the drain region 18 via the drain electrode 23. The transistor 19 may be an n-type or p-type field effect transistor, but various switching elements such as a diode, a bipolar transistor, and a MESFET (Metal Semiconductor Field Effect Transistor) can be used.

  FIG. 16 shows an equivalent circuit diagram of the MRAM, which includes, for example, six memory cells, has a bit line 11 and a write word line 12 intersecting each other, and a storage element is formed at the intersection of these write lines. 10 includes a field effect transistor 19 and a sense line 21 which are connected to the memory element 10 and perform element selection at the time of reading. The sense line 21 is connected to the sense amplifier 23 and detects stored information. In the figure, 24 is a bidirectional write word line current drive circuit, and 25 is a bit line current drive circuit.

FIG. 17 is an asteroid curve showing the write condition of the MRAM, and shows the reversal threshold value of the storage layer magnetization direction by the applied easy axis magnetic field _HEA and hard axis magnetic field _HHA . When a corresponding synthetic magnetic field vector is generated outside the asteroid curve, magnetic field reversal occurs, but the synthetic magnetic field vector inside the asteroid curve does not invert the cell from one of its current bistable states. Also in cells other than the intersections of word lines and bit lines are a current flows, a magnetic field generated by the word line or bit line alone is applied, if their size is more than one direction reversal magnetic field H _K Since the magnetization direction of the cells other than the intersection is also reversed, the selected cell can be selectively written only when the combined magnetic field is in the gray region in the figure.

As described above, in the MRAM, by using the two write lines of the bit line and the word line, only the designated memory cell is selectively written by the reversal of the magnetic spin using the asteroid magnetization reversal characteristic. It is common. Synthetic magnetization in a single storage area is determined by the vector combination of the magnetization hard axis magnetic field H _HA and the magnetization easy axis magnetic field H _EA applied thereto. The write current flowing through the bit line, the magnetic field H _EA easy magnetization axis direction is applied to the cell, and the current flowing through the word line applies a magnetic field H _HA hard magnetization axis direction cell.

  FIG. 18 explains the read operation of the MRAM. Here, the layer configuration of the TMR element 10 is schematically illustrated, the above-described magnetization fixed layer is shown as a single layer 26, and the components other than the storage layer 2 and the tunnel barrier layer 3 are not illustrated.

  That is, as described above, the information is written by inverting the magnetic spin of the cell by the combined magnetic field at the intersection of the bit line 11 and the word line 12 wired in a matrix and changing the direction to “1”, “0”. Record as information. The reading is performed using the TMR effect applying the magnetoresistive effect. The TMR effect is a phenomenon in which the resistance value changes depending on the direction of the magnetic spin, and the magnetic spin is antiparallel and has a high resistance state. Information “1” and “0” are detected based on a low resistance state in which the magnetic spins are parallel. In this read, a read current (tunnel current) is passed between the word line 12 and the bit line 11 and an output corresponding to the level of the resistance is read to the sense line 21 via the read field effect transistor 19 described above. Do by.

  A conventional method for forming an MRAM will be briefly described with reference to FIGS.

  FIG. 19A shows an interlayer insulating film made of a silicon oxide film having a thickness of T (400 nm), for example, on a substrate (not shown) on which a Tr (transistor) formed using CMOS technology and a wiring layer are formed. The word line 123 and the read line 123 are formed with a wiring width W (260 nm) and an interval L (280 nm) in the memory portion A in the region 31, and the lower layer wirings 33 and 34 have a wiring width of the peripheral circuit portion B. It is formed in W (260 nm).

A diffusion prevention film 32 made of a silicon nitride film for preventing diffusion of copper ions in the wiring is interposed between the word line 12 and the lower layer wirings 33 and 34 of the peripheral circuit portion B and the upper interlayer insulating film 35. However, the upper wiring 123a formed by opening the interlayer insulating film 35 by etching is connected to the read line 123, and Ta / PtMn / CoFe (second pinned layer) / Ru / CoFe (first pin) is connected to the upper surface thereof. The TMR element 10 is formed after the pin layer 26 including the layer), the tunnel barrier layer 3 including Al ₂ O _3, and the TMR element material including the free layer 2 including CoFe-30B (free layer) / Ta are stacked. In order to do this, a state is shown in which the free layer 2 and the tunnel barrier layer 3 other than those above the word line 12 are removed by etching.

  In addition, in each part, Cu plating of the wiring to the connection hole is provided with a barrier film made of Ta or the like, for example, and a Cu diffusion preventing device is made by the damascene method using this barrier film as a seed metal (FIG. 22B). Reference) is omitted.

  In FIG. 19B, the TMR element 10 and the readout line 123 are connected by a wiring 22 made of a base metal layer (Ta or the like) of the pinned layer 26, and the readout line is connected by a lower layer metal (eg Ta) of the pinned layer 26. In order to isolate the memory cell from the memory cell including the word line 12 and the TMR element 10 to which the read line 123 is connected by the wiring 22 after the 123 is formed so as to prevent diffusion of Cu upward. In addition, a resist mask 36 is formed on the pinned layer 26, and the adjacent memory cells are divided (separated) by etching.

  However, the pinned layer 26 in the non-mask portion is also removed at the time of this division, and at the same time, the peripheral circuit portion B which is an open space easily reacts with the reactive gas. Etching up to (virtual line portion).

  FIG. 20 (c) shows a state after removing the resist mask, and FIG. 20 (d) shows that an interlayer insulating film 40 and a diffusion preventing film 41 are laminated thereon, and a connection hole (not shown) is formed thereon. After the formation, the connection hole is filled by Cu plating to form the contact plug 12a for connecting the TMR element 10 of the memory part A and the bit line, and to connect the bit line on one lower layer wiring 33 of the peripheral circuit part B In this case, the contact plug 33a is formed and the upper wiring 34a is formed on the other lower wiring 34 in the peripheral circuit portion B.

  In FIG. 21E, an interlayer insulating film 42 and a diffusion preventing film 43 are laminated on this, and then a resist mask (not shown) is formed and patterned to form a bit line region and a peripheral circuit portion B. A connection hole is formed on the upper wiring 34a, and the connection hole on the bit line region and the upper wiring 34 is buried by Cu plating, and the contact plug 34b is formed on the formation of the bit line 11 and the upper wiring 34a of the peripheral circuit portion B. Is formed.

  Thereby, the contact plug 33 a connected to the contact plug 12 a of the memory part A and the lower layer wiring 33 of the peripheral circuit part B is connected to the bit line 11. In addition, a connection terminal for connecting the upper wiring 34a continuous with the other lower wiring 34 of the peripheral circuit portion B to an external device or the like is formed.

  As an example of the MRAM, it has been proposed to reduce the chip area by configuring the memory unit with TMR elements and using the TMR elements as resistance elements, fuse elements, or contacts in the peripheral circuit region (described later). Patent Document 1).

JP 2002-359356 A (page 7, column 12, line 47 to page 8, column 13, line 3 and FIG. 1)

  In order for the MRAM to operate efficiently, it is necessary to apply a sufficient synthetic magnetic field to the TMR element 10 by the bit line and the word line. Therefore, as shown in FIG. 22, the distance between the word line 12 and the pinned layer 26 should be small. For this purpose, the thickness of the lower insulating layer 35 should be as small as possible in order to increase the magnetic field. However, the over-etching of the metal layer used for the lower layer of the pinned layer 26 described above causes the ground of the open space of the peripheral circuit portion B other than the memory portion A to be scraped. Easy to be exposed.

When Cu is exposed in this way, corrosion with Cl ₂ (chlorine) gas that is usually used for etching the above-mentioned base metal layer (for example, Ta, PtMn, etc.) becomes a problem. When the wiring layer is etched, there is a problem that the wiring resistance varies and causes a defect such as a short circuit between wirings due to scattered Cu. Therefore, since the pinned layer 26 cannot be thinned, it cannot be avoided that the synthetic magnetic field becomes weak.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a magnetic memory device capable of protecting the lower layer wiring of the peripheral circuit portion and improving its reliability, and a method for manufacturing the same. There is to do.

That is, in the present invention, a magnetic memory element is constituted by a tunnel magnetoresistive effect element in which a magnetization fixed layer with a fixed magnetization direction, a tunnel barrier layer, and a magnetic layer capable of changing the magnetization direction are stacked. In a magnetic memory device having a memory unit composed of the magnetic memory element and a peripheral circuit unit of the memory unit,
A lower layer wiring of the peripheral circuit section is covered with the same constituent material as at least a part of the metal layer constituting the magnetization fixed layer and the underlying conductive layer. It may be referred to as a memory device of the invention).

Further, according to the present invention, a magnetic memory element is constituted by a tunnel magnetoresistive effect element formed by stacking a magnetization fixed layer with a fixed magnetization direction, a tunnel barrier layer, and a magnetic layer capable of changing the magnetization direction. In a method of manufacturing a magnetic memory device having a memory unit composed of a magnetic memory element and a peripheral circuit unit of the memory unit,
Forming the lower layer wiring in the peripheral circuit portion;
Laminating each constituent material of the underlying conductive layer of the magnetization fixed layer, the magnetization fixed layer, the tunnel barrier layer, and the magnetic layer in this order on the memory unit including the lower layer wiring;
And a step of patterning at least a part of the metal layer constituting the magnetization fixed layer and the base conductive layer so as to cover the lower layer wiring, and forming the magnetic memory element. The present invention relates to a device manufacturing method (hereinafter referred to as a manufacturing method of the present invention).

  According to the present invention, since the lower layer wiring is protected by the metal material covering the lower layer wiring of the peripheral circuit portion, it is possible to prevent the lower layer wiring from being exposed by etching in the manufacturing process. Even if it does not exist or its film thickness is small, the lower layer wiring does not corrode, and it is possible to form good wiring with low contact resistance, resulting in a layer structure that can strengthen the synthetic magnetic field Therefore, it is possible to obtain a magnetic memory device that can achieve the above. In addition, the metal material on the lower layer wiring of the peripheral circuit portion can be easily formed without adding a process simultaneously with the etching for dividing the memory element.

  In the above-described magnetic memory device and manufacturing method of the present invention, the upper layer wiring (upper wiring) connected to the lower layer wiring of the peripheral circuit section is connected to the bit line of the magnetic memory element, and the magnetic memory element In this case, only an insulating diffusion prevention film for preventing diffusion of the constituent metal elements of the word line exists between the word line disposed on the opposite side of the bit line and the base conductive layer. It is desirable in that it can strengthen the magnetic field.

  In this case, it is preferable that a read line connected to the base conductive layer is embedded in the insulating layer in which the word line is embedded, and a lower layer wiring of the peripheral circuit portion is embedded in the insulating layer.

  Further, the connection of the bit line to the magnetic memory element and the formation of the upper layer wiring may be performed through an insulating layer.

  Furthermore, it is desirable that the lower layer wiring, the word line, and the read line are made of copper or a copper alloy in terms of good conductivity.

  An insulator layer or a conductor layer is sandwiched between the magnetization pinned layer and the magnetic layer, and currents are passed through the bit line and the word line provided on the upper surface and the lower surface of the memory element, respectively. A magnetic memory device is suitably configured by writing information by magnetizing the magnetic layer in a predetermined direction with an induced magnetic field and reading out the written information by a tunnel magnetoresistance effect through the tunnel barrier layer. Can be formed.

  Next, the best mode for carrying out the present invention will be specifically described with reference to the drawings.

Embodiment 1
FIG. 1 is a schematic cross-sectional view of the MRAM according to the present embodiment. A three-layer interlayer insulating film (hereinafter simply referred to as an insulating film) consisting of a lower layer, an intermediate layer, and an upper layer on a substrate (not shown). 31, 35, and 42 are stacked with the diffusion prevention films 32 and 41 interposed therebetween, and in the memory portion A, the word line 12 and the read line 123 arranged on the lower insulating film 31, and the diffusion prevention A memory cell including the TMR element 10 connected to the read line 123 by the wiring 22 on the film 32 is formed.

  The TMR element 10 is connected to the upper bit line 11 via the contact plug 12a, and one lower layer wiring 33 of the peripheral circuit portion B is connected to the contact plug 33a with the cap 45 interposed therebetween. The contact plug 33a is connected to the bit line. 11 is connected. Similarly, an upper wiring 34a is formed on the other lower wiring 34 of the peripheral circuit portion B with a cap 45 interposed therebetween, and is further connected to a contact plug 34b. An external device is connected to the diffusion preventing film 43 on the upper insulating film 42. Etc. are formed for connection to the terminals.

  In the present embodiment, the wiring 22 that connects the TMR element 10 and the readout line 123 is formed by using the pinned layer 26 that constitutes the TMR element 10, as in the conventional case. The insulating film 35 is selectively removed (omitted) and the TMR element 10 is disposed on and in contact with the diffusion preventing film 32. Further, at least tantalum (described later) which is a base metal layer of the pinned layer 26 is used. The same material as that of the laminated structure composed of platinum and manganese alloy layer 26a is formed as a cap 45 covering the lower layer wirings 33 and 34 of the peripheral circuit portion B over the entire width and length, and each contact plug or upper wiring is formed thereon. It is a notable feature of the present embodiment that is formed.

The TMR element 10 includes Ta (tantalum) (3) / PtMn (platinum / manganese alloy) (30) / CoFe (cobalt / iron alloy) (2.4) / Ru (ruthenium) (0.75) / CoFe ( Cobalt / iron alloy) (2.2) / Al ₂ O ₃ (aluminum oxide) (1.5) / CoFe (cobalt / iron alloy) -30B (4) / Ta (tantalum) (5) (however, figures in parentheses) Indicates a film thickness (unit: nm)). Here, reference numeral 2b in FIG. 1 is Ta, which is the uppermost layer to be a metal electrode, 2a is CoFe-30B, 3 is a tunnel barrier layer (Al ₂ O ₃ ), 26b is CoFe / Ru / CoFe, 26a is Ta / Although PtMn is shown, in the following description, 2a and 2b are collectively referred to as the free layer 2, and 26a and 26b are collectively referred to as the pinned layer 26.

  In particular, in order to prevent Cu embedded in the connection hole from being exposed and degenerated when patterning is performed by RIE (reactive ion etching), the lower wirings 33 and 34 of the peripheral circuit portion B are formed on the upper side as described above. The structure is covered with a metal layer (cap layer) 45.

  In addition, the cap layer 45 can confine copper ions in the lower layer wiring made of copper or a copper alloy (hereinafter referred to as Cu), and in particular, can prevent diffusion upward, and the TMR element 10 can be connected to the lower layer wiring. Since the distance between the bit line 11 and the word line 12 is reduced by interposing only the diffusion prevention film 32 therebetween and being close to the word line 12, a sufficient synthetic magnetic field can be applied, and the operation of the MRAM Can increase the sex.

  Also in the memory portion A, since the base metal (Ta) of the pinned layer is deposited on the read line 123 and the diffusion prevention film 32 covers the other word lines 12, the read line 123 and Cu in the word line 12 does not diffuse upward. Since the entire width and total length of the lower layer wirings 33 and 34 in the peripheral circuit portion are covered with the pin layer material having a diffusion preventing function, the diffusion of these lower layer wirings above Cu and the upper wirings and contact plugs Can be prevented from spreading downward.

  Here, in the conventional structure shown in FIG. 22, in order to increase the combined magnetic field, the film thickness of the insulating film 35 between the word line 12 and the bit line 11 is reduced, and the bit line 11 and the word line 12 are However, if the insulating film 35 between them is made thin, the following problems (1) and (2) occur.

(1) In order to embed Cu plating as a contact plug 123a in the connection hole, the diameter of the hole is widened during reverse sputtering for improving the adhesion of the surface of the seed metal attached to the inner wall surface of the connection hole. It is difficult to get a reverse sputtering margin to avoid Further, when the reverse sputtering amount is increased, the insulating film 35 is lost.
(2) It is difficult to obtain a polishing margin sufficient to avoid peeling of the interlayer insulating film 35 during surface polishing by CMP or the like performed after Cu plating as a contact plug 123a in the connection hole.

  However, in the present embodiment, as described above, since the TMR element 10 is in contact with the diffusion preventing film 32 on the lower layer wiring, the interlayer insulating film 35 in the conventional structure is omitted. No need for Cu plating embedding or CMP polishing, and the above problems (1) and (2) can be solved at the same time.

  The wiring having such a structure is formed in a matrix as shown in the schematic plan view of FIG. 2 is a plan view of FIG. 1, in which only the wiring is shown by a solid line in order to clearly show the relationship between the wirings. As shown in the figure, the TMR element 10 is formed in an elliptical planar shape.

  An outline of the manufacturing process of the MRAM will be described with reference to FIGS. In the following process, for example, a barrier layer made of Ta or the like is formed when Cu is buried in the connection hole. Further, after the filling, surface polishing by CMP is performed. The resist mask is formed through a process such as a photolithography technique. Etching is performed using a necessary etching gas or the like, but is simply referred to as etching, and description of each process may be omitted on the assumption that these processes are performed.

  First, as shown in FIG. 3A, for example, an insulating layer made of, for example, a silicon oxide film is formed in a memory portion A on a substrate (not shown) on which a Tr and a wiring layer are formed. Cu is embedded in the film 31 to form a word line 12 and a read line 123 having a thickness of 400 nm, and the lower wirings 33 and 34 are similarly formed in the peripheral circuit portion B. The film is deposited to a thickness of 30 nm by the CVD method to form a connection hole 27 with a wiring or the like connected to the TMR element.

Next, as shown in FIG. 3 (b), consists of the free layer 2 made of Ta / PtMn / CoFe / Ru / pinned layer 26 made of CoFe, Al ₂ O ₃ consisting of the tunnel barrier layer 3, CoFe-30B / Ta A magnetic layer 10A to be laminated is laminated.

  Next, as shown in FIG. 3C, a mask layer 46 necessary for processing the magnetic layer 10A is laminated on the magnetic layer 10A. As the mask layer, for example, a silicon nitride film 46a having a thickness of 65 nm / a silicon oxide film 46b having a thickness of 250 nm (hereinafter 46a and 46b are collectively referred to as 46) is deposited by the CVD method, and this is patterned thereon. A resist mask 49 is formed.

  Next, as shown in FIG. 4D, the mask layer 46 is etched by the resist mask 49 by dry etching. Next, as shown in FIG. 4E, the mask layer 46 is used as a mask, and the tunnel barrier layer. 3 is dry-etched on the free layer 2 (CoFe-30B / Ta). By this etching, the mask layer 46 is thinned.

  Next, as shown in FIG. 4F, a mask layer 47 is formed again on the memory part A and the peripheral circuit part B. The mask layer 47 is formed with a structure of, for example, a silicon nitride film 47a having a thickness of 65 nm / a silicon oxide film 47b having a thickness of 250 nm (hereinafter 47a and 47b are collectively referred to as 47).

  Next, as shown in FIG. 5G, the tunnel barrier layer 3 and the pinned layer 26 are etched by dry etching using the mask layer 47 as a mask.

  As a result, in the memory portion A, the TMR element 10 including the pinned layer 26 / tunnel barrier layer 3 / free layer 2 is formed under the thinned mask 46 with the diffusion prevention film 32 sandwiched between the word line 12. A pair of memory cells in which the read line 123 and the TMR element are connected by the wiring 22 made of the pinned layer 26 are formed in a state separated from adjacent memory cells. As a result, the upper surface of the readout line 123 is covered with the base metal layer (Ta) of the pinned layer 26, and Cu is prevented from diffusing upward. Further, since the cap 45 to be described later covering the lower layer wirings 33 and 34 of the peripheral circuit portion B can be formed at the time of separation of the memory cell, the cap 45 can be easily formed without adding a process.

  Next, as shown in FIG. 5H, only the mask layer 47 of the peripheral circuit portion B is removed, and the upper layer metal (CoFe / Ru) of the tunnel barrier layer 3 and the pinned layer 26 on the lower wirings 33 and 34 in this region. / CoFe) is etched by dry etching so that only the base metal layer Ta of the pinned layer 26 and the metal layer (PtMn) thereon remain. This prevents Cu from diffusing upward from the upper surfaces of the lower wirings 33 and 34 and is covered with the conductive cap 45. The mask layer 47 is thinned by this etching.

  Next, as shown in FIG. 5 (i), an interlayer insulating film 35 is formed on the upper surface including the mask layer 47, and then the interlayer insulating film 35 is planarized by CMP. Next, as shown in FIG. 6 (j), By forming a resist mask 48 and etching, a connection hole 28 is formed between the TMR element 10 of the memory part A and the lower layer wirings 33 and 34 of the peripheral circuit part B.

  Next, as shown in FIG. 6 (k), Cu is embedded in the connection hole 28 by plating to form the contact plug 12a of the memory part A, and to connect the lower layer wiring 33 of the peripheral circuit part B and the bid line. After forming the upper wiring 34a on the contact plug 33a and the other lower wiring 34 of the peripheral circuit portion B and polishing the buried Cu by CMP, as shown in FIG. A prevention film 41 is deposited. As a result, the lower layer wirings 33 and 34 of the peripheral circuit part B are also connected to the upper part through the conductive base metal layer (Ta / PtMn), so that the contact resistance can be reduced and taken out to the upper part. The base metal layer prevents Cu from diffusing in the vertical direction.

  Next, as shown in FIG. 7 (m), after the interlayer insulating film 42 and the diffusion prevention film 43 are formed thereon, a resist mask 51 is formed and etched as shown in FIG. 7 (n). A bit hole region 39 is formed and a connection hole 29 is formed with the upper wiring 34 a continuous with the lower wiring 34 in the peripheral circuit portion B. Further, the contact plugs 12a and 33a are opened to connect to the bit lines by a mask (not shown).

  Next, as shown in FIG. 8 (o), the bit line 11 is formed and the connection hole 29 is filled by Cu plating to connect to the contact plug 12a of the memory part A and the lower layer wiring 33 of the peripheral circuit part B. The contact plug 33 a is connected to the bit line 11. Further, an external terminal for connecting the upper wiring 34a continuous with the other lower wiring 34 of the peripheral circuit portion B to an external device or the like is formed, and the same MRAM as in FIG. 1 can be formed.

  By forming the MRAM by the above-described process, the upper surfaces of the lower layer wirings 33 and 34 are covered with the base metal layer (Ta / PtMn) 45 of the pinned layer 26, thereby preventing the lower layer wiring (Cu) from being etched and exposing Cu. In addition, since only the diffusion prevention film 32 exists between the word line 12 and the TMR element 10, the distance between the bit line 11 and the word line 12 is reduced, and a sufficient combined magnetic field is applied. Thus, the lower writing to the TMR element 10 can be performed satisfactorily.

  FIG. 9 shows a modification of the present embodiment. The formation of the cap 45 on the wiring 22 connecting the TMR element 10 of the memory part A and the readout line 123 and the lower layer wirings 33 and 34 of the peripheral circuit part B may be formed by the process of this modification.

  That is, FIG. 9A is the same state as FIG. 5G described above, and the exposed portions of the tunnel barrier layer 3 and the pinned layer 26 exposed between the masks are etched by using the mask layer 47 as a mask. It has been removed.

  Next, as shown in FIG. 9B, after removing the mask 47 including the mask 46 remaining in the previous step, a mask layer 50 made of, for example, SiN / SiO is formed only on the TMR element 10, and this mask is formed. Etching is performed using the layer 50 as a mask.

  As a result, as shown in FIG. 9C, the mask layer 50 is removed, and the upper layer metal (CoFe / P) of the tunnel barrier layer 3 and the pinned layer 26 not only in the peripheral circuit portion B but also in the memory portion A. (Ru / CoFe) 26b is removed, and the lower layer metal layer 26a made of Ta / PtMn of the pinned layer 26 is used to connect the wiring 22 connecting the TMR element 10 and the readout line 123 and the caps of the lower layer wirings 33 and 34 of the peripheral circuit portion B. 45 can be formed.

  Also in this manner, similarly to the above, the diffusion of Cu in the wiring is prevented, the distance between the word line 12 and the bit line 11 is reduced, and a sufficient combined magnetic field acts to write to the TMR element 10. It can be done well.

  FIG. 10 shows another modification. Thus, the cap 45 of the lower layer wirings 33 and 34 of the peripheral circuit portion B may be formed.

  That is, FIG. 10 (a) shows the same state as FIG. 5 (g) as described above. Then, after removing the mask 47 including the mask 46 remaining in the previous step, an interlayer insulating film 35 and a diffusion prevention film 41 are formed thereon, as shown in FIG. 10B, and a resist mask 48 is formed thereon. And is etched into a mask pattern.

  As a result, as shown in FIG. 10B, the interlayer film 35 and the diffusion prevention film 41 are opened in the pattern of the resist mask 48, and the connection holes are formed on the TMR element 10 and the lower layer wirings 33 and 34 of the peripheral circuit portion B. 28 is formed, but the interlayer insulating film 35 under the connection hole 28 is removed by the first etching, the surface of the TMR element 10 is exposed in the memory portion A, and the peripheral circuit portion B is on the lower wirings 33 and 34 The upper part of the tunnel barrier layer 3 is exposed (not shown).

  Next, only the tunnel barrier layer 3 and the upper layer (CoFe / Ru / CoFe) 26b of the pinned layer are etched again using an etching gas that can be etched, thereby connecting the peripheral circuit portion B as shown in FIG. A cap 45 made only of the lower layer metal (Ta / PtMn) 26 a of the pinned layer 26 is formed around the hole 28, and the tunnel barrier layer 3 and the upper layer metal 26 b of the pinned layer 26 remain in the interlayer film 35.

  In this case, either one of the connection holes 28 of the memory part A or the peripheral circuit part B may be covered with a mask or the like and etched separately using a different etching gas from the beginning.

  Next, as shown in FIG. 10C, the contact plug 33a is formed on the contact plug 12a of the memory part A and the lower layer wiring 33 of the peripheral circuit part B by embedding Cu in the connection hole by plating. An upper wiring 34a is formed on the other lower wiring 34 of the circuit.

  In this case as well, since each lower layer wiring is covered with the cap 45, the diffusion of Cu in the wiring can be prevented, and at the same time, the distance between the word line 12 and the bit line 11 is reduced, and a sufficient combined magnetic field is obtained. As a result, the writing to the TMR element 10 can be performed satisfactorily.

  According to the present embodiment, the lower layer wirings 33 and 34 of the peripheral circuit portion B are formed by the cap 45 made of the same material as that of at least one portion of the metal layer 26a made of Ta / PtMn constituting the pinned layer 26 and the underlying metal layer. Since the lower layer wirings 33 and 34 are protected by the cap 45 covering the lower layer wirings during the etching for dividing the memory cells, the lower layer wirings 33 and 34 are prevented from being exposed. it can. Therefore, even if the interlayer insulating film 35 does not exist, the lower layer wirings 33 and 34 are not corroded by chlorine gas or the like, and the contact resistance is small, and the diffusion of Cu upward is prevented to form a favorable wiring. be able to.

  Further, since the distance between the word line 12 and the bit line 11 can be reduced, a magnetic memory device having a layer structure that can increase the combined magnetic field and improve the writing to the TMR element 10 can be obtained. Since the above metal layer material on the lower layer wiring can be formed by etching simultaneously with the division of the memory element, it can be easily formed without adding a process. Further, since the TMR element 10 is formed in contact with the diffusion preventing film 32 on the interlayer insulating film 31, the problem of reverse sputtering margin and polishing margin when the interlayer insulating film is thin can be solved.

Embodiment 2
11 and 12 are schematic cross-sectional views showing the structure of the MRAM according to the present embodiment and a schematic formation process thereof.

  This embodiment is different from the first embodiment described above in that a thin interlayer insulating film 35a is formed between the TMR element 10 and the diffusion preventing film 32 on the lower interlayer insulating film 31 in the configuration as in the conventional example. Thus, the above-described synthetic magnetic field is easy to act, and copper layers 123a, 33a, and 34a are embedded in the interlayer insulating film 35a in the same manner as the damascene structure described above, and the readout line 123 and the lower layer wiring 33, 34 is a part.

  11A shows a state before the upper part of the peripheral circuit portion B is over-etched when the memory cell is divided in the memory portion A (however, in the TMR element 10, the tunnel barrier film 3 is already the same as the free layer). It is processed into a pattern.)

  Next, as shown in FIG. 11B, by etching using the resist mask 51, in the peripheral circuit portion B in the open space, the lower wirings 33 and 34 are covered simultaneously with the memory cell division of the TMR element 10. Although the pin layer material 26 can be easily formed, etching proceeds more than the memory portion A, and the region not covered with the resist mask 51 is etched not only to the diffusion prevention film 32 but also to the upper part of the interlayer insulating film 31. It is easy to be done.

  However, at the time of etching shown in FIG. 11B, the lower layer wirings 33 and 34 (33a, 34a) in the peripheral circuit portion are covered and protected by the mask 51 and the pin layer material 26. Will not be exposed. As a result, as in the first embodiment, it is possible to prevent corrosion of the lower layer wiring and increase in wiring resistance. In addition, as shown in FIG. 11C, after the resist mask is removed, the side surfaces of the lower layer wirings 33 and 34 are located above the lower layer wirings 33 and 34 of the peripheral circuit portion B so that the side surfaces of the lower layer wirings 33 and 34 Since it is covered with the film 35a and the upper part is covered with the mask 45 made of the pin layer material 26, it is possible to prevent Cu from diffusing upward.

  In addition, due to the presence of the interlayer film 35a, the diffusion preventive film 32 in the lower layer is protected and not damaged in the memory portion A during the divided etching between the memory cells, so that the Cu ions are immersed in the word line 12 and the read line 123. In addition to preventing the short circuit between the memory cells, it is possible to reduce the etching amount of the lower interlayer film 31 in the peripheral circuit portion and relatively flatten the surface.

  Thereafter, the same process as in the conventional example shown in FIGS. That is, an interlayer insulating film 40 and a diffusion prevention film 41 are laminated on this, a connection hole (not shown) is formed thereon, and then, as shown in FIG. A contact plug 12a for connecting to a bit line is formed on 10 and a contact plug 33b for connecting to a bit line is formed on one lower layer wiring 33 (33a) of the peripheral circuit portion B, and the other lower layer wiring 34 ( An upper wiring 34b is formed on 34a).

  Next, as shown in FIG. 12E, after the interlayer insulating film 42 and the diffusion preventing film 43 are laminated thereon, a resist mask (not shown) is formed and patterned to form the bit line region. And the connection hole is formed on the upper wiring 34b of the peripheral circuit portion B, and the connection hole on the bit line region and the upper wiring 34b is embedded by Cu plating, thereby forming the bit line 11 and the peripheral circuit portion B. A contact plug 34c is formed on the upper wiring 34b.

  Thereby, the contact plug 33b connected to the contact plug 12a of the memory part A and the lower layer wiring 33 (33a) of the peripheral circuit part B is connected to the bit line 11, and also connected to the upper wiring 34b of the peripheral circuit part B. An MRAM in which the contact plug 34c serves as a connection terminal with an external device or the like can be formed.

  According to the present embodiment, as in the first embodiment, the cap 45 formed of the metal layer 26a made of Ta / PtMn constituting at least a part of the base metal layer of the pinned layer 26 is used for the peripheral circuit portion B. Since 33a and 34a which are a part of the lower layer wiring are covered, even if the interlayer insulating film is over-etched, the lower layer wirings 33a and 34a are protected by the cap 45 (mask) covering the lower layer wiring. Thus, exposure of the lower layer wirings 33a and 34a can be prevented. Further, the metal layer material covering the lower layer wiring of the peripheral circuit portion B can be easily formed without adding a process. Thereby, the lower layer wirings 33a and 34a are not corroded by chlorine gas or the like, the contact resistance is small, and the diffusion of Cu upward can be prevented.

  Moreover, even if the interlayer insulating film 35a is present, it is thin so that the above-described synthetic magnetic field is likely to act.

  Further, since the interlayer film 35a exists under the pinned layer 26, the diffusion preventing film 32 can be protected in the memory portion during the divided etching between the memory cells. Since the entire width and total length of the lower layer wirings 33 (33a) and 34 (34a) in the peripheral circuit portion B are covered with the pin layer material having a diffusion preventing function, the diffusion of the lower layer wirings above Cu is performed. In addition, Cu can be prevented from diffusing downward from the contact plug or the upper wiring.

  Each of the above-described embodiments can be variously modified based on the technical idea of the present invention.

  For example, in the first embodiment described above, the tunnel barrier film 3 exists on the pinned layer 26 in the state of FIG. 5G after element isolation. It may be formed in the same pattern as 2. As a result, the tunnel barrier film does not exist on the lower layer wiring of the peripheral circuit portion, so that the subsequent step of FIG.

  Further, if the pinned layer 26 (and also the PtMn layer) is removed by etching in the step of FIG. 11C and only Ta is left on the lower layer wirings 33a and 34a, the lower layer wiring 33a and the lower layer wiring 33a in the step of FIG. It is possible to reduce the contact resistance between the contact plug 33b and the lower layer wiring 34a connected on this, and the upper wiring 34b connected thereon.

  The constituent materials and film thicknesses of the pinned layer 26, the tunnel barrier layer 3 and the free layer 2 can be appropriately implemented as long as they have functions equivalent to those of the respective embodiments.

  Further, the material and film thickness of each mask layer, the material and film thickness of the diffusion prevention film, and the like may be appropriate, and the formation process of the MRAM is not limited to the embodiment.

Although the present invention is suitable for MRAM, it can also be applied to other magnetic memory devices composed of a memory element having a magnetizable magnetic layer. The MRAM of the present invention is ROM-like with a fixed magnetic direction. It can also be used.

It is a schematic sectional drawing which shows MRAM by Embodiment 1 of this invention. FIG. 2 is a schematic plan view of the MRAM. It is a schematic sectional drawing which shows the manufacturing process of MRAM similarly. It is a schematic sectional drawing which shows the manufacturing process of MRAM similarly. It is a schematic sectional drawing which shows the manufacturing process of MRAM similarly. It is a schematic sectional drawing which shows the manufacturing process of MRAM similarly. It is a schematic sectional drawing which shows the manufacturing process of MRAM similarly. It is a schematic sectional drawing which shows the manufacturing process of MRAM similarly. It is a schematic sectional drawing which shows the manufacturing process of the modification of MRAM similarly. It is a schematic sectional drawing which shows the manufacturing process of the other modification of MRAM similarly. FIG. 10 is a schematic cross-sectional view showing the manufacturing process of the MRAM according to the second embodiment. It is a schematic sectional drawing which shows the manufacturing process of MRAM similarly. It is a schematic perspective view of the TMR element of MRAM. It is a schematic perspective view of a part of the memory cell portion of the MRAM. It is a schematic sectional drawing of the memory cell of MRAM. It is an equivalent circuit diagram of MRAM. It is a magnetic field response characteristic figure at the time of writing of MRAM. It is a read operation principle diagram of MRAM. It is a schematic sectional drawing which shows the manufacturing process of MRAM by a prior art example. It is a schematic sectional drawing which shows the manufacturing process of MRAM similarly. It is a schematic sectional drawing which shows the manufacturing process of MRAM similarly. It is a schematic sectional drawing which shows the manufacturing process of other one form of MRAM same as the above.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Topcoat layer, 2 ... Memory layer (free layer), 3 ... Tunnel barrier layer,
4 ... 1st magnetization fixed layer, 5 ... Antiferromagnetic coupling layer, 6 ... 2nd magnetization fixed layer,
DESCRIPTION OF SYMBOLS 7 ... Antiferromagnetic material layer, 8 ... Underlayer, 9 ... Support substrate, 10 ... TMR element, 10A ... Magnetic material layer, 11 ... Bit line, 12 ... Word line for writing, 12a ... Contact line,
13 ... Silicon substrate, 14 ... Well region, 15 ... Gate insulating film, 16 ... Gate electrode,
17 ... Source region, 18 ... Drain region,
19: Read-out field effect transistor (selection transistor), 20: Source electrode,
21 ... sense line, 22 ... wiring, 24 ... word line current drive circuit,
25: bit line current drive circuit, 26: magnetization fixed layer (pinned layer),
27, 28, 29 ... connection hole, 30 ... barrier film, 31, 35, 40, 42 ... interlayer insulating film,
32, 41, 43 ... Diffusion prevention film, 33, 34 ... Lower layer wiring,
36, 48, 51 ... resist mask, 37 ... separation groove, 39 ... bit line formation region,
45 ... Cap, 46, 47, 49, 50 ... Mask layer, 123 ... Read-out line,
A ... Memory part, B ... Peripheral circuit part, T ... Thickness, L ... Spacing, W ... Width

Claims (10)

A magnetic memory element is constituted by a tunnel magnetoresistive effect element formed by laminating a magnetization fixed layer with a fixed magnetization direction, a tunnel barrier layer, and a magnetic layer capable of changing the magnetization direction. In a magnetic memory device having a memory unit and a peripheral circuit unit of the memory unit,
A magnetic memory device, wherein a lower layer wiring of the peripheral circuit portion is covered with the same constituent material as at least a part of a metal layer constituting the magnetization fixed layer and the underlying conductive layer.   The magnetic memory device according to claim 1, wherein an upper layer wiring connected to the lower layer wiring of the peripheral circuit unit is connected to a bit line of the magnetic memory element.   In the magnetic memory element, only an insulating diffusion prevention film for preventing diffusion of constituent metal elements of the word line is provided between the word line disposed on the side opposite to the bit line and the underlying conductive layer. The magnetic memory device according to claim 2, wherein the magnetic memory device is present.   The magnetic memory device according to claim 3, wherein a read line connected to the base conductive layer is embedded in an insulating layer in which the word line is embedded.   The magnetic memory device according to claim 4, wherein the lower layer wiring is embedded in the insulating layer.   3. The magnetic memory device according to claim 2, wherein the connection of the bit line to the magnetic memory element and the formation of the upper layer wiring are performed via an insulating layer.   The magnetic memory device according to claim 4, wherein the lower layer wiring, the word line, and the read line are made of copper or a copper alloy.   An insulator layer or a conductor layer is sandwiched between the magnetization pinned layer and the magnetic layer, and is induced by flowing current to the bit line and the word line provided on the upper surface and the lower surface of the memory element, respectively. The magnetic memory device according to claim 1, wherein information is written by magnetizing the magnetic layer in a predetermined direction with a magnetic field, and the write information is read by a tunnel magnetoresistive effect through the tunnel barrier layer. . A magnetic memory element is constituted by a tunnel magnetoresistive effect element formed by laminating a magnetization fixed layer with a fixed magnetization direction, a tunnel barrier layer, and a magnetic layer capable of changing the magnetization direction. In a method of manufacturing a magnetic memory device having a memory unit and a peripheral circuit unit of the memory unit,
Forming the lower layer wiring in the peripheral circuit portion;
Laminating each constituent material of the underlying conductive layer of the magnetization fixed layer, the magnetization fixed layer, the tunnel barrier layer, and the magnetic layer in this order on the memory unit including the lower layer wiring;
And a step of patterning at least a part of the metal layer constituting the magnetization fixed layer and the base conductive layer so as to cover the lower layer wiring, and forming the magnetic memory element. Device manufacturing method.   The method for manufacturing a magnetic memory device according to claim 9, wherein the magnetic memory device according to claim 2 is manufactured.

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