JP2005303231A - Magnetic memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a magnetic memory device, having a structure in which low power consumption and high integration of the memory device and high-speed operation of the memory device can be achieved at the same time. <P>SOLUTION: The magnetic memory device has a memory cell comprising a TMR element 10, in which magnetization fixed layers 4 to 7, a tunnel barrier layer 3, and a magnetization free layer 2 are laminated, and to which the write operation is conducted using a bit line 11 and a write word line 12. The bit line 11 (a first wiring line) is formed via an interlayer insulating film 54 (a first insulating layer), in which the TMR element 10 is embedded, while the write word line 12 (a second wiring line) is arranged opposite via an interlayer insulating film 50 (a second insulating layer). In the peripheral circuit section, the bit line 11 is connected to a connection wiring line 65 (a third wiring line) formed in an upper part which is separated from the interlayer insulating film 54, in order to avoid increase of the parasitic capacitance associated with the connecting wiring line 65, by the shortening of the distance between the bit line 11 and the write word line 12. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  In the present invention, a magnetic memory element is configured by a tunnel magnetoresistive effect element in which a magnetization fixed layer with a fixed magnetization direction, a tunnel barrier layer, and a magnetization free layer capable of changing the magnetization direction are stacked. The present invention relates to a magnetic memory device having a memory unit composed of a magnetic memory element, and more particularly to a magnetic random access memory, that is, a magnetic memory device configured as an MRAM (Magnetic Random Access Memory) which is a so-called nonvolatile memory.

  With the rapid spread of information communication equipment, especially small personal devices such as portable terminals, the elements such as memory and logic that make it up are becoming more highly integrated, faster, and consume less power. Performance improvement is required.

  In particular, nonvolatile memories are considered essential in the ubiquitous era. The nonvolatile memory can protect important information including personal information even when power is consumed or trouble occurs or the server and the network are disconnected due to some trouble. In addition, recent portable devices are designed to reduce power consumption as much as possible by setting unnecessary circuit blocks to the standby state. However, if a non-volatile memory that can serve both as a high-speed work memory and a large-capacity storage memory can be realized. , Power consumption and memory waste can be eliminated. In addition, if a high-speed, large-capacity nonvolatile memory can be realized, an “instant-on” function that can be instantly started when the power is turned on becomes possible.

  Examples of the non-volatile memory include a flash memory using a semiconductor and an FRAM (Ferroelectric Random Access Memory) using a ferroelectric.

However, the flash memory has a drawback that the access time is as slow as about 100 ns. On the other hand, in FRAM, the number of rewritable times is 10 ¹² to 10 ¹⁴ , and the endurance is small to replace completely with SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory), and ferroelectricity It has been pointed out that microfabrication of body capacitors is difficult.

  MRAM does not have these drawbacks, and has attracted attention as a non-volatile memory having excellent characteristics such as high speed, large capacity (high integration), and infinite rewrite resistance (for example, Wang et al., IEEE Trans. Magn., 33, 4498 (1997)). The MRAM is a semiconductor magnetic memory that performs reading using a magnetoresistive effect based on a spin-dependent conduction phenomenon peculiar to nanomagnets, and is a non-volatile memory that can hold a memory without supplying power from the outside. The MRAM has a simple structure and can be easily integrated. In addition, since the recording can be performed by reversing the magnetic moment, the number of rewritable times is large, and the access time is expected to be very high. Have already been reported to be operable at 100 MHz (R. Scheuerlein et al., ISSCC Digest of Technical Papers, p. 128-129, Feb. 2000).

  A TMR (Tunnel Magnetoresistance) element used for MRAM has a structure in which a tunnel barrier layer is sandwiched between two magnetic layers of a magnetization free layer (storage layer) and a magnetization fixed layer, and the magnetization directions of the two magnetic layers. Is read as information by using the fact that the intensity of the current flowing through the tunnel barrier layer changes due to the difference in the relative magnetization direction. It is a memory element which performs. MRAM has been vigorously developed, for example, attracting attention due to recent improvements in the properties of TMR materials.

  Hereinafter, the TMR type MRAM will be described in more detail.

  FIG. 20 is a perspective view of the TMR element 10 serving as a memory element of an MRAM memory cell. The TMR element 10 is provided on the support substrate 9, and includes a magnetization free layer (storage layer) 2 in which the magnetization direction is relatively easily reversed, and a first magnetization fixed layer 4 in which the magnetization direction is fixed. And a second magnetization fixed layer 6. For the magnetization free layer (memory layer) 2 and the first and second magnetization fixed layers 4 and 6, for example, a ferromagnetic material mainly composed of nickel, iron, cobalt, or an alloy thereof is used.

  Between the first magnetization fixed layer 4 and the second magnetization fixed layer 6, a conductor layer 5 is disposed so that these magnetic layers are antiferromagnetically coupled. As the material of the conductor layer 5, ruthenium, copper, chromium, gold, silver, or the like can be used. The second magnetization fixed layer 6 is in contact with the antiferromagnetic material layer 7, and the second magnetization fixed layer 6 has a strong unidirectional magnetic anisotropy due to the exchange interaction acting between these layers. . As a material of the antiferromagnetic material layer 7, for example, a manganese alloy such as iron, nickel, platinum, iridium, and rhodium, cobalt, nickel oxide, or the like can be used.

  The magnetization free layer (memory layer) 2 has a magnetization easy axis (direction axis in which the ferromagnetic material is easily magnetized) parallel to the magnetization direction of the magnetization fixed layer 4, and is parallel to the magnetization direction of the magnetization fixed layer 4. Alternatively, it is easy to be magnetized in either antiparallel direction, and the magnetization direction can be reversed relatively easily between these two states. Therefore, when the magnetization free layer (storage layer) 2 is used as an information storage medium, 2 of the magnetization free layer (storage layer) 2 magnetized “parallel” and “antiparallel” with respect to the magnetization direction of the magnetization fixed layer 4. The two states are associated with information “0” and “1”.

  In addition, a tunnel barrier layer 3 made of an insulator made of an oxide or nitride such as aluminum, magnesium, or silicon is sandwiched between the magnetization free layer (memory layer) 2 and the first magnetization fixed layer 4. The magnetic free layer (memory layer) 2 and the first magnetization fixed layer 4 are disconnected from each other, and the tunnel current corresponding to the magnetization direction of the magnetization free layer (memory layer) 2 flows. . The magnetic layer and the conductor layer constituting the TMR element 10 are mainly formed by sputtering, but the tunnel barrier layer 3 can be obtained by oxidizing or nitriding a metal film formed by sputtering.

  The top coat layer 1 has a role of preventing mutual diffusion between the TMR element 10 and wiring connected to the TMR element 10, reducing contact resistance, and preventing oxidation of the magnetization free layer (memory layer) 2, and is usually made of copper. Materials such as tantalum, titanium nitride and titanium can be used. The base electrode layer 8 is used for connection with a readout switching element connected in series with the TMR element 10. The base electrode layer 8 may also serve as the antiferromagnetic material layer 7.

  FIG. 21 is an enlarged perspective view showing a part of a general MRAM in a simplified manner. Here, for the sake of simplicity, the read circuit portion is omitted, and nine memory cells are shown as an example. The MRAM has a bit line 11 and a writing word line 12 that intersect each other, and TMR elements 10 are arranged in a matrix between the layers where the wirings 11 and 12 intersect.

  22 and 16 show equivalent circuit diagrams of the MRAM. FIG. 22 shows the overall configuration, and FIG. 23 is a partially enlarged view thereof. In FIG. 23, six memory cells are shown as an example. At the intersection of the bit line 11 and the write word line 12, the TMR element 10 and the TMR element 10 are connected to each other. A field effect transistor 15 for selecting an element is provided. Further, a read word line 13 for controlling ON / OFF of the field effect transistor 15 and a sense line 14 for outputting the read information are provided. In the peripheral circuit portion, a bit line current drive circuit 16 is connected to the bit line 11, a bidirectional write word line current drive circuit 17 is connected to the write word line 12, and a read line is connected to the sense line 14. A sense amplifier 18 for detecting the output information is connected.

  Information is written to the TMR element 10 by passing a current through the bit line 11 and the write word line 12, and the magnetization direction of the magnetization free layer (storage layer) 2 is changed to a magnetization fixed layer by a combined magnetic field generated from these. This is performed by setting it to “parallel” or “anti-parallel” to the magnetization direction of 4.

A magnetic field in the magnetization free layer (storage layer) 2 of the TMR element 10 is normally applied by a write current flowing in the easy axis direction of the magnetic field H _EA through the bit line 11, and a magnetic field H _{HA in the} hard axis direction of magnetization is applied to the write word. Applied by a write current flowing through the line 12, a combined magnetic field is generated by vector synthesis of these magnetic fields _HEA and _HHA .

In the MRAM, a magnetic field H _EA (<H _s ) and H _HA (<H _s ) having a strength that does not cause magnetization reversal by only one of them is applied, and current is passed using the asteroid magnetization reversal characteristics. There at the intersection of the word line 12 the write bit line 11 causes only cause of the magnetic spin inversion in the memory cell in which both the magnetic field H _EA and H _HA acts together, it is common to perform writing. Hereinafter, this principle will be described in detail (see US Pat. No. 6,081,445).

FIG. 24 is an asteroid curve graph showing the magnetic field response characteristics of the magnetization free layer (memory layer) 2 of the TMR element during the information write operation. As shown in FIG. 24, when the magnetic field H _EA applied in the easy axis direction is H _x (<H _s ) and the magnetic field H _HA applied in the hard axis direction is H _y (<H _s ), H _x and H _y and a vector sum combined magnetic field H the magnetization free layer (storing layer) applied to the 2, greater than the threshold value H _c of the combined magnetic field H corresponding to the point C on the asteroid curve, When the size reaches the area A outside the asteroid curve, the magnetization direction of the magnetization free layer (memory layer) 2 can be reversed. On the other hand, the synthetic magnetic field H in which the vector sum remains inside the asteroid curve cannot reverse the magnetization direction of the magnetization free layer (memory layer) 2.

In the magnetization direction reversal characteristics described above, when both the easy magnetization axial magnetic field _HEA and the difficult magnetization axial magnetic field _HHA are present, the magnitude of the magnetic field required to reverse the magnetization direction is independent. And using two write lines of the bit line 11 and the write word line 12, information is selectively transmitted only to the TMR element 10 of the memory cell at the intersection of the two. It shows the principle that enables writing.

That is, when a single magnetic field acts in the direction of the easy axis or the hard axis, the threshold value of the magnetic field required for the magnetization reversal is the easy axis (x axis) or the hard axis of the asteroid curve. The value H _s on the (y-axis). Therefore, even if H _x or H _y smaller than H _s is applied, the magnetization direction of the magnetization free layer (storage layer) 2 cannot be reversed alone. However, if both acting together, the combined magnetic field H reaches the outside of the area A of the asteroid curve beyond the threshold H _c on asteroid curve, the magnetization free layer (storing layer) 2 of the magnetization It is possible to reverse the direction.

At this time, by a write current flowing through the bit line 11, to all the TMR elements 10 disposed below the bit line 11, a magnetization easy axis direction magnetic field H _EA H _x is applied, also, the word line for writing by the write current flowing through the 12, all of the TMR elements 10 arranged above the write word line 12, although H _y is applied a hard-axis direction magnetic field H _HA, the bit line 11 and word line 12 the memory cells other than the memory cell at the intersection, so H _x or H _y is only acting alone, write of information does not occur. Both can work together to write information only to the memory cell at the intersection of the bit line 11 and the word line 12. In this manner, by using the bit line 11 and the write word line 12, it becomes possible to selectively write information only to the memory cells at the intersection of the two.

Note that if H _x or H _y is larger than the unidirectional reversal magnetic field H _s , information is written to all the memory cells to which it is applied. Therefore, H _x and H _y are less than H _s . There must be. Therefore, an appropriate region of the combined magnetic field applied to the magnetization free layer (storage layer) 2 for writing information is a region A shown in gray in FIG. For this reason, the magnitude of the current passed through the bit line 11 and the write word line 12 is adjusted so that the combined magnetic field falls within the gray region A in the figure.

  FIG. 25 is a schematic cross-sectional view for explaining the information reading operation in the TMR element 10 of the MRAM. Here, the layer configuration of the TMR element 10 is schematically shown, and the above-described 4 to 6 magnetization fixed layers are shown together, and the topcoat layer 1, the antiferromagnetic material layer 7, and the base electrode layer 8 are The illustration is omitted.

  Reading of information recorded in the TMR element 10 is performed using the TMR effect which is one type of magnetoresistive effect. The TMR effect means that the resistance to the tunnel current flowing between two magnetic layers facing each other across the tunnel barrier layer is reduced if the magnetic spin directions of the two magnetic layers are “parallel”, and “anti-parallel”. If so, it is a phenomenon that grows.

  Specifically, as shown in FIG. 25, a tunnel current flowing from the bit line 11 through the magnetization free layer (memory layer) 2, the tunnel barrier layer 3 and the magnetization fixed layers 4 to 6 is supplied, and the magnitude of the above resistance is increased. Is read from the base electrode layer 8, and the directions of the magnetic spins of the two magnetic layers are detected based on the magnitude of the read current.

  That is, as shown in the left diagram of FIG. 25, when the magnetization directions of the magnetization free layer (storage layer) 2 and the magnetization fixed layer 4 are “parallel” and the magnetic spins are aligned, these two layers The resistance between them is small, and a large read current flows through the tunnel barrier layer 3. On the other hand, when the magnetization direction of the magnetization free layer (storage layer) 2 and the magnetization fixed layer 4 is “antiparallel” and the magnetic spins are opposite as shown in the right diagram of FIG. The resistance between the layers is large and the read current flowing through the tunnel barrier layer 3 is small.

  As will be described later with reference to FIG. 26, the base electrode layer 8 of the TMR element 10 is connected to the drain electrode 23 of the read transistor 15 by the read wiring 19, and the source electrode 27 of the read transistor 15 is connected to the sense line 14. It is connected. Therefore, during the read operation of the MRAM, the TMR element 10 selected by applying the control signal to the gate electrode (read word line) 13 among the TMR elements 10 connected to the bit line 11 to which the drive current is applied. Is read out to the sense line 14 via the read field effect transistor 15. Thus, the field effect transistor 15 functions as a switching element for selectively reading information stored in the TMR element 10.

  FIG. 26A is a cross-sectional view of an essential part of a boundary region between a memory portion and a peripheral circuit portion, schematically showing a typical architecture of a conventional MRAM.

  The left portion of FIG. 26A shows one of a large number of memory cells arranged in the memory portion. Under each memory cell, for example, a p-type well region 28 formed in a p-type silicon semiconductor substrate 27, a drain electrode 22, a drain region 23, a gate electrode 13, a gate insulating film 24, a source region 25, and a source An n-type read field effect transistor 15 formed of an electrode 26 is provided, and a sense line 14, a write word line 12, a TMR element 10, and a bit line 11 are disposed thereon.

  The TMR element 10 is formed on the interlayer insulating film 50 by sputtering or the like, for example, a tantalum layer as the base electrode layer 8, a manganese alloy layer of platinum as the antiferromagnetic layer 7, and iron as the second magnetization fixed layer 6. And a cobalt alloy layer, a ruthenium layer as the conductor layer 5 that antiferromagnetically couples the magnetic layer, an iron-cobalt alloy layer as the first magnetization fixed layer 4, an aluminum oxide layer as the tunnel barrier layer 3, and a magnetization free layer 2 is formed by laminating an alloy layer CoFe-30B of iron, cobalt, and boron, and a thallium layer as the topcoat layer 1.

  A part of the layers 4 to 8 forming the TMR element 10 is patterned into the shape of the readout wiring 19 and also serves as the wiring. The readout wiring 19 uses the readout current of the TMR element 10 for the readout. It functions to transmit to the drain electrode 22 of the read transistor 15 through the connection hole 20 and the read land 21.

  The gate electrode 13 of the read transistor 15 is formed by connecting the gate electrode 13 of each cell in a band shape, and also serves as the read word line 13. The source electrode 26 is connected to the sense line 14. As described above, the field effect transistor 15 functions as a switching element that sends a read current of the TMR element 10 of the cell to the sense line 14 when a predetermined control signal is applied to the gate electrode (read word line) 13. . The transistor 15 may be an n-type or p-type field effect transistor, but various switching elements such as a diode, a bipolar transistor, and a MESFET (Metal Semiconductor Field Effect Transistor) can be used.

  On the other hand, the right part of FIG. 26A shows an example of the peripheral circuit transistor 30 formed in the peripheral circuit portion. Specifically, the peripheral circuit transistor 30 constitutes the bit line current drive circuit 16, the write word line current drive circuit 17, the sense amplifier 18 and the like shown in FIG. For example, the peripheral circuit transistor 30 shown in FIG. 26A constitutes the bit line current drive circuit 16.

  FIGS. 26B and 26C show another method of forming an electrical connection to the TMR element 10. FIG. 26B shows an example in which the bit line 11 is connected via a connection plug instead of being directly connected to the topcoat layer 1. FIG. 26 (c) shows another form of the readout wiring 19, and instead of providing the readout plug 20, the constituent layer of the readout wiring 19 is formed in the opening formed above the readout land 21. Is directly embedded and a connection with the read land 21 is formed.

  The memory device of FIG. 26 is fabricated by standard materials and methods of integrated circuit technology. For example, a wiring metal material used in a general semiconductor process, such as copper or aluminum, is used for forming the wiring such as the bit line 11 and the writing word line 12. Thus, an aluminum wiring is formed by film formation by sputtering, patterning by lithography and dry etching. Moreover, plugs such as electrodes and connection holes are formed by filling tungsten or the like.

  As shown in the enlarged view of the write word line 12, in the copper wiring, a tantalum layer or a tantalum nitride layer is used as a barrier layer (diffusion prevention film) for preventing the diffusion of copper ions. In the drawings of this specification, the illustration of the barrier layer is omitted. Similarly, illustration of a titanium nitride layer used as a barrier layer for a tungsten electrode or a tungsten plug is omitted.

  In general, a silicon oxide film is formed by a CVD (Chemical Vapor Deposition) method as an interlayer insulating film, and a silicon nitride film is formed by a CVD method as a diffusion prevention film.

  As described above, in the MRAM, the bit line 11 and the writing line are arranged so as to intersect the TMR element in which the tunnel barrier layer 3 is sandwiched between two ferromagnetic layers, the magnetization free layer 2 and the magnetization fixed layers 4 to 6. Each memory cell has a basic structure in which the word lines 12 are arranged in a matrix at the intersection region of the word lines 12 and a read cell selection switch (such as a MOS (Metal Oxide Semiconductor) transistor 15). The structure of this structure has been widely reported by IBM and Motorola (see Patent Documents 1 to 3 described later).

  This MRAM writing is characterized by current magnetic field writing in which data is selectively written into the TMR element 10 at the intersection by a magnetic field generated by a current flowing through the bit line 11 and the writing word line 12.

Japanese Patent Laid-Open No. 11-317071 (page 7-9, FIG. 11-16) JP-A-10-116490 (pages 3 and 4, FIGS. 1 and 2) US Pat. No. 6,174,737 (page 2-6, FIG. 1-13)

  As a problem for increasing the degree of integration of a memory device using a TMR element, for example, an MRAM and putting the memory device into practical use, it is required to reduce the write current of the TMR element. In order to enable writing with the smallest possible write current of 10 mA or less, more preferably 1 mA or less, the current flowing through the bit line 11 and the write word line 12 can increase the efficiency with which the magnetic free layer 2 generates a magnetic field. is necessary. For example, in the magnetic memory device shown in FIG. 26, the distances between the bit line 11 (first wiring described later) and the writing word line 12 (second wiring described later) and the magnetization free layer 2 of the TMR element 10 (FIG. 26). X and y) are made as small as possible, more specifically, the thickness of the interlayer insulating film 50 (including the diffusion preventing film 49) (second insulating film described later) and the interlayer insulating film 54 (described later) The first insulating film) is required to be as thin as possible, and various measures for this purpose have been devised.

  On the other hand, in the peripheral circuit portion of the MRAM, an existing technique has already been established that enables high-speed operation of the TMR element 10 by operating the current flowing through the bit line 11 and the write word line 12 at high speed.

However, in the conventional magnetic memory device shown in FIG. 26, the bit line 11 and the write word line 12 of the memory unit, the upper connection wiring 103 (third wiring described later) of the peripheral circuit unit that drives the bit line 11, and Since the lower connection wiring 38 (fourth wiring described later) is formed in the same insulating layer, that is, the interlayer insulating films 202 and 46, the distance L between the upper connection wiring 103 and the lower connection wiring 38 in the peripheral circuit portion. And between x and y above
L = x + y
If the thickness of the interlayer insulating film 50 and / or the interlayer insulating film 54 is reduced and x and / or y is reduced with the aim of reducing power consumption and high integration of the TMR element 10, The distance L between the connection wirings of the circuit is also inevitably reduced, causing problems such as an increase in circuit delay due to an increase in parasitic capacitance between the connection wirings, and reducing the power consumption and high integration of the memory device. There arises a problem that high-speed operation cannot be achieved.

  The present invention has been made in view of the circumstances as described above, and an object of the present invention is to provide a magnetic device having a structure in which low power consumption and high integration of a memory device and high-speed operation of the memory device can be compatible. It is to provide a memory device.

That is, according to the present invention, a magnetic memory element is configured by a tunnel magnetoresistive effect element in which a magnetization fixed layer with a fixed magnetization direction, a tunnel barrier layer, and a magnetization free layer capable of changing the magnetization direction are stacked. A first wiring (for example, a bit line 11 to be described later) connected to the tunnel magnetoresistive effect element is provided in addition to the connection portion with the tunnel magnetoresistive effect element. The first insulating layer (for example, an interlayer insulating film 54 to be described later) is formed, and the second insulating layer (for example, an interlayer insulating film 50 to be described later) is disposed on the opposite side to the first wiring. A second wiring (for example, a write word line 12 to be described later) is disposed opposite to the tunnel magnetoresistive effect element, and writing to the tunnel magnetoresistive effect element is performed using the first wiring and the second wiring. In the magnetic memory device configured Migihitsuji,
The first wiring is connected to a third wiring (for example, an upper connection wiring 65 described later) formed in a state of being separated from the first insulating layer and led to the peripheral circuit portion;
The second wiring is connected to a fourth wiring (for example, a lower connection wiring 38 or 92 described later) formed in a state of being separated from the second insulating layer and led to the peripheral circuit portion. The present invention relates to a magnetic memory device characterized by comprising at least one of them.

  According to the present invention, the first wiring connected to the tunnel magnetoresistive effect element is formed via the first insulating layer provided in a portion other than the connection part with the tunnel magnetoresistive effect element, and the first Since the second wiring is disposed opposite to the tunnel magnetoresistive element through the insulating layer on the side opposite to the first wiring, the thickness of the first insulating layer and the second insulating layer can be reduced by reducing the thickness of the first insulating layer and the second insulating layer. Reducing the distance between the one wiring and the second wiring and the magnetization free layer of the tunnel magnetoresistive element, and increasing the efficiency with which the current flowing through the first wiring and the second wiring generates a magnetic field in the magnetization free layer; Low power consumption and high integration of the memory device can be realized.

  On the other hand, the first wiring is connected to a third wiring formed in a state of being separated from the first insulating layer and led to a peripheral circuit portion, and the second wiring is connected to the second insulation. The third wiring and the fourth wiring are defined as at least one of the requirements for being connected to the fourth wiring formed in a state of being separated from the layer and being led to the peripheral circuit portion. A sufficient distance can be provided between the wiring lines and the parasitic capacitance between both wirings can be reduced, the circuit delay can be suppressed, and the memory device can be operated at high speed.

  As described above, according to the magnetic memory device of the present invention, both low power consumption and high integration of the memory device and high-speed operation of the memory device can be achieved.

  In the present invention, the first wiring and / or the second wiring is formed through the insulating layer (for example, an interlayer insulating film 56 or 46 described later) in which the first wiring and / or the second wiring are embedded. It is good to be connected with 4 wirings. When the third wiring or / and the fourth wiring are formed through the insulating layer in which the first wiring and the second wiring are embedded, the third wiring and the fourth wiring are interposed between the third wiring and the fourth wiring. A distance larger than the distance between the first wiring and the second wiring is secured.

  At this time, it is preferable that the insulating layer and the first wiring or / and the second wiring exist at the same level. In this case, the first wiring and the third wiring, or the second wiring and the fourth wiring are directly overlapped with each other without providing an interlayer insulating film or a connection hole therebetween. There is an advantage that it can be connected and the number of manufacturing steps is reduced.

  Alternatively, a connection hole is provided in another insulating layer (for example, an interlayer insulating film 72 described later) formed on or below the insulating layer, and the first wiring and the third wiring, or / In addition, the second wiring and the fourth wiring may be connected. With this configuration, there is an advantage that the distance and the parasitic capacitance between the third wiring and the fourth wiring can be adjusted by appropriately selecting the thickness and material of the other insulating layer.

  In addition, at least the first wiring and / or the second wiring may be covered with a magnetic layer on at least a part of the surface other than the surface facing the tunnel magnetoresistive element. As a result, the magnetic flux generated by the current flowing through the first wiring and / or the second wiring is collected in the tunnel magnetoresistive effect element, and a magnetic field having a required strength is formed with a smaller current. The magnetic layer may be formed on the first wiring and / or the second wiring, and is not necessary for the third wiring or / and the fourth wiring. By limiting the formation of the magnetic layer to the memory unit in a separate process, it is possible to prevent the already formed wiring formation in the peripheral circuit unit from being affected. For example, cutting of a part including the wiring Etc. becomes easy.

  Further, it is preferable that the first wiring and the second wiring are arranged so as to intersect with each other, and the tunnel magnetoresistive effect element is disposed in the intersecting region. The tunnel barrier layer is sandwiched between the magnetization fixed layer and the magnetization free layer, and a magnetic field is induced by flowing a current through the bit line as the first wiring and the word line as the second wiring. Then, the magnetization free layer may be magnetized in a predetermined direction to write information, and the written information may be read by a tunnel magnetoresistance effect through the tunnel barrier layer. These are standard configurations of MRAM.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1
FIG. 1 is a schematic cross-sectional view showing the structure of the magnetic memory device according to the first embodiment. This magnetic memory device should be compared with the conventional magnetic memory device shown in FIG.

  As in FIG. 26, FIG. 1 is a cross-sectional view of the main part of the boundary region between the memory unit and the peripheral circuit unit, showing the structure of the memory unit on the left side and the structure of the peripheral circuit unit on the right side. . The structure of the memory portion is the same as that in FIG. 26, and only the structure of the peripheral circuit portion is different.

  As described above, in the magnetic memory device shown in FIG. 26, in the memory portion, the bit line 11 (the first wiring) is formed via the interlayer insulating film 54 (the first insulating layer) in which the TMR element 10 is embedded. In addition, on the opposite side of the bit line 11, the write word line 12 (second wiring) is disposed oppositely via the interlayer insulating film 50 (second insulating layer). The bit line 11 is extended as it is, and the upper connection wiring 103 (the third wiring) of the peripheral circuit portion connected to the bit line 11 is formed.

As a result, as described above, the bit line 11 (the first wiring) and the write word line 12 (the second wiring), the upper connection wiring 103 (the third wiring) and the lower connection wiring in the peripheral circuit portion. 38 (the fourth wiring) are respectively provided in the same insulating layer, that is, the interlayer insulating films 202 and 46, and therefore the distance between the bit line 11 and the write word line 12 and the magnetization free layer 2 of the TMR element 10 Are x and y, respectively, and the distance L between the upper connection wiring 103 and the lower connection wiring 38 in the peripheral circuit portion is
L = x + y
Therefore, there has been a problem that the low power consumption and high integration of the memory device cannot be compatible with the high speed operation of the memory device.

On the other hand, in the magnetic memory device according to the present embodiment, in the peripheral circuit portion, the upper connection wiring 65 (third wiring) sandwiches the diffusion prevention film 55, the interlayer insulating film 56, and the diffusion prevention film 59. Since the bit line 11 is connected to the interlayer insulating film 54 (the first insulating layer) and spaced apart from the interlayer insulating film 54 (the first insulating layer), the upper connection wiring 65 (the third wiring) in the peripheral circuit portion and The distance L from the lower connection wiring 38 (the fourth wiring) is
L = x + y + l
It becomes. However, l is the total thickness of the diffusion prevention film 55, the interlayer insulating film 56, and the diffusion prevention film 59.

  Therefore, by reducing the distance (x and y) between the bit line 11 and the write word line 12 and the magnetization free layer 2 of the TMR element 10 as much as possible, the current flowing through the bit line 11 and the write word line 12 is changed to the magnetization free layer. Even if the efficiency of generating a magnetic field in 2 is improved and the power consumption and the high integration of the memory device are reduced, if the interlayer insulating film 56 having an appropriate thickness is provided, the upper connection wiring 65 in the peripheral circuit portion is provided. Since a sufficient distance L can be secured between the (third wiring) and the lower connection wiring 38 (fourth wiring), there is no problem of circuit delay due to an increase in parasitic capacitance, and compatibility with high-speed operation of the memory device. Can be made.

  Hereinafter, other parts of the magnetic memory device according to the present embodiment will be described and the manufacturing method thereof will be described.

  The left part of FIG. 1 shows one of a number of memory cells arranged in the memory unit. Each memory cell includes a drain electrode 22, a drain region 23, a gate electrode in a p-type well region 28 formed in, for example, a p-type silicon semiconductor substrate 27 as in the conventional magnetic memory device shown in FIG. 13, an n-type read field effect transistor 15 including a gate insulating film 24, a source region 25, and a source electrode 26 is provided, and a sense line 14, a write word line 12, a TMR element 10, and a bit line are provided thereon. 11 is arranged.

  The TMR element 10 has a structure in which a tunnel barrier layer 3 is sandwiched between two magnetic layers of a magnetization free layer (storage layer) 2 and a magnetization fixed layer whose magnetization is relatively easily reversed. This is a storage element that performs reading using the relative magnetization direction of the magnetic layer and performs reading using the change in the intensity of the current flowing through the tunnel barrier layer due to the difference in the relative magnetization direction.

  The TMR element 10 is not shown in detail here, but as already described with reference to FIG. 13, the base electrode layer 8 made of thallium, etc./manganese alloy such as iron, nickel, platinum, iridium, rhodium, cobalt Or antiferromagnetic layer 7 made of nickel oxide, etc./second magnetization fixed layer 6 made of a ferromagnetic made of nickel, iron or cobalt, or an alloy thereof / conductor layer made of ruthenium, copper, chromium, gold, silver or the like 5 / first magnetization fixed layer 4 made of a ferromagnetic material made of nickel, iron or cobalt, or an alloy thereof / tunnel barrier layer 3 made of an oxide or nitride such as aluminum, magnesium or silicon 3 / nickel Magnetized free layer 2 made of ferromagnet made of iron, cobalt, or an alloy thereof / Topcoating made of copper, tantalum, titanium nitride, etc. Coat layer 1 are laminated on a substrate.

  The magnetization fixed layer has two magnetization fixed layers of a first magnetization fixed layer 4 and a second magnetization fixed layer 6, and a conductor layer in which these magnetic layers are antiferromagnetically coupled between them. 5, the second magnetization fixed layer 6 is in contact with the antiferromagnetic layer 7, and the second magnetization fixed layer 6 has a strong unidirectional magnetic anisotropy by the exchange interaction acting between these layers. The magnetization directions of the first magnetization fixed layer 4 and the second magnetization fixed layer 6 are fixed.

  Further, between the magnetization free layer 2 and the first magnetization fixed layer 4, a tunnel barrier layer 3 made of an insulator made of oxide, nitride, or the like of aluminum, magnesium, silicon, etc. is sandwiched, so that the magnetization free It plays the role of breaking the magnetic coupling between the layer 2 and the magnetization fixed layer 4 and flowing a tunnel current. These magnetic layers and conductor layers are mainly formed by sputtering, but the tunnel barrier layer 3 can be obtained by oxidizing or nitriding a metal film formed by sputtering.

  The topcoat layer 1 has a role of preventing mutual diffusion between the TMR element 10 and the wiring connected to the TMR element, reducing contact resistance, and preventing the magnetization free layer 2 from being oxidized.

  The TMR element 10 shown in FIG. 1 is formed using the interlayer insulating film 50 as a substrate, and a part of the layers 4 to 8 is patterned into the shape of the readout wiring 19 and also serves as a wiring. The read wiring 19 functions to transmit the read current of the TMR element 10 to the drain electrode 22 of the read transistor 15 through the read connection hole 20 and the read land 21.

  In writing to the TMR element 10, a current is passed through the bit line 11 and the write word line 12, and the TMR of the memory cell at the intersection of the bit line 11 and the write word line 12 is generated by a combined magnetic field generated therefrom. The magnetization direction of the magnetization free layer (memory layer) 2 of the element 10 is set to “parallel” or “anti-parallel” with respect to the magnetization fixed layer, and this direction corresponds to information “0” and “1”. Let

The magnetic field in the memory cell is applied by the write current flowing through the bit line 11 with the magnetic field H _{EA in the} easy axis direction, and is applied by the write current flowing through the write word line 12 with the magnetic field H _{HA in the} hard axis direction. A combined magnetic field is provided by vector synthesis of the magnetic fields _HEA and _HHA .

FIG. 24 is an asteroid curve showing the write condition of the MRAM, and shows the threshold value at which the magnetization direction of the magnetization free layer (memory layer) 2 is reversed by the applied magnetic fields _HEA and _HHA . When a synthetic magnetic field corresponding to the outside of the asteroid curve is generated, magnetization reversal is possible. However, in the synthetic magnetic field inside the asteroid curve, the magnetization direction of the magnetization free layer (memory layer) 2 is reversed from one to the other. I can't let you. In MRAM, magnetic fields H _EA and H _HA that do not cause magnetization reversal with only one of magnetic fields H _EA and H _HA are applied, and magnetic spin reversal is applied only to specified memory cells using asteroid magnetization reversal characteristics. Wake up and write.

However, since the magnetic field generated by the bit line 11 or the write word line 12 alone is also applied to the cells other than the intersection of the bit line 11 and the write word line 12 through which a current flows, their magnitudes are equal to each other. In the case of the direction reversal magnetic field H _K or more, the magnetization direction of the cell other than the intersection is also reversed. Therefore, the current flowing in the bit line 11 and the write word line 12 is prevented so that the magnetization direction of the magnetization free layer (storage layer) 2 does not reverse in the magnetic field generated by the bit line 11 or the write word line 12 alone. The size is adjusted so that the combined magnetic field falls within the gray area in the figure.

  Information is read using the TMR effect using the magnetoresistive effect, and current is supplied from the bit line 11 between the magnetization free layer (memory layer) 2 and the magnetic fixed layers 4 to 7 with the tunnel barrier layer 2 interposed therebetween. (Tunnel current) is supplied, and an output current corresponding to the level of the resistance is taken out to the sense line 14 via the read field effect transistor 15.

  Next, the flow of the manufacturing process of the MRAM shown in FIG. 1 will be described with reference to the schematic sectional views of FIGS. Materials for wiring layers such as the write word line 12, the read land 21, the drain electrode land 37 of the peripheral circuit transistor 30, and the lower connection wiring 38 are used in general semiconductor processes such as copper and aluminum. A metal material for wiring can be used.

  First, in FIGS. 2A to 4J, a transistor is formed on a substrate, and a lower wiring is formed in an insulating film stacked thereon.

  First, as shown in FIG. 2A, the main parts of the read MOS field effect transistor 15 and the peripheral circuit field effect transistor 30 are formed in the well region 28 of the semiconductor substrate by a known semiconductor technique.

  For example, after a laminated film of a silicon oxide film and a silicon nitride film is formed on the surface of the p-type region 28 of the silicon substrate, patterning is performed by a photolithography technique and dry etching, and the exposed inactive region is subjected to STI (Shallow Trench Isolation). ) Or an isolation structure by the oxide film 41 by LOCOS (Local Oxidation of Silicon). Next, after removing the laminated film, a silicon oxide film is formed by a thermal oxidation method, a polycrystalline silicon film is formed thereon by a CVD (Chemical Vapor Deposition) method, and patterned by a photolithography technique and dry etching to form a gate. Electrodes 13 and 33 are formed. Subsequently, the silicon oxide films other than the gate insulating films 24 and 34 are removed by etching using the gate electrodes 13 and 33 as a mask. Thereafter, phosphorus, arsenic, or the like is ion-implanted into the N channel region to form drain regions 22 and 32 and source regions 25 and 35.

  Next, as shown in FIG. 2B, a silicon oxide film is deposited as the interlayer insulating film 42 by the CVD method and patterned by photolithography and dry etching to form an opening 43 in the interlayer insulating film 42. .

  Next, as shown in FIG. 2C, a titanium nitride thin film (not shown) is formed on the surface as a barrier layer by a sputtering method, and then tungsten or the like is buried in the opening 43 by a CVD method. The source electrode 26 made of a tungsten plug is formed by planarization by CMP (Chemical and Mechanical Polishing). At this time, CMP is performed up to the point where the thin film of titanium nitride adhering to other than the opening 43 can be completely removed (the same applies hereinafter).

  Next, as shown in FIG. 2D, a thin film made of aluminum or the like is formed by sputtering or vapor deposition, and patterning is performed by photolithography and dry etching to form the sense line 14.

  Next, as shown in FIG. 3E, a silicon oxide film or the like is deposited thereon as the interlayer insulating film 44 by the CVD method and patterned by photolithography and dry etching to form the interlayer insulating films 44 and 42. A penetrating opening 45 is formed.

  Next, as shown in FIG. 3F, a titanium nitride thin film (not shown) is formed as a barrier layer on the entire surface of the interlayer insulating film 44 by sputtering as in the case of FIG. 2C. Thereafter, tungsten or the like is buried in the opening 43 by the CVD method, and then the surface is planarized by the CMP method to form the drain electrode 22, the drain electrode 31, and the source electrode 36 made of a tungsten plug.

  Next, as shown in FIG. 3G, a silicon oxide film is deposited as an interlayer insulating film 46 by a CVD method, and patterned by photolithography and dry etching, and a wiring groove 47 and an opening 48 are formed in the interlayer insulating film 46. Form.

  Next, as shown in FIG. 3H, a thin film (not shown) of tantalum or tantalum nitride is formed as a barrier layer on the entire surface of the interlayer insulating film 46 by sputtering, and then the wiring grooves 47 and openings are formed by CVD. 48 is filled with copper. Subsequently, the surface is planarized by CMP to form the write word line 12, the read land 21, the drain electrode land 37 of the peripheral circuit transistor 30, and the lower connection wiring 38. Copper embedding may be performed by copper plating.

  When aluminum is used instead of copper, a thin film such as aluminum is formed by sputtering or vapor deposition, and patterned by photolithography and dry etching, as in the case of FIG. 12. After forming the read land 21, the drain electrode land 37 of the peripheral circuit transistor 30, and the lower connection wiring 38, an interlayer insulating film 46 made of silicon oxide is formed by CVD, and the surface is flattened by etch back. .

  Next, as shown in FIG. 4I, after a silicon nitride film is formed by the CVD method as the diffusion preventing film 49 for preventing the diffusion of copper ions, a silicon oxide film is deposited as the interlayer insulating film 50 by the CVD method. Then, the opening 51 is formed by patterning by photolithography and dry etching.

  Next, as shown in FIG. 4 (j), a titanium nitride thin film (not shown) is used as a barrier layer on the entire surface of the interlayer insulating film 50 in the same manner as in FIGS. 2 (c) and 3 (f). Then, tungsten or the like is buried in the opening 51 by the CVD method, and then the surface is flattened by the CMP method to form the read plug 20 made of a tungsten plug. The read plug 20 is a connection hole for connecting the TMR element 10 to be formed next and the read transistor 15.

  With the above, the formation of the lower wiring is completed. Next, in FIGS. 4 (k) to 5 (n), the TMR element 10 including the layers 1 to 8 is formed, and a part of the layers 4 to 8 is patterned. Thus, the readout wiring 19 is formed.

  First, as shown in FIG. 4K, the entire surface is formed by sputtering or the like, for example, a tantalum layer as the base electrode layer 8 / a manganese alloy layer such as platinum as the antiferromagnetic layer 7 / the second magnetization fixed layer 6. As a conductor layer 5 for antiferromagnetically coupling an iron-cobalt alloy layer / magnetic layer as a ruthenium layer / first magnetization fixed layer 4 as an iron-cobalt alloy layer / tunnel barrier layer 3 as an aluminum oxide layer / magnetization An alloy layer of iron, cobalt, and boron as the free layer 2 is laminated with a thallium layer as the topcoat layer 1 to form each layer constituting the TMR element 10.

  The tunnel barrier layer 3 can be obtained by oxidizing or nitriding a metal film formed by sputtering. Further, the top coat layer 1 has a role of preventing mutual diffusion between the TMR element 10 and wiring connected to the TMR element, reducing contact resistance, and preventing the magnetization free layer 2 from being oxidized.

  Next, as shown in FIG. 5L, a resist mask 52 is formed by photolithography, and the topcoat layer 1 is processed into the shape of a TMR element by dry etching using the resist mask 52 as a mask.

  Next, as shown in FIG. 5 (m), the memory layer 2 and the tunnel barrier layer 3 are etched using the top coat layer 1 as a mask to be processed into the shape of the TMR element.

  Next, as shown in FIG. 5N, a resist mask 53 is formed by photolithography, and the remaining layers 4 to 8 are etched to be processed into the shape of the readout wiring 19. Thereafter, the resist mask 53 is removed, and the formation of the TMR element 10 and the readout wiring 19 is completed. Here, the portions of the read wiring 19 in the layers 4 to 8 are arranged so as not to overlap the write word line 12 in the vertical direction.

  Next, as a third stage, the bit line 11 is formed in the memory cell portion in FIGS. 6 (o) to 7 (r). As a material of the bit line 11, a wiring metal material used in a general semiconductor process such as copper or aluminum can be used. Further, the surface of the bit line 11 not facing the TMR element 10, that is, the upper surface and the side surface is made of a magnetic material so that the efficiency of generating a magnetic field at the position of the TMR element 10 by the current flowing through the bit line 11 is improved. It is good also as a structure covered with.

  First, as shown in FIG. 6O, a silicon oxide film is deposited as the interlayer insulating film 54 by the CVD method, and the TMR element 10 and the readout wiring 19 are embedded. Next, a silicon nitride film as a diffusion preventing film 55 for preventing diffusion of copper used for the bit line 11 and a silicon oxide film as an interlayer insulating film 56 are laminated and deposited on the entire surface of the substrate by CVD. .

  Next, as shown in FIG. 6P, patterning is performed by a photolithography technique and dry etching to form a wiring groove 57.

  Next, as shown in FIG. 6 (q), an opening 58 for connecting to the topcoat layer 1 of the TMR element 10 is formed.

  Next, as shown in FIG. 7 (r), a tantalum or tantalum nitride thin film (not shown) is formed on the entire surface by sputtering as in FIG. 3 (h), and then wiring by CVD. Copper is embedded in the trench 58, and then the surface is planarized by CMP to form the bit line 11. Copper embedding may be performed by copper plating.

  In the case of using aluminum instead of copper, as in the case of FIG. 2D, a thin film such as aluminum is formed by sputtering or vapor deposition, and patterning is performed by photolithography and dry etching to form the bit line 11. After the formation, an interlayer insulating film 56 made of silicon oxide is formed by CVD, and the surface is flattened by etch back.

  Next, as the last step, in FIGS. 7 (s) to 9 (x), the upper connection wiring 65 to the bit line 11 is formed in the peripheral circuit portion, and then the protective layer is formed on the surface. Thereafter, the memory device is completed through a general semiconductor process. As a material of the upper connection wiring 65, a wiring metal material used in a general semiconductor process such as copper or aluminum can be used.

  First, as shown in FIG. 7S, a silicon nitride film as a diffusion preventing film 59 for preventing diffusion of copper used for the upper connection wiring 65 and a silicon oxide film as an interlayer insulating film 60 are formed by CVD. Are stacked and deposited on the entire surface of the substrate.

  Next, as shown in FIG. 7 (t), patterning is performed by a photolithography technique and dry etching to form a recess 61a at a position where a connection hole to the peripheral circuit transistor 30 is formed.

  Next, as shown in FIG. 8 (u), patterning is performed by a photolithography technique and dry etching to form a wiring groove 62. At this time, the opening 61a formed earlier is further increased in depth, and a recess 61b reaching the diffusion prevention film 49 is formed.

  Next, as shown in FIG. 8V, an opening 63 of the diffusion prevention film 59 and an opening 64 reaching the drain electrode land 37 are formed by photolithography and dry etching.

  Next, as shown in FIG. 9 (w), a thin film (not shown) of tantalum or tantalum nitride is formed as a barrier layer on the entire surface by sputtering, and then the wiring trench 62 and the opening 64 are formed by plating or CVD. Copper is buried, and then the surface is planarized by CMP to form an upper connection wiring 65 and a connection portion 66 to the bit line 11.

  When aluminum instead of copper is used, a thin film such as aluminum is formed by sputtering or vapor deposition, and patterned by photolithography and dry etching, as in the case of FIG. Then, an interlayer insulating film 60 made of silicon oxide is formed by CVD, and the surface is flattened by etch back.

  Next, as shown in FIG. 9 (x), a silicon nitride film is formed as a diffusion prevention film 67 for preventing diffusion of copper used for the upper connection wiring 65 by the CVD method, and then a surface protective layer is formed. 68, a silicon oxide film is deposited on the entire surface of the substrate. Thereafter, the memory device is completed through a general semiconductor process.

Embodiment 2
FIG. 10 is a schematic cross-sectional view of the boundary region between the memory unit and the peripheral circuit unit, showing the structure of the magnetic memory device according to the second embodiment.

  In the magnetic memory device according to the first embodiment shown in FIG. 1, a diffusion prevention film 59 and an interlayer insulating film 60 are formed on the interlayer insulating film 56 provided with the bit line 11 to form the interlayer insulating film 60. Since the upper connection wiring 65 to the bit line 11 is formed, the bit line 11 (the first wiring) and the upper connection wiring 65 (the third wiring) overlap with each other through the diffusion prevention film 59. Both of them can be directly connected by the connecting portion 66 without providing an interlayer insulating film or a connection hole, and there is an advantage that a manufacturing process is reduced.

On the other hand, in the magnetic memory device based on the second embodiment shown in FIG. 10, a diffusion prevention film 71 and an interlayer insulation film 72 are formed as separate insulation layers on the interlayer insulation film 56 provided with the bit line 11. A connection hole 73 is provided in these insulating films, and the bit line 11 (the first wiring) and the upper connection wiring 65 are connected through the connection hole 73. In this case, the distance L between the upper connection wiring 65 (the third wiring) and the lower connection wiring 38 (the fourth wiring) is
L = x + y + l + m
Given in. Here, m is the total film thickness of the diffusion preventing film 71 and the interlayer insulating film 72. The present embodiment has an advantage that the distance L and the parasitic capacitance between the upper connection wiring 65 and the lower connection wiring 38 (the fourth wiring) can be adjusted by appropriately selecting the thickness and material of the interlayer insulating film 72. It is possible to achieve both low power consumption and high integration of the device and high-speed operation of the memory device.

Embodiment 3
FIG. 11 is a schematic cross-sectional view of the boundary region between the memory unit and the peripheral circuit unit, showing the structure of the magnetic memory device according to the third embodiment.

  In the first and second embodiments, the upper upper connection wiring 65 is provided above the bit line 11. However, in the magnetic memory device according to the present embodiment shown in FIG. This is a method of being provided below the write word line 12.

The distance L between the upper connection wiring 65 (the third wiring) and the lower connection wiring 38 (the fourth wiring) is:
L = x + y + n
Given in. Here, n is the total thickness of the diffusion preventing film 49 and the interlayer insulating film 50. Also in the present embodiment, by appropriately setting the film thickness of the interlayer insulating film 50 and the like, it is possible to achieve both low power consumption and high integration of the memory device and high-speed operation of the memory device.

Embodiment 4
FIG. 12 is a schematic cross-sectional view showing the structure of the magnetic memory device according to the fourth embodiment. This is a schematic sectional view taken up and down at the position of the ZZ line shown in FIG.

  In the first to third embodiments, the connection wiring for driving the bit line 11 has been studied, but in the present embodiment, the connection wiring for driving the write word line 12 is studied. As described with reference to FIG. 23, the write word line 12 is connected to the write word line current drive circuit 17 in the peripheral circuit portion, and the transistor 30 shown on the right side of FIG. It forms part of the current drive circuit 17.

Also in this case, in the conventional magnetic memory device, the bit line 11 and the write word line 12 of the memory unit and the connection wiring of the peripheral circuit unit that drives the write word line 12 are formed in the same insulating layer. Between the distance L between the connection wirings of the peripheral circuit part and the x and y,
L = x + y
As x and / or y are reduced in order to reduce the power consumption and increase the integration of the TMR element 10, the distance L between the connection wirings of the peripheral circuits also decreases, and the connection wirings As a result, an increase in circuit delay due to an increase in the parasitic capacitance of the memory device causes a problem that low power consumption and high integration of the memory device cannot be compatible with high-speed operation of the memory device.

On the other hand, in the present embodiment, since the lower connection wiring 92 of the peripheral circuit section for driving the write word line 12 is provided in the interlayer insulating film 44 below the write word line 12, Between the distance L between the connection wiring 92 and the lower connection wiring 94 and x and y,
L = x + y + k
There is a relationship. Here, k is the total thickness of the interlayer insulating film 46 and the diffusion prevention film 93. Also in this embodiment, by appropriately setting the film thickness of the interlayer insulating film 46 and the like, it is possible to achieve both low power consumption and high integration of the memory device and high-speed operation of the memory device.

Embodiment 5
FIG. 13 is a schematic sectional view showing the structure of the magnetic memory device according to the fifth embodiment. The basic structure of this magnetic memory device is the same as that of the magnetic memory device according to the first embodiment shown in FIG. 1 except that the bit line 11 and the write word line 12 are other than the surface facing the TMR element 10. The only difference is that the surface is covered with the magnetic layers 101, 103, and 105.

  Since it is covered with the magnetic layers 101, 103, and 105, the magnetic flux generated by the current flowing through the bit line 11 and the write word line 12 is collected in the TMR element 10, and a magnetic field having a required strength can be obtained with less current. It is formed. The magnetic layer is preferably formed on the bit line 11 and the write word line 12, and need not be provided on the upper connection wiring and the lower connection wiring of the peripheral circuit portion (however, the bit line 11 and the write word line are not provided). 12 may be inevitably formed in a wiring made in the same process as that of No. 12). The magnetic material having a high effect of concentrating the magnetic flux on the TMR element 10 is desirably a material having a high magnetic permeability, such as permalloy.

Since other parts are the same as those of the first embodiment, detailed description thereof is omitted, but it is needless to say that the same features as those of the first embodiment are provided. That is, since the diffusion prevention film 59 and the interlayer insulating film 60 are formed on the interlayer insulating film 56 provided with the bit line 11 and the upper connection wiring 65 to the bit line 11 is formed in the interlayer insulating film 60, The distance L between the upper connection wiring 65 and the lower connection wiring 38 in the peripheral circuit portion is:
L = x + y + (total thickness of diffusion preventing film 55, interlayer insulating film 56, and diffusion preventing film 59)
It becomes.
By reducing the distances (x and y) between the bit line 11 and the write word line 12 and the magnetization free layer 2 of the TMR element 10 as much as possible, the current flowing through the bit line 11 and the write word line 12 flows in the magnetization free layer 2. The efficiency of generating a magnetic field can be improved, and low power consumption and high integration of the memory device can be realized. At this time, if an interlayer insulating film 56 having an appropriate film thickness is provided, a sufficient distance L can be secured between the upper connection wiring 65 and the lower connection wiring 38 in the peripheral circuit portion, so that a circuit due to an increase in parasitic capacitance can be secured. There is no delay problem. As a result, it is possible to achieve both low power consumption and high integration of the memory device and high-speed operation of the memory device.

  Further, the bit line 11 and the upper connection wiring 65 overlap with each other through the diffusion prevention film 59, and both can be directly connected by the connection portion 66 without providing an interlayer insulating film or a connection hole therebetween. There is an advantage that the number of processes is reduced.

  Next, a manufacturing method of the magnetic memory device according to the present embodiment will be described with emphasis on the method of forming the magnetic layers 101, 103, and 105, which is a difference from the first embodiment.

  First, as shown in FIG. 14A, the field effect transistor 15 is formed on the surface of the p-type region 28 of the silicon substrate, for example, by the steps shown in FIGS. 2A to 3F of the first embodiment. 30 and the interlayer insulating films 42 and 44 laminated thereon, the sense line 14 made of aluminum wiring, the drain electrode 22 made of tungsten plug, the source electrode 26, the drain electrode 31, and the source electrode 36 are formed. .

  Next, as shown in FIG. 14B, a silicon oxide film is deposited as an interlayer insulating film 46 by a CVD method and patterned by photolithography and dry etching to form wiring grooves 47 and openings 48.

  Next, after a tantalum or tantalum nitride thin film (not shown) is formed as a barrier layer on the entire surface of the interlayer insulating film 46 by sputtering, the magnetic layer 101 is sputtered on the entire surface as shown in FIG. Formed by. As a material of the magnetic layer 101, for example, permalloy (NiFe) is preferably used.

  Next, as shown in FIG. 14D, a copper layer 102 as a wiring material is formed on the entire surface of the interlayer insulating film 46 by a plating method, and copper is embedded in the wiring trench 47 and the opening 48. The copper layer 102 may be formed by a CVD method.

  Subsequently, the copper layer 102 is first polished by the CMP method, and then the magnetic layer 101 is polished to flatten the surface, and the copper layer 102 and the magnetic layer adhered to other than the wiring groove 47 and the opening 48. As shown in FIG. 15E, the write word line 12 having a clad structure in which the three surfaces other than the upper surface are covered with the magnetic layer 101 is obtained.

  Next, after a silicon nitride film is formed as a diffusion preventing film 49 for preventing the diffusion of copper ions by the CVD method, a silicon oxide film is deposited as the interlayer insulating film 50 by the CVD method, and patterned by a photolithography technique and dry etching. To form an opening. After forming a thin film of titanium nitride (not shown) as a barrier layer over the entire surface of the interlayer insulating film 50 by sputtering, tungsten or the like is buried in the opening by CVD, and then the surface is planarized by CMP. As shown in FIG. 15F, a read plug 20 made of a tungsten plug is formed.

  Next, the TMR element 10 and the read plug 20 for connecting the base electrode layer to the read plug 20 are formed by the steps shown in FIGS. 4K to 5N of the first embodiment. Make it. First, the layers constituting the TMR element 10 are formed by laminating the entire surface of the substrate by sputtering or the like, and this is formed by photolithography and dry etching, as shown in FIG. Processed into 19 shapes.

  Next, as shown in FIG. 15H, a silicon nitride film as an anti-diffusion film 55 for preventing diffusion of copper used as the bit line 11 and an interlayer insulating film for forming the bit line 11 are formed by CVD. As 56, a silicon oxide film is deposited on the entire surface of the substrate.

  Next, as shown in FIG. 16 (i), patterning is performed by photolithography and dry etching to form a wiring groove 57 and an opening 58 for connecting to the topcoat layer 1 of the TMR element 10 is formed. .

  Next, after a tantalum or tantalum nitride thin film (not shown) is formed on the entire surface by sputtering as a barrier layer, a magnetic layer 103 is formed on the entire surface by sputtering as shown in FIG. Examples of the magnetic material having a high effect of concentrating the magnetic flux include permalloy (NiFe).

  Next, as shown in FIG. 16K, the magnetic layer 103 at the bottom of the wiring groove 57 is removed by etching. As a result, the magnetic layer 103 remains only on the side wall of the wiring groove 57 on the substrate.

  Next, as shown in FIG. 17L, copper, which is a wiring material, is formed on the entire surface of the interlayer insulating film 56 by a plating method, and the copper layer 104 is embedded in the wiring groove 57. The copper layer 102 may be formed by a CVD method.

  Subsequently, as shown in FIG. 17 (m), the copper layer 104 is first polished by the CMP method to flatten the surface and remove the copper and magnetic material adhering to other than the wiring grooves 57, and the side surfaces are magnetic. The bit line 11 covered with the body layer 103 is obtained.

  Next, as shown in FIG. 17 (n), a magnetic layer 105 is formed on the entire surface by sputtering.

  Next, as shown in FIG. 18 (o), the magnetic layer 105 is patterned on the upper portion of the bit line 11 by lithography and etching, so that the three surfaces other than the bottom surface are covered with the magnetic layers 103 and 105. In addition, the bit line 11 having a cladding structure is obtained.

  Next, as shown in FIG. 18 (p), a silicon nitride film as a diffusion preventing film 59 for preventing diffusion of copper used for the upper connection wiring 65 and a silicon oxide film as an interlayer insulating film 60 are formed by CVD. Are stacked and deposited on the entire surface of the substrate.

  Next, as shown in FIG. 18 (q), by the steps shown in FIGS. 7 (t) to 8 (v) of the first embodiment, patterning is performed by a photolithography technique and dry etching, and wiring trenches 62, A through hole 64 for connecting to the drain electrode of the peripheral circuit transistor 30 and an opening 63 serving as a connecting portion to the bit line 11 are formed.

  Next, after forming a thin film (not shown) of tantalum or tantalum nitride as a barrier layer on the entire surface by sputtering, copper is formed on the entire surface by plating as shown in FIG. Then, copper is embedded in the through hole 64. Copper embedding may be performed by a CVD method.

  Next, as shown in FIG. 19 (s), the copper layer 106 is polished by CMP to planarize the surface and remove the copper layer 106 adhering to portions other than the wiring trenches 62 to obtain the upper connection wiring 65. .

  Next, although not shown, a silicon nitride film is formed as a diffusion prevention film 67 for preventing diffusion of copper used for the upper connection wiring 65 by CVD, and then a silicon oxide film is used as the surface protection layer 68. Is deposited on the entire surface of the substrate. Thereafter, the magnetic memory device according to the fifth embodiment is completed through a general semiconductor process.

  As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to these examples at all, and can be suitably changed in the range which does not deviate from the main point of invention.

  MRAM is considered to be indispensable in the ubiquitous era as a high-speed and non-volatile large-capacity memory, and it is considered that all electronic devices, in particular, higher speed, lower power consumption, higher integration, etc. It is suitable for information communication equipment for which performance enhancement is required, particularly for personal small equipment such as a portable terminal.

1 is a schematic cross-sectional view of a magnetic memory device (MRAM) based on Embodiment 1 of the present invention. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing of the magnetic memory device (MRAM) based on Embodiment 2 of this invention. It is a schematic sectional drawing of the magnetic memory device (MRAM) based on Embodiment 3 of this invention. It is a schematic sectional drawing of the magnetic memory device (MRAM) based on Embodiment 4 of this invention. It is a schematic sectional drawing of the magnetic memory device (MRAM) based on Embodiment 5 of this invention. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic sectional drawing which shows the manufacturing process of a magnetic memory device equally. It is a schematic perspective view of the TMR element of MRAM. It is a schematic perspective view of a part of the memory cell portion of the MRAM. It is an equivalent circuit diagram of MRAM. It is an equivalent circuit diagram of MRAM. It is a magnetic field response characteristic figure at the time of writing of MRAM. It is a read operation principle diagram of MRAM. It is a schematic sectional drawing of the conventional magnetic memory device (MRAM).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Topcoat layer, 2 ... Magnetization free layer (memory layer), 3 ... Tunnel barrier layer,
4 ... 1st magnetization fixed layer, 5 ... Antiferromagnetic coupling layer, 6 ... 2nd magnetization fixed layer,
7 ... Antiferromagnetic material layer, 8 ... Under electrode layer, 9 ... Support substrate, 10 ... Memory cell (TMR element),
11: Bit line, 12: Write word line,
13: Gate electrode (read word line), 14: Sense line,
15: Field effect transistor for reading (selection transistor),
16 ... bit line current drive circuit, 17 ... word line current drive circuit, 18 ... sense amplifier,
19 ... Reading wiring, 20 ... Reading plug, 21 ... Reading land,
22 ... Drain electrode, 23 ... Drain region, 24 ... Gate insulating film, 25 ... Source region,
26 ... Source electrode, 27 ... Silicon substrate, 28 ... Well region,
30 ... peripheral circuit transistor, 31 ... drain electrode, 32 ... drain region,
33 ... Gate electrode, 34 ... Gate insulating film, 35 ... Source region, 36 ... Source electrode,
37 ... Drain electrode land, 38 ... Lower connection wiring,
41 ... Silicon oxide film (for example, LOCOS and STI),
42, 44, 46, 50, 54, 56, 60 ... interlayer insulating film,
43, 45, 48, 51, 58, 62, 63 ... opening, 47, 57, 61 ... wiring groove,
49, 55, 59, 67 ... Diffusion prevention film (silicon nitride), 52, 53 ... Resist mask, 64 ... Through hole, 65 ... Connection part, 66 ... Bit connection line, 68 ... Insulating film, 71 ... Diffusion prevention film, 72 ... Interlayer insulating film, 74 ... Connection hole, 81, 84, 86 ... Diffusion prevention film,
82, 83, 85 ... interlayer insulating films, 101, 103, 105 ... magnetic layers,
102, 104, 106 ... copper layer, 201, 204 ... diffusion prevention film, 202 ... interlayer insulation film,
205 ... Insulating film

Claims (8)

A magnetic memory element is configured by a tunnel magnetoresistive effect element in which a magnetization fixed layer with a fixed magnetization direction, a tunnel barrier layer, and a magnetization free layer capable of changing the magnetization direction are stacked. A first wiring connected to the tunnel magnetoresistive effect element is formed via a first insulating layer provided in a portion other than the connection part with the tunnel magnetoresistive effect element, and A second wiring is disposed opposite to the tunnel magnetoresistive element through a second insulating layer on the opposite side of the first wiring, and the tunnel magnetoresistive element is formed using the first wiring and the second wiring. In a magnetic memory device configured to perform writing,
The first wiring is connected to a third wiring formed in a state of being separated from the first insulating layer and led to a peripheral circuit portion;
The second wiring is configured to constitute at least one of being connected to a fourth wiring formed in a state of being separated from the second insulating layer and being led to a peripheral circuit portion. Magnetic memory device.   2. The magnetic memory according to claim 1, wherein the first wiring and / or the second wiring are connected to the third wiring and / or the fourth wiring formed through an insulating layer in which the first wiring and / or the second wiring are embedded. apparatus.   The magnetic memory device according to claim 2, wherein the insulating layer and the first wiring or / and the second wiring are present at the same level.   A connection hole is provided in another insulating layer formed on or below the insulating layer, and the first wiring and the third wiring or / and the second wiring and the fourth wiring are connected through the connection hole. The magnetic memory device according to claim 2, wherein:   2. The magnetic memory according to claim 1, wherein at least the first wiring and / or the second wiring is covered with a magnetic layer on at least a part of a surface other than the surface facing the tunnel magnetoresistive element. apparatus.   6. The magnetic memory device according to claim 5, wherein the magnetic layer is formed on the first wiring and / or the second wiring and is not formed on the third wiring or / and the fourth wiring. 7.   2. The magnetic memory device according to claim 1, wherein the first wiring and the second wiring are arranged to intersect with each other, and the tunnel magnetoresistive element is disposed at the intersection.   The tunnel barrier layer is sandwiched between the magnetization fixed layer and the magnetization free layer, and magnetic fields induced by flowing currents to the bit line as the first wiring and the write word line as the second wiring, respectively. 2. The magnetic memory device according to claim 1, wherein information is written by magnetizing the magnetization free layer in a predetermined direction, and the written information is read by a tunnel magnetoresistance effect through the tunnel barrier layer.

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