CN107017275B

CN107017275B - Magnetic memory device

Info

Publication number: CN107017275B
Application number: CN201610900391.1A
Authority: CN
Inventors: 徐辅永; 徐宣揆; 高宽协; 李龙圭
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2015-10-15
Filing date: 2016-10-14
Publication date: 2021-09-14
Anticipated expiration: 2036-10-14
Also published as: KR20170045080A; KR102466880B1; CN107017275A

Abstract

The present disclosure provides magnetic storage devices. A magnetic memory device includes: a substrate; a landing pad on the substrate; a first magnetic tunnel junction pattern and a second magnetic tunnel junction pattern disposed on the substrate and spaced apart from the landing pad when viewed from a plan view; and A connecting structure electrically connects the top surface of the second magnetic tunnel junction pattern to the landing pad. When viewed from a plan view, the distance between the landing pad and the first magnetic tunnel junction pattern is greater than the distance between the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern, and the landing pad and the second magnetic tunnel junction pattern The distance therebetween is greater than the distance between the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern.

Description

Magnetic memory device

Technical Field

Embodiments of the inventive concepts relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a magnetic memory device including a magnetic tunnel junction pattern and a method of manufacturing the same.

Background

A memory device that can be read/written quickly and has a low voltage is required for high-speed and low-power consumption electronic products. Magnetic storage devices have been developed to meet these needs. Magnetic storage devices can meet the demands of next generation storage devices due to their high operating characteristics and ability to store data in a non-volatile manner.

Magnetic storage devices employ Magnetic Tunnel Junction (MTJ) patterns to store information. The magnetic tunnel junction pattern may include two magnetic layers and an insulating layer disposed between the two magnetic layers. The resistance of the magnetic tunnel junction pattern depends on the magnetization directions of the two magnetic layers. For example, when the magnetization directions of the two magnetic layers are antiparallel to each other, the magnetic tunnel junction pattern may have a relatively large resistance. When the magnetization directions of the two magnetic layers are parallel to each other, the magnetic tunnel junction pattern may have a relatively small resistance. The magnetic memory device may read/write data using a difference between resistances of the magnetic tunnel junction patterns.

In spin transfer torque magnetic random access memory (STT-MRAM) devices, the magnitude of a write current required to write data to a magnetic cell may decrease as the size of the magnetic cell decreases. Therefore, it is desirable to reduce the size of STT-MRAM devices.

Disclosure of Invention

Embodiments of the inventive concept provide a magnetic storage device having improved reliability.

In one aspect, a magnetic storage device may include: a substrate; a landing pad (landing pad) on the substrate; a first magnetic tunnel junction pattern and a second magnetic tunnel junction pattern disposed on the substrate and spaced apart from the landing pad when viewed from a plan view; and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. The first and second magnetic tunnel junction patterns may be spaced apart from each other by a first distance when viewed in a plan view. A distance between the landing pad and the first magnetic tunnel junction pattern may be greater than the first distance when viewed from a plan view. A distance between the landing pad and the second magnetic tunnel junction pattern may be greater than the first distance when viewed from a plan view.

In one aspect, a magnetic storage device may include at least one memory column, each memory column including a plurality of unit memory cells arranged in a first direction. Each unit memory cell may include: landing pads; a first magnetic tunnel junction pattern separated from the landing pad by a first distance when viewed from a plan view; a second magnetic tunnel junction pattern separated from the landing pad by a second distance and separated from the first magnetic tunnel junction pattern by a third distance when viewed from a plan view; and an interconnection structure electrically connecting the landing pad to a top surface of the second magnetic tunnel junction pattern. The first distance and the second distance may be greater than the third distance.

In another aspect, a magnetic memory device includes a substrate, an interlayer insulating layer on the substrate, and a magnetic memory cell on the substrate. The magnetic memory cell includes: a landing pad on the substrate; a first magnetic tunnel junction pattern and a second magnetic tunnel junction pattern on the interlayer insulating layer and spaced apart from the landing pad; a first bit line conductively connected to an upper portion of the first magnetic tunnel junction pattern; a second bit line conductively connected to a lower portion of the second magnetic tunnel junction pattern; and an interconnect structure on the landing pad, the interconnect structure passing through the interlayer insulating layer and conductively connecting the landing pad to an upper portion of the second magnetic tunnel junction pattern. A first separation distance between the second magnetic tunnel junction pattern and the landing pad is greater than a second separation distance between the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern.

Drawings

The inventive concept will become more apparent in light of the attached drawings and accompanying detailed description.

FIG. 1 is a schematic block diagram illustrating a magnetic storage device according to some embodiments of the inventive concept.

Fig. 2 is a circuit diagram illustrating a cell array of a magnetic memory device according to some embodiments of the inventive concept.

Fig. 3 is a circuit diagram illustrating a unit memory cell of a magnetic storage device according to some embodiments of the inventive concept.

Fig. 4 is a plan view illustrating a unit memory cell of a magnetic storage device according to some embodiments of the inventive concept.

Fig. 5 is a sectional view taken along line I-I' of fig. 4.

Fig. 6 is a plan view illustrating a unit memory cell of a magnetic storage device according to some embodiments of the inventive concept.

Fig. 7A to 7E are plan views illustrating memory cell arrays of magnetic storage devices according to some embodiments of the inventive concepts.

Fig. 8A to 8C are sectional views illustrating a method of manufacturing a unit memory cell of a magnetic storage device according to some embodiments of the inventive concept.

Fig. 9A and 9B are conceptual diagrams illustrating magnetic tunnel junction patterns according to some embodiments of the inventive concept.

Detailed Description

The exemplary embodiments of the aspects of the inventive concept illustrated and described herein include their complementary counterparts. Like reference numerals or like reference indicators denote like elements throughout the specification.

Referring to fig. 1, the magnetic memory device includes a memory cell array 1, a word line decoder 2, a word line driver 3, a bit line decoder 4, a read/write circuit 5, and a control logic circuit 6.

The memory cell array 1 may include a plurality of memory blocks BLK0 through BLKn. Each of the memory blocks BLK0 through BLKn may include a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The word lines, bit lines, and source lines may be electrically connected to the memory cells.

The word line decoder 2 may decode an address signal input from an external system to select one of the word lines. The address signal decoded in the word line decoder 2 may be supplied to the word line driver 3. The word line driver 3 may supply a selected word line voltage and an unselected word line voltage generated from a voltage generation circuit (not shown) to a selected word line and an unselected word line, respectively, in response to a control signal output by the control logic circuit 6. The word line decoder 2 and the word line driver 3 may be commonly connected to the plurality of memory blocks BLK0 through BLKn, and may supply a driving signal to a word line of one memory block selected by the block selection signal.

The bit line decoder 4 may decode an address signal input from an external system to select one of the bit lines. The bit line decoder 4 may be commonly connected to the plurality of memory blocks BLK0 through BLKn, and may supply data to bit lines of a memory block selected by a block selection signal.

The read-write circuit 5 may be connected to the memory cell array 1 through bit lines. The read-write circuit 5 may select one of the bit lines in response to a bit line selection signal received from the bit line decoder 4. The read-write circuit 5 may be configured to exchange data with an external system. The read-write circuit 5 may operate in response to a control signal output by the control logic circuit 6. The read-write circuit 5 may receive power (e.g., voltage or current) from the control logic 6 and may provide the power to the selected bit line.

The control logic 6 may control the overall operation of the magnetic storage device. The control logic circuit 6 may receive a control signal and an external voltage, and may operate in response to the received control signal. The control logic circuit 6 can generate the power necessary for the read/write operation by means of an external voltage. The control logic 6 may control read, write and/or erase operations in response to control signals.

Fig. 2 is a circuit diagram illustrating a cell array of a magnetic memory device according to some embodiments of the inventive concept. For example, fig. 2 is a circuit diagram illustrating an embodiment of the memory cell array described with reference to fig. 1.

Referring to fig. 2, the memory cell array 1 may include a plurality of word lines WL, a plurality of bit lines BL1 and BL2, a plurality of source lines SL, and a plurality of unit memory cells 10. The bit lines BL1 and BL2 may cross the word line WL. As shown in fig. 2, the source lines SL may be parallel to the bit lines BL1 and BL 2. However, the embodiments of the inventive concept are not limited thereto. In some embodiments, unlike fig. 2, the source lines SL may be parallel to the word lines WL.

Each unit memory cell 10 may be connected between one word line WL and a pair of bit lines BL1 and BL2 crossing the one word line WL. Each unit memory cell 10 may include first and second memory elements ME1 and ME2 and first and second select elements SE1 and SE 2.

A first memory element ME1 may be connected between a first select element SE1 and a first bit line BL1, and a second memory element ME2 may be connected between a second select element SE2 and a second bit line BL 2. The first selection element SE1 may be connected between the first memory element ME1 and the source line SL, and the second selection element SE2 may be connected between the second memory element ME2 and the source line SL. The first select element SE1 and the second select element SE2 may share one source line SL and may be controlled by the same word line WL. In addition, the unit memory cells 10 arranged in the first direction or the second direction perpendicular to the first direction may be commonly connected to the source lines SL.

One unit memory cell 10 may be selected by one word line WL and a pair of bit lines BL1 and BL 2. In some embodiments, each of the first memory element ME1 and the second memory element ME2 may be a variable resistance element which is switchable between two resistance states by an electrical pulse applied thereto. The first and second memory elements ME1 and ME2 may be formed of a material having a resistance value that changes according to the magnitude and/or direction of a current or voltage applied thereto, and may have a non-volatile characteristic such that they can maintain the stored resistance value even if the current or voltage to the memory element is interrupted. In some embodiments, each of the first memory element ME1 and the second memory element ME2 may have a magnetoresistive property. In some embodiments, each of the first memory element ME1 and the second memory element ME2 may be a magnetic tunnel junction pattern described later with reference to fig. 9A and/or 9B. In certain embodiments, each of the first memory element ME1 and the second memory element ME2 may include a perovskite compound or a transition metal oxide.

Each of the first and second selection elements SE1, SE2 may be a diode, a PNP bipolar transistor, an NPN bipolar transistor, an NMOS field effect transistor, or a PMOS field effect transistor. In some embodiments, first select element SE1 and second select element SE2 may control the supply of current to first memory element ME1 and second memory element ME2 in response to a voltage on word line WL.

Fig. 3 is a circuit diagram illustrating a unit memory cell of a magnetic storage device according to some embodiments of the inventive concept. For example, fig. 3 is a circuit diagram illustrating an embodiment of the unit memory cell described with reference to fig. 2.

Referring to fig. 3, the unit memory cell 10 may include first and second magnetic tunnel junction patterns MTJP1 and MTJP2 serving as memory elements ME1 and ME2, and first and second selection transistors SE1 and SE2 serving as the above selection elements SE1 and SE 2. The first magnetic tunnel junction pattern MTJP1 may include a first free pattern FP1, a first pinned pattern PP1, and a first tunnel barrier pattern TBP1 disposed between the first free pattern FP1 and the first pinned pattern PP 1. Likewise, the second magnetic tunnel junction pattern MTJP2 may include a second free pattern FP2, a second pinned pattern PP2, and a second tunnel barrier pattern TBP2 disposed between the second free pattern FP2 and the second pinned pattern PP 2. Each of the first and second pinned patterns PP1 and PP2 may have a magnetization direction fixed in one direction. The first free pattern FP1 may have a magnetization direction changeable to be parallel or anti-parallel to the magnetization direction of the first pinned pattern PP1, and the second free pattern FP2 may have a magnetization direction changeable to be parallel or anti-parallel to the magnetization direction of the second pinned pattern PP 2. According to some embodiments of the inventive concept, each of the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially similar to a magnetic tunnel junction pattern described later with reference to fig. 9A and/or 9B.

The first bit line BL1 and the second bit line BL2 may cross the word line WL, and the source line SL may be commonly connected to the first select transistor SE1 and the second select transistor SE 2. The first magnetic tunnel junction pattern MTJP1 may be connected between the first bit line BL1 and the first selection transistor SE1, and the first selection transistor SE1 may be connected between the first magnetic tunnel junction pattern MTJP1 and the source line SL. The second magnetic tunnel junction pattern MTJP2 may be connected between the second bit line BL2 and the second selection transistor SE2, and the second selection transistor SE2 may be connected between the second magnetic tunnel junction pattern MTJP2 and the source line SL.

In some embodiments, as shown in fig. 3, the first free pattern FP1 may be connected to the first bit line BL1, and the first pinned pattern PP1 may be connected to the first selection transistor SE 1. In these embodiments, the second free pattern FP2 may be connected to the second selection transistor SE2, and the second pinned pattern PP2 may be connected to the second bit line BL 2.

In some embodiments, unlike fig. 3, the first pinned pattern PP1 may be connected to the first bit line BL1, and the first free pattern FP1 may be connected to the first selection transistor SE 1. In these embodiments, the second pinned pattern PP2 may be connected to the second selection transistor SE2, and the second free pattern FP2 may be connected to the second bit line BL 2. Hereinafter, for the purpose of ease and convenience of explanation, the unit memory cell 10 shown in fig. 3 will be described as an example.

In some embodiments, to write a data value of 1 into a selected unit memory cell 10, a turn-on voltage may be applied to a word line WL connected to the selected unit memory cell 10. A first bit line voltage may be applied to the first bit line BL1 and the second bit line BL2, and a first source line voltage lower than the first bit line voltage may be applied to the source lines SL.

Under these voltage conditions, the first and second selection transistors SE1 and SE2 may be turned on to electrically connect the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 to the source line SL, respectively. First write current I flowing from first bit line BL1 to source line SL_W1The second write current I that may be supplied to the first magnetic tunnel junction pattern MTJP1 and flows from the second bit line BL2 to the source line SL_W2May be provided to the second magnetic tunnel junction pattern MTJP 2. Here, the first write current I is viewed from the viewpoints of the first and second magnetic tunnel junction patterns MTJP1 and MTJP2_W1Can be in the same direction as the second write current I_W2The flow direction of (a) is opposite. In other words, when the same voltage is applied to the first bit line BL1 and the second bit line BL2, write currents flowing in opposite directions to each other may be supplied to the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2, respectively.

More specifically, the first write current I_W1May be provided in a direction from the first free pattern FP1 of the first magnetic tunnel junction pattern MTJP1 to the first pinned pattern PP1, and thus the first write current I_W1May be provided in a direction from the first pinned pattern PP1 to the first free pattern FP 1. In this case, electrons having spins in the same direction as the magnetization direction of the first pinned pattern PP1 may pass through the first tunnel barrier pattern TBP1 (e.g., by a tunneling effect) to apply torque to the first free pattern FP 1. As a result, the magnetization direction of the first free pattern FP1 may be changed to be parallel to the magnetization direction of the first pinned pattern PP 1. Conversely, the second write current I_W2May be provided at the second layer from the second magnetic tunnel junction pattern MTJP2The pinned pattern PP2 to the second free pattern FP2, and thus the second write current I_W2May be provided in a direction from the second free pattern FP2 to the second pinned pattern PP 2. In this case, electrons having spins in a direction opposite to the magnetization direction of the second pinned pattern PP2 cannot pass through the second tunnel barrier pattern TBP2 (by a tunneling effect), but may be reflected from the second tunnel barrier pattern TBP2 into the second free pattern FP2 to apply torque to the second free pattern FP 2. As a result, the magnetization direction of the second free pattern FP2 may be changed to be antiparallel to the magnetization direction of the second pinned pattern PP 2.

As described above, when the data value 1 is written in the selected unit memory cell 10, the first magnetic tunnel junction pattern MTJP1 may be written such that the magnetization direction of the first free pattern FP1 and the magnetization direction of the first pinned pattern PP1 are parallel to each other, and the second magnetic tunnel junction pattern MTJP2 may be written such that the magnetization direction of the second free pattern FP2 and the magnetization direction of the second pinned pattern PP2 are antiparallel to each other. In other words, the first magnetic tunnel junction pattern MTJP1 may have a low resistance state, and the second magnetic tunnel junction pattern MTJP2 may have a high resistance state.

In some embodiments, in order to write a data value of 0 into the selected unit memory cell 10, a turn-on voltage may be applied to the word line WL connected to the selected unit memory cell 10. In addition, a second bit line voltage may be applied to the first bit line BL1 and the second bit line BL2, and a second source line voltage higher than the second bit line voltage may be applied to the source lines SL.

Under these voltage conditions, at the first write current I as described above_W1And a second write current I_W2Currents in opposite directions may be supplied to the first and second magnetic tunnel junction patterns MTJP1 and MTJP2, respectively. Therefore, in contrast to when writing the data value 1, the first magnetic tunnel junction pattern MTJP1 may be written such that the magnetization direction of the first free pattern FP1 and the magnetization direction of the first pinned pattern PP1 are antiparallel to each other, and the second magnetic tunnel junction pattern MTJP2 may be written such that the magnetization direction of the second free pattern FP2 and the second pinned pattern FP2 are antiparallel to each otherThe magnetization directions of the rolling patterns PP2 are parallel to each other. In other words, the first magnetic tunnel junction pattern MTJP1 may have a high resistance state, and the second magnetic tunnel junction pattern MTJP2 may have a low resistance state.

Since the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 have different resistance states from each other as described above, the resistance value of one of the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be used as a reference resistance value when data is read out from the selected unit memory cell 10. Accordingly, the unit memory cell 10 may have a sensing margin (sensing margin) corresponding to a difference between resistance values of the first and second magnetic tunnel junction patterns MTJP1 and MTJP 2. Thus, the reliability of the unit memory cell 10 can be improved.

Fig. 4 is a plan view illustrating a unit memory cell of a magnetic storage device according to some embodiments of the inventive concept. For example, fig. 4 is a plan view illustrating an embodiment of the unit memory cell described with reference to fig. 2 and 3. Fig. 5 is a sectional view taken along line I-I' of fig. 4.

Referring to fig. 4 and 5, a substrate 110 may be provided. The substrate 110 may include a first select transistor SE1 and a second select transistor SE 2. The first select transistor SE1 and the second select transistor SE2 may be controlled by one word line (not shown). In addition, a source line (not shown) may be further provided to be commonly connected to the source region of the first select transistor SE1 and the source region of the second select transistor SE 2.

The first interlayer insulating layer 120 may be provided on the substrate 110. For example, the first interlayer insulating layer 120 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The first and second contact plugs PLG1 and PLG2 and the second bit line BL2 may be provided on the substrate 110. The first contact plug PLG1 may pass through the first interlayer insulating layer 120 to be connected to the drain region of the first select transistor SE 1. The second contact plug PLG2 may pass through the first interlayer insulating layer 120 to be connected to the drain region of the second select transistor SE 2. The second bit line BL2 may be disposed in the first interlayer insulating layer 120 and may extend in the first direction D1. The first and second contact plugs PLG1 and PLG2 and the second bit line BL2 may be disposed at substantially the same level (lelsel). As used in this specification, the term "horizontal plane" means a height from the top surface of the substrate 110. The first and second contact plugs PLG1 and PLG2 and the second bit line BL2 may include a conductive material.

A second interlayer insulating layer 122 may be provided on the first interlayer insulating layer 120. For example, the second interlayer insulating layer 122 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

A first bottom electrode BE1 and a second bottom electrode BE2 may BE provided as well as a landing pad LPAD. The first bottom electrode BE1 may pass through the second interlayer insulating layer 122 to BE electrically connected to the first contact plug PLG1, and the second bottom electrode BE2 may pass through the second interlayer insulating layer 122 to BE electrically connected to the second bit line BL 2. The landing pad LPAD may pass through the second interlayer insulating layer 122 to be electrically connected to the second contact plug PLG 2. The top surfaces of the first and second bottom electrodes BE1 and BE2 and the top surface of the landing pad LPAD may BE disposed at substantially the same level. Each of the first and second bottom electrodes BE1 and BE2 and the landing pad LPAD may comprise a conductive material. For example, each of the first and second bottom electrodes BE1 and BE2 and the landing pad LPAD may comprise a metal, such as copper, aluminum, tungsten, or titanium.

The first optional bottom electrode pattern OBEP1, the first magnetic tunnel junction pattern MTJP1, the first optional top electrode pattern otecp 1, and the first top electrode pattern TEP1 may BE sequentially stacked on the first bottom electrode BE 1. The second optional bottom electrode pattern OBEP2, the second magnetic tunnel junction pattern MTJP2, the second optional top electrode pattern otecp 2, and the second top electrode pattern TEP2 may BE sequentially stacked on the second bottom electrode BE 2. Accordingly, the bottom surface of the first magnetic tunnel junction pattern MTJP1 may BE electrically connected to the first selection transistor SE1 through the first bottom electrode BE1 and the first contact plug PLG1, and the bottom surface of the second magnetic tunnel junction pattern MTJP2 may BE electrically connected to the second bit line BL2 through the second bottom electrode BE 2.

The first and second alternative bottom electrode patterns OBEP1, OBEP2 and the first and second alternative top electrode patterns otecp 1, otecp 2 may include, for example, a conductive metal nitride, such as titanium nitride and/or tantalum nitride. The first and second top electrode patterns TEP1 and TEP2 may include, for example, at least one of tungsten, tantalum, aluminum, copper, gold, silver, titanium, and a conductive metal nitride including at least one of them.

The first magnetic tunnel junction pattern MTJP1 may include a first free pattern FP1, a first pinned pattern PP1, and a first tunnel barrier pattern TBP1 disposed between the first free pattern FP1 and the first pinned pattern PP 1. Likewise, the second magnetic tunnel junction pattern MTJP2 may include a second free pattern FP2, a second pinned pattern PP2, and a second tunnel barrier pattern TBP2 disposed between the second free pattern FP2 and the second pinned pattern PP 2. The stacking order of the first free pattern FP1, the first pinned pattern PP1, and the first tunnel barrier pattern TBP1 may be the same as the stacking order of the second free pattern FP2, the second pinned pattern PP2, and the second tunnel barrier pattern TBP 2.

In some embodiments, as shown in fig. 5, the first pinned pattern PP1, the first tunnel barrier pattern TBP1, and the first free pattern FP1 may be sequentially stacked, and the second pinned pattern PP2, the second tunnel barrier pattern TBP2, and the second free pattern FP2 may be sequentially stacked. However, the embodiments of the inventive concept are not limited thereto. Alternatively, unlike fig. 5, the first free pattern FP1, the first tunnel barrier pattern TBP1, and the first pinned pattern PP1 may be sequentially stacked, and the second free pattern FP2, the second tunnel barrier pattern TBP2, and the second pinned pattern PP2 may be sequentially stacked. Hereinafter, for the purpose of ease and convenience of explanation, the embodiment shown in fig. 5 will be described as an example. The first and second magnetic tunnel junction patterns MTJP1 and MTJP2 will be described in more detail later with reference to fig. 9A and/or 9B.

As described with reference to fig. 3, the first pinned pattern PP1 may BE electrically connected to the drain region of the first selection transistor SE1 through the first bottom electrode BE1 and the first contact plug PLG 1. The second pinned pattern PP2 may BE electrically connected to the second bit line BL2 through the second bottom electrode BE 2.

A distance d1 between the landing pad LPAD and the first magnetic tunnel junction pattern MTJP1 may be greater than a distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2 when viewed in a plan view. Further, a distance d2 between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP2 may be greater than a distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2 when viewed from a plan view.

In some embodiments, as shown in fig. 4, the first magnetic tunnel junction pattern MTJP1, the second magnetic tunnel junction pattern MTJP2, and the landing pad LPAD may be arranged on a line along a second direction D2 perpendicular to the first direction D1. However, the embodiments of the inventive concept are not limited thereto.

The first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be formed by patterning a magnetic tunnel junction layer, as described later with reference to fig. 8A to 8C. During the process of patterning the magnetic tunnel junction layer, etch byproducts may be generated from the magnetic tunnel junction layer and then may be deposited again on sidewalls of the first magnetic tunnel junction pattern MTJP1 and sidewalls of the second magnetic tunnel junction pattern MTJP 2. Therefore, the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be short-circuited. The possibility that the magnetic tunnel junction patterns MTJP1 and MTJP2 become short-circuited increases as the distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2 decreases. The distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially equal to or greater than a minimum interval distance capable of substantially preventing the magnetic tunnel junction patterns MTJP1 and MTJP2 from being short-circuited by etch byproducts generated during the patterning of the magnetic tunnel junction layer.

In addition, the landing pad LPAD may be exposed and partially etched during the patterning process of forming the magnetic tunnel junction patterns MTJP1 and MTJP 2. The etch by-products generated by the etching of the landing pad LPAD may be re-deposited on the sidewalls of the magnetic tunnel junction patterns MTJP1 and MTJP2, thereby causing a short circuit of the magnetic tunnel junction patterns MTJP1 and MTJP 2. The probability that the magnetic tunnel junction patterns MTJP1 and MTJP2 become short-circuited due to the etching of the landing pad LPAD may increase as the distance between the magnetic tunnel junction patterns MTJP1 and MTJP2 and the landing pad LPAD decreases.

According to an embodiment of the inventive concept, a distance d1 between the landing pad LPAD and the first magnetic tunnel junction pattern MTJP1 and a distance d2 between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP2 may be greater than a distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2 when viewed in a plan view. Accordingly, even if the landing pad LPAD is exposed during the process of forming the first and second magnetic tunnel junction patterns MTJP1 and MTJP2, it is possible to reduce or minimize the possibility that the etch by-products generated by the etching of the landing pad LPAD will be redeposited on the sidewalls of the magnetic tunnel junction patterns MTJP1 and MTJP 2. Thus, according to embodiments of the inventive concept, the magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially prevented or suppressed from being shorted by the etch by-products of the landing pad LPAD, and thus the reliability of the magnetic memory device may be improved.

The third interlayer insulating layer 124 may be provided on the second interlayer insulating layer 122 to cover the first and second magnetic tunnel junction patterns MTJP1 and MTJP 2. The third interlayer insulating layer 124 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The interconnect contact INC may pass through the third interlayer insulating layer 124 to be electrically connected to the landing pad LPAD. The interconnect contact INC may comprise a conductive material. The interconnect contact INC may comprise, for example, a metal such as copper, aluminum, tungsten or titanium.

The first bit line BL1 and the interconnection pattern INP may be provided on the third interlayer insulating layer 124. The first bit line BL1 may be electrically connected to the first top electrode pattern TEP1 and may extend in the first direction D1. The interconnection pattern INP may electrically connect the interconnection contact INC to the second top electrode pattern TEP 2. The interconnect pattern INP and the interconnect contact INC may constitute an interconnect structure INST. Accordingly, as described with reference to fig. 3, the top surface of the first magnetic tunnel junction pattern MTJP1 (i.e., the first free pattern FP1) may be electrically connected to the first bit line BL1 through the first top electrode pattern TEP 1. Further, the top surface (i.e., the second free pattern FP2) of the second magnetic tunnel junction pattern MTJP2 may be electrically connected to the drain region of the second select transistor SE2 through the second top electrode pattern TEP2, the interconnect structure INST, the landing pad LPAD, and the second contact plug PLG 2. Each of the first bit line BL1 and the interconnection pattern INP may include a conductive material. For example, each of the first bit line BL1 and the interconnection pattern INP may include a metal such as copper, aluminum, tungsten, or titanium.

Fig. 6 is a plan view illustrating a unit memory cell of a magnetic storage device according to some embodiments of the inventive concept. For example, fig. 6 is a plan view illustrating an embodiment of the unit memory cell described with reference to fig. 2 and 3. In the embodiment of fig. 6, substantially the same elements as those described with reference to fig. 4 and 5 are denoted by the same reference numerals or the same reference indicators, and the description thereof will be omitted or briefly mentioned for the purpose of ease and convenience of explanation.

Other features of the unit memory cell 10 shown in fig. 6 may be substantially similar to the corresponding features of the unit memory cell 10 described with reference to fig. 4 and 5, except for the planar arrangement of the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 and the landing pad LPAD. Therefore, the planar arrangement of the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 and the landing pad LPAD will be mainly described below.

Referring to fig. 6, when viewed from a plan view, a distance d1 between the landing pad LPAD and the first magnetic tunnel junction pattern MTJP1 may be greater than a distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP 2. Further, a distance d2 between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP2 may be greater than a distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2 when viewed from a plan view.

The first magnetic tunnel junction pattern MTJP1, the second magnetic tunnel junction pattern MTJP2, and the landing pad LPAD may not be arranged in one row. For example, as shown in fig. 6, the first magnetic tunnel junction pattern MTJP1 and the landing pad LPAD may be arranged in the second direction D2 to constitute one row, and the second magnetic tunnel junction pattern MTJP2 may be offset from the row in the first direction D1, so that the first magnetic tunnel junction pattern MTJP1, the second magnetic tunnel junction pattern MTJP2, and the landing pad LPAD of a single memory cell form a triangular shape.

The first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be formed by patterning a magnetic tunnel junction layer (not shown). During the patterning process of the magnetic tunnel junction layer, an etch byproduct generated from the magnetic tunnel junction layer may be re-deposited on sidewalls of the first and second magnetic tunnel junction patterns MTJP1 and MTJP2, which may cause the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 to become short-circuited. The possibility that the magnetic tunnel junction patterns MTJP1 and MTJP2 are short-circuited may increase as the distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2 decreases. The distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially equal to or greater than a minimum spacing distance capable of substantially preventing the magnetic tunnel junction patterns MTJP1 and MTJP2 from being short-circuited by the etch by-products generated from the magnetic tunnel junction layer.

According to an embodiment of the inventive concept, a distance d1 between the landing pad LPAD and the first magnetic tunnel junction pattern MTJP1 and a distance d2 between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP2 may be greater than a distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2 when viewed in a plan view. Accordingly, even if the landing pad LPAD is exposed during the patterning process of forming the first and second magnetic tunnel junction patterns MTJP1 and MTJP2, it is possible to reduce or minimize the possibility that the etch by-products generated from the landing pad LPAD will be redeposited on the sidewalls of the magnetic tunnel junction patterns MTJP1 and MTJP 2. In other words, according to embodiments of the inventive concept, the magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially prevented or suppressed from being short-circuited by the etch by-products generated by the etching of the landing pad LPAD, and thus the reliability of the magnetic memory device may be improved.

Fig. 7A to 7E are plan views illustrating memory cell arrays of magnetic storage devices according to some embodiments of the inventive concepts. For example, fig. 7A to 7E may be plan views illustrating embodiments of the memory cell array described with reference to fig. 2.

Referring to fig. 7A, a memory cell array according to some embodiments of the inventive concept may include a plurality of unit memory cells 10 arranged two-dimensionally. Each unit memory cell 10 may be substantially similar to the unit memory cells described with reference to fig. 4 and 5. Therefore, a detailed description of each unit memory cell 10 will be omitted for the purpose of easy and convenient explanation. Such a planar arrangement of the unit memory cell 10 (or the magnetic tunnel junction pattern and the landing pad included therein) will be mainly described below.

Referring to fig. 4, 5, and 7A, the unit memory cells 10 arranged two-dimensionally may be divided into a plurality of memory columns 15. Each memory column 15 may include a plurality of unit memory cells 10 arranged along the first direction D1, and a plurality of memory columns 15 may be arranged in the second direction D2.

Each memory column 15 may include a first sub-column SC1, a second sub-column SC2, and a third sub-column SC3, the first sub-column SC1 including a first magnetic tunnel junction pattern MTJP1 arranged in the first direction D1, the second sub-column SC2 including a second magnetic tunnel junction pattern MTJP2 arranged in the first direction D1, and the third sub-column SC3 including a landing pad LPAD arranged in the first direction D1. In each memory rank 15, the second sub-rank SC2 may be disposed between the first sub-rank SC1 and the third sub-rank SC 3.

A distance D4 between the first sub-column SC1 and the third sub-column SC3 in the second direction D2 may be greater than a distance D6 between the first sub-column SC1 and the second sub-column SC2 in the second direction D2, and a distance D5 between the second sub-column SC2 and the third sub-column SC3 in the second direction D2 may be greater than a distance D6 between the first sub-column SC1 and the second sub-column SC2 in the second direction D2.

The first magnetic tunnel junction patterns MTJP1 included in the first sub-column SC1 may be spaced apart from each other in the first direction D1 and may be arranged in the first direction D1. Likewise, the second magnetic tunnel junction patterns MTJP2 included in the second sub-column SC2 may be spaced apart from each other in the first direction D1 and may be arranged in the first direction D1. In some embodiments, a distance D7 between the first magnetic tunnel junction patterns MTJP1 in the first direction D1 and a distance D8 between the second magnetic tunnel junction patterns MTJP2 in the first direction D1 may be smaller than a distance D2 between the second magnetic tunnel junction patterns MTJP2 and the landing pad LPAD in the second sub-column SC2 (fig. 4).

According to some embodiments, a distance D7 between the first magnetic tunnel junction patterns MTJP1 in the first direction D1 may be substantially equal to a distance D8 between the second magnetic tunnel junction patterns MTJP2 in the first direction D1. Further, the distances d7 and d8 may be substantially equal to the distance d3 (fig. 4) between the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 (d3 ═ d7 ═ d 8). In this case, the magnetic tunnel junction patterns MTJP1 and MTJP2 included in one memory column 15 may be arranged at substantially equal distances in the first direction D1 and the second direction D2. As described with reference to fig. 4, the distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially equal to or greater than a minimum spacing distance capable of substantially preventing the magnetic tunnel junction patterns MTJP1 and MTJP2 from being short-circuited by the etch by-products generated from the magnetic tunnel junction layer. Accordingly, a distance between the magnetic tunnel junction patterns MTJP1 and MTJP2 included in one memory column 15 may be substantially equal to or greater than a minimum spacing distance capable of substantially preventing the magnetic tunnel junction patterns MTJP1 and MTJP2 from being short-circuited by the etch by-products generated from the magnetic tunnel junction layer.

According to the embodiment shown in fig. 7A, the first to third sub-ranks SC1, SC2, and SC3 may be arranged in the same order in each memory rank 15. Specifically, the first sub-rank SC1, the second sub-rank SC2, and the third sub-rank SC3 may be arranged in the second direction D2 in a specified order in each memory rank 15. Thus, the third sub-column SC3 of one memory column 15 of the two adjacent memory columns 15 may be adjacent to the first sub-column SC1 of the other memory column 15 of the two adjacent memory columns 15 with the boundary of the two adjacent memory columns 15 interposed therebetween. A distance D9 in the second direction D2 between the third sub-column SC3 and the first sub-column SC1 that are adjacent to each other with the boundary interposed therebetween may be greater than a distance D6 in the second direction D2 between the first sub-column SC1 and the second sub-column SC2 included in one memory column 15. For example, the distance D9 in the second direction D2 between the third sub-column SC3 and the first sub-column SC1 that are adjacent to each other with the boundary interposed therebetween may be substantially equal to the distance D5 in the second direction D2 between the second sub-column SC2 and the third sub-column SC3 included in one memory column 15. Likewise, the minimum distance d10 between the landing pad LPAD and the first magnetic tunnel junction pattern MTJP1 respectively included in the third sub-column SC3 and the first sub-column SC1 adjacent to each other with the boundary interposed therebetween may be greater than the distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP 2. For example, the minimum distance d10 may be substantially equal to the distance d2 between the second magnetic tunnel junction pattern MTJP2 and the landing pad LPAD.

According to the embodiments illustrated in fig. 4, 5, and 7A, when viewed from a plan view, a distance d10 or d2 between the landing pad LPAD and the magnetic tunnel junction pattern MTJP1 or MTJP2 adjacent to each other may be greater than a distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP 2. Accordingly, even if the landing pad LPAD is exposed during the patterning process for forming the magnetic tunnel junction patterns MTJP1 and MTJP2, it is possible to reduce or minimize the possibility that the etch by-products generated from the landing pad LPAD will be redeposited on the sidewalls of the magnetic tunnel junction patterns MTJP1 and MTJP 2. In other words, according to embodiments of the inventive concept, the magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially prevented or suppressed from being shorted by the etch by-products of the landing pad LPAD, and thus the reliability of the magnetic memory device may be improved.

Referring to fig. 5, a first bit line BL1 extending in a first direction D1 may be provided. Each of the first bit lines BL1 may be commonly connected to the first magnetic tunnel junction patterns MTJP1 included in each of the memory columns 15. More specifically, each of the first bit lines BL1 may be provided on the first magnetic tunnel junction pattern MTJP1 included in the corresponding first sub-column SC1 to be commonly connected to the first magnetic tunnel junction pattern MTJP1 included in the corresponding first sub-column SC 1. In addition, a second bit line BL2 extending in the first direction D1 may be provided. Each of the second bit lines BL2 may be commonly connected to the second magnetic tunnel junction patterns MTJP2 included in each of the memory columns 15. More specifically, each of the second bit lines BL2 may be provided under the second magnetic tunnel junction pattern MTJP2 included in the corresponding second sub-column SC2 to be commonly connected to the second magnetic tunnel junction pattern MTJP2 included in the corresponding second sub-column SC 2. As shown in fig. 5, the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be disposed at the same level. Therefore, the first bit line BL1 may be disposed at a higher level than the second bit line BL 2.

Referring to fig. 7B, a memory cell array according to some embodiments of the inventive concept may include a plurality of unit memory cells 10 arranged in a two-dimensional layout. Each unit memory cell 10 may be substantially similar to the unit memory cells described with reference to fig. 4 and 5. Therefore, a detailed description of each unit memory cell 10 will be omitted for the purpose of easy and convenient explanation. The planar arrangement of the unit memory cell 10 (or the magnetic tunnel junction pattern and landing pad included therein) will be mainly described below.

Referring to fig. 4, 5, and 7B, the unit memory cells 10 arranged two-dimensionally may be divided into a plurality of memory columns 15. Each memory column 15 may include a plurality of unit memory cells 10 arranged along the first direction D1, and the plurality of memory columns 15 may be arranged in a second direction D2 perpendicular to the first direction D1.

Each memory rank 15 may be similar to the memory ranks described with reference to fig. 4, 5, and 7A. Each memory column 15 may include a first sub-column SC1, a second sub-column SC2, and a third sub-column SC3, the first sub-column SC1 including a first magnetic tunnel junction pattern MTJP1 arranged in the first direction D1, the second sub-column SC2 including a second magnetic tunnel junction pattern MTJP2 arranged in the first direction D1, and the third sub-column SC3 including a landing pad LPAD arranged in the first direction D1. For the purpose of ease and convenience of explanation, a detailed description of each of the first to third sub-columns SC1, SC2, and SC3 will be omitted.

According to the embodiment shown in fig. 7B, the first to third sub-ranks SC1 to SC3 of one memory rank 15 of two adjacent memory ranks 15 and the first to third sub-ranks SC1 to SC3 of the other memory rank 15 of the two adjacent memory ranks 15 may be symmetrical with respect to a boundary between the two adjacent memory ranks 15. Specifically, the first, second, and third sub-ranks SC1, SC2, and SC3 of one memory rank 15 of the two adjacent memory ranks 15 may be arranged in the second direction D2 in a designated order, and the first, second, and third sub-ranks SC1, SC2, and SC3 of another memory rank 15 of the two adjacent memory ranks 15 may be arranged in the second direction D2 in an opposite order. In other words, the memory columns 15 may be arranged mirror-symmetrically along the second direction D2.

A first boundary among the boundaries between the memory columns 15 may be adjacent to the first subcolumns SC1 respectively included in a pair of memory columns 15 adjacent to each other with the first boundary interposed therebetween. In other words, the first subcolumns SC1 of the pair of memory columns 15 may be adjacent to each other with the first margin interposed therebetween. A distance D11 in the second direction D2 between the first sub-columns SC1 adjacent to each other with the first boundary interposed therebetween may be smaller than a distance D5 in the second direction D2 between the second sub-column SC2 and the third sub-column SC3 included in one memory column 15. For example, the distance D11 between the first sub-ranks SC1 in the second direction D2 may be substantially equal to the distance D6 between the first sub-rank SC1 and the second sub-rank SC2 included in one memory rank 15 in the second direction D2. Likewise, the minimum distance d12 between the first magnetic tunnel junction patterns MTJP1 respectively included in the first sub-columns SC1 adjacent to each other with the first boundary interposed therebetween may be smaller than the distance d2 (fig. 4) between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP 2. For example, the minimum distance d12 may be substantially equal to the distance d3 (fig. 4) between the first and second magnetic tunnel junction patterns MTJP1 and MTJP 2.

A second boundary of the boundaries between the memory columns 15 may be adjacent to the third sub-columns SC3 respectively included in another pair of memory columns 15 adjacent to each other with the second boundary interposed therebetween. In other words, the third subcolumns SC3 of the other pair of memory columns 15 may be adjacent to each other with the second boundary interposed therebetween. A distance D13 in the second direction D2 between the third sub-columns SC3 adjacent to each other with the second boundary interposed therebetween may be smaller than a distance D5 in the second direction D2 between the second sub-column SC2 and the third sub-column SC3 included in one memory column 15. Further, the distance D13 between the adjacent third sub-ranks SC3 in the second direction D2 may also be smaller than the distance D6 between the first sub-rank SC1 and the second sub-rank SC2 included in one memory rank 15 in the second direction D2. Likewise, the minimum distance d14 between the landing pads LPAD respectively included in the third sub-column SC3 adjacent to each other with the second boundary interposed therebetween may be smaller than the distance d2 between the landing pads LPAD and the second magnetic tunnel junction pattern MTJP 2. In addition, the minimum distance d14 may also be smaller than the distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP 2.

According to the embodiments illustrated in fig. 4, 5, and 7B, a distance d2 between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP2 adjacent to each other may be greater than a distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2 when viewed from a plan view. Accordingly, even if the landing pad LPAD is exposed during the patterning process for forming the magnetic tunnel junction patterns MTJP1 and MTJP2, it is possible to reduce or minimize the possibility that the etch by-products generated from the landing pad LPAD will be redeposited on the sidewalls of the magnetic tunnel junction patterns MTJP1 and MTJP 2. In other words, according to embodiments of the inventive concept, the magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially prevented or suppressed from being shorted by the etch by-products of the landing pad LPAD, and thus the reliability of the magnetic memory device may be improved.

A first bit line BL1 extending in the first direction D1 may be provided. Each of the first bit lines BL1 may be commonly connected to the first magnetic tunnel junction patterns MTJP1 included in each of the memory columns 15. In addition, a second bit line BL2 extending in the first direction D1 may be provided. Each of the second bit lines BL2 may be commonly connected to the second magnetic tunnel junction patterns MTJP2 included in each of the memory columns 15. The first bit line BL1 and the second bit line BL2 may be substantially similar to those described with reference to fig. 4, 5, and 7A.

Referring to fig. 7C, a memory cell array according to some embodiments of the inventive concept may include a plurality of unit memory cells 10 arranged two-dimensionally. Each unit memory cell 10 may be substantially similar to the unit memory cell described with reference to fig. 6. Therefore, a detailed description of each unit memory cell 10 will be omitted for the purpose of easy and convenient explanation. The planar arrangement of the unit memory cell 10 (or the magnetic tunnel junction pattern and landing pad included therein) will be mainly described below.

Referring to fig. 6 and 7C, the unit memory cells 10 arranged two-dimensionally may be divided into a plurality of memory columns 15. Each memory column 15 may include a plurality of unit memory cells 10 arranged along the first direction D1, and the plurality of memory columns 15 may be arranged in a second direction D2 perpendicular to the first direction D1.

Each memory column 15 may include a first sub-column SC1, a second sub-column SC2, and a third sub-column SC3, the first sub-column SC1 including a first magnetic tunnel junction pattern MTJP1 arranged in the first direction D1, the second sub-column SC2 including a second magnetic tunnel junction pattern MTJP2 arranged in the first direction D1, and the third sub-column SC3 including a landing pad LPAD arranged in the first direction D1.

When viewed in a plan view, a distance D4 between the first sub-column SC1 and the third sub-column SC3 included in one memory column 15 in the second direction D2 may be greater than a distance D6 between the first sub-column SC1 and the second sub-column SC2 included in one memory column 15 in the second direction D2. Further, when viewed from a plan view, a distance D5 between the second sub-column SC2 and the third sub-column SC3 included in one memory column 15 in the second direction D2 may be greater than a distance D6 between the first sub-column SC1 and the second sub-column SC2 included in one memory column 15 in the second direction D2.

The first magnetic tunnel junction patterns MTJP1 included in the first sub-column SC1 may be spaced apart from each other in the first direction D1 and may be arranged in the first direction D1. Likewise, the second magnetic tunnel junction patterns MTJP2 included in the second sub-column SC2 may be spaced apart from each other in the first direction D1 and may be arranged in the first direction D1. A distance D7 between the first magnetic tunnel junction patterns MTJP1 in the first direction D1 and a distance D8 between the second magnetic tunnel junction patterns MTJP2 in the first direction D1 may be less than a distance D2 between the landing pad LPAD and the second magnetic tunnel junction patterns MTJP 2. In each memory rank 15, the second sub-rank SC2 may be disposed between the first sub-rank SC1 and the third sub-rank SC 3.

According to the embodiment shown in fig. 7C, the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 respectively included in the first and second sub-columns SC1 and SC2 of one memory column 15 may be arranged in a zigzag form along the first direction D1 when viewed from a plan view. Likewise, the second magnetic tunnel junction patterns MTJP2 and the landing pads LPAD respectively included in the second sub-column SC2 and the third sub-column SC3 of one memory column 15 may be arranged in a zigzag form along the first direction D1 when viewed from a plan view. Therefore, when viewed from a plan view, a distance D5 between the second sub-column SC2 and the third sub-column SC3 in the second direction D2 may be smaller than a distance D2 between the second magnetic tunnel junction pattern MTJP2 and the landing pad LPAD (fig. 4). Further, when viewed from a plan view, a distance D6 between the first sub-column SC1 and the second sub-column SC2 in the second direction D2 may be smaller than a distance D3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2 (fig. 4).

According to some embodiments, a distance D7 between the first magnetic tunnel junction patterns MTJP1 in the first direction D1 may be substantially equal to a distance D8 between the second magnetic tunnel junction patterns MTJP2 in the first direction D1. Further, the distances d7 and d8 may be substantially equal to the distance d3 (fig. 4) between the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 (i.e., d3 ═ d7 ═ d 8). In other words, the magnetic tunnel junction patterns MTJP1 and MTJP2 included in one memory column 15 may be spaced apart from each other by substantially equal distances. As described above, the distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially equal to or greater than a minimum spacing distance capable of substantially preventing the magnetic tunnel junction patterns from being short-circuited by the etch by-products generated from the magnetic tunnel junction layer. Accordingly, the distances d3, d7, and d8 between the magnetic tunnel junction patterns MTJP1 and MTJP2 included in one memory column 15 may be substantially equal to or greater than a minimum spacing distance capable of substantially preventing the magnetic tunnel junction patterns from being short-circuited by the etch by-products generated from the magnetic tunnel junction layer.

According to the embodiment shown in fig. 6 and 7C, the first to third sub-ranks SC1, SC2, and SC3 may be arranged in the same order in each memory rank 15. Specifically, the first sub-rank SC1, the second sub-rank SC2, and the third sub-rank SC3 may be arranged in the second direction D2 in a specified order in each memory rank 15. Thus, the third sub-column SC3 of one memory column 15 of the two adjacent memory columns 15 may be adjacent to the first sub-column SC1 of the other memory column 15 of the two adjacent memory columns 15 with a boundary between the two adjacent memory columns 15 interposed therebetween. A distance D9 in the second direction D2 between the third sub-column SC3 and the first sub-column SC1 that are adjacent to each other with the boundary interposed therebetween may be greater than a distance D6 in the second direction D2 between the first sub-column SC1 and the second sub-column SC2 included in one memory column 15. A minimum distance d10 between the landing pad LPAD and the first magnetic tunnel junction pattern MTJP1 respectively included in the third sub-column SC3 and the first sub-column SC1 adjacent to each other with the boundary interposed therebetween may be greater than a distance d3 (fig. 4) between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP 2. For example, the minimum distance d10 may be substantially equal to the distance d2 (fig. 4) between the second magnetic tunnel junction pattern MTJP2 and the landing pad LPAD.

According to the embodiments shown in fig. 6 and 7C, when viewed from a plan view, a distance d10 or d2 between the landing pad LPAD and the magnetic tunnel junction pattern MTJP1 or MTJP2 adjacent to each other may be greater than a distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2 (fig. 4). Accordingly, even if the landing pad LPAD is exposed during the patterning process for forming the magnetic tunnel junction patterns MTJP1 and MTJP2, it is possible to reduce or minimize the possibility that the etch by-products generated from the landing pad LPAD will be redeposited on the sidewalls of the magnetic tunnel junction patterns MTJP1 and MTJP 2. In other words, according to embodiments of the inventive concept, the magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially prevented or suppressed from being shorted by the etch by-products of the landing pad LPAD, and thus the reliability of the magnetic memory device may be improved.

A first bit line BL1 extending in the first direction D1 may be provided. Each of the first bit lines BL1 may be commonly connected to the first magnetic tunnel junction patterns MTJP1 included in each of the memory columns 15. More specifically, each of the first bit lines BL1 may be provided on the first magnetic tunnel junction pattern MTJP1 included in the corresponding first sub-column SC1 so as to be commonly connected to the first magnetic tunnel junction pattern MTJP1 included in the corresponding first sub-column SC 1. In addition, a second bit line BL2 extending in the first direction D1 may be provided. Each of the second bit lines BL2 may be commonly connected to the second magnetic tunnel junction patterns MTJP2 included in the corresponding memory column 15. More specifically, each of the second bit lines BL2 may be provided under the second magnetic tunnel junction pattern MTJP2 included in the corresponding second sub-column SC2 to be commonly connected to the second magnetic tunnel junction pattern MTJP2 included in the corresponding second sub-column SC 2. As shown in fig. 5, the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be disposed at the same level. Therefore, the first bit line BL1 may be disposed at a higher level than the second bit line BL 2.

Referring to fig. 7D, a memory cell array according to some embodiments of the inventive concept may include a plurality of unit memory cells 10 arranged two-dimensionally. Each unit memory cell 10 may be substantially similar to the unit memory cell described with reference to fig. 6. Therefore, a detailed description of each unit memory cell 10 will be omitted for the purpose of easy and convenient explanation. The planar arrangement of the unit memory cell 10 (or the magnetic tunnel junction pattern and landing pad included therein) will be mainly described below.

Referring to fig. 6 and 7D, the unit memory cells 10 arranged two-dimensionally may be divided into a plurality of memory columns 15. Each memory column 15 may include a plurality of unit memory cells 10 arranged along the first direction D1, and the plurality of memory columns 15 may be arranged in a second direction D2 perpendicular to the first direction D1.

Each memory rank 15 may be similar to the memory ranks described with reference to fig. 6 and 7C. In some embodiments, each memory rank 15 may include a first sub-rank SC1, a second sub-rank SC2, and a third sub-rank SC3, the first sub-rank SC1 including a first magnetic tunnel junction pattern MTJP1 arranged in a first direction D1, the second sub-rank SC2 including a second magnetic tunnel junction pattern MTJP2 arranged in a first direction D1, and the third sub-rank SC3 including a landing pad LPAD arranged in the first direction D1. For the purpose of ease and convenience of explanation, a detailed description of each of the first to third sub-columns SC1, SC2, and SC3 will be omitted.

According to the embodiment shown in fig. 7D, the first to third sub-ranks SC1 to SC3 of one memory rank 15 of two adjacent memory ranks 15 and the first to third sub-ranks SC1 to SC3 of the other memory rank 15 of the two adjacent memory ranks 15 may be symmetrical with respect to a boundary between the two adjacent memory ranks 15. Specifically, the first, second, and third sub-ranks SC1, SC2, and SC3 of one memory rank 15 of the two adjacent memory ranks 15 may be arranged in the second direction D2 in a designated order, and the first, second, and third sub-ranks SC1, SC2, and SC3 of another memory rank 15 of the two adjacent memory ranks 15 may be arranged in the second direction D2 in an opposite order. In other words, the memory columns 15 may be arranged mirror-symmetrically along the second direction D2.

A first boundary of the boundaries between the memory ranks 15 may be adjacent to the first sub-ranks SC1 respectively included in the pair of memory ranks 15 adjacent to each other with the first boundary interposed therebetween. In other words, the first subcolumns SC1 of the pair of memory columns 15 may be adjacent to each other with the first margin interposed therebetween. A distance D11 in the second direction D2 between the first sub columns SC1 adjacent to each other with the first boundary interposed therebetween may be smaller than a distance D2 between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP 2. For example, the distance d11 may be substantially equal to the distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP 2. Likewise, the minimum distance d12 between the first magnetic tunnel junction patterns MTJP1 respectively included in the first sub-columns SC1 adjacent to each other with the first boundary interposed therebetween may be smaller than the distance d2 between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP 2. For example, the minimum distance d12 may be substantially equal to the distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP 2.

A second boundary of the boundaries between the memory ranks 15 may be adjacent to the third subcolumns SC3 respectively included in another pair of memory ranks 15 that are adjacent to each other with the second boundary interposed therebetween. In other words, the third subcolumns SC3 of another pair of memory columns 15 may be adjacent to each other with the second boundary interposed therebetween. A distance D13 in the second direction D2 between the third sub-columns SC3 adjacent to each other with the second boundary interposed therebetween may be smaller than a distance D5 in the second direction D2 between the second sub-column SC2 and the third sub-column SC3 included in one memory column 15. Further, the distance D13 between the adjacent third sub-ranks SC3 in the second direction D2 may also be smaller than the distance D6 between the first sub-rank SC1 and the second sub-rank SC2 included in one memory rank 15 in the second direction D2. Likewise, the minimum distance d14 between the landing pads LPAD respectively included in the third sub-column SC3 adjacent to each other with the second boundary interposed therebetween may be smaller than the distance d2 between the landing pads LPAD and the second magnetic tunnel junction pattern MTJP 2. In addition, the minimum distance d14 may also be smaller than the distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP 2.

According to the embodiments shown in fig. 6 and 7D, when viewed from a plan view, a distance D2 between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP2 adjacent to each other may be greater than a distance D3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP 2. Accordingly, even if the landing pad LPAD is exposed during the patterning process for forming the magnetic tunnel junction patterns MTJP1 and MTJP2, the possibility that the etch by-products generated from the landing pad LPAD will be redeposited on the sidewalls of the magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially reduced or minimized. In other words, according to embodiments of the inventive concept, the magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially prevented or suppressed from being shorted by the etch by-products of the landing pad LPAD, and thus the reliability of the magnetic memory device may be improved.

Each of the first bit lines BL1 extending in the first direction D1 may be commonly connected to the first magnetic tunnel junction patterns MTJP1 included in the corresponding memory column 15. Further, each of the second bit lines BL2 extending in the first direction D1 may be commonly connected to the second magnetic tunnel junction patterns MTJP2 included in the corresponding memory column 15. The first bit line BL1 and the second bit line BL2 may be substantially similar to those described with reference to fig. 7A.

Referring to fig. 7E, a memory cell array according to some embodiments of the inventive concept may include a plurality of unit memory cells 10 arranged two-dimensionally. Each unit memory cell 10 may be substantially similar to the unit memory cell described with reference to fig. 6. Therefore, a detailed description of each unit memory cell 10 will be omitted for the purpose of easy and convenient explanation. The planar arrangement of the unit memory cell 10 (or the magnetic tunnel junction pattern and landing pad included therein) will be mainly described below.

Referring to fig. 6 and 7E, the unit memory cells 10 arranged two-dimensionally may be divided into a plurality of memory columns 15. Each memory column 15 may include a plurality of unit memory cells 10 arranged along the first direction D1, and the plurality of memory columns 15 may be arranged in a second direction D2 perpendicular to the first direction D1.

Each memory rank 15 may be similar to the memory ranks described with reference to fig. 6 and 7D. Specifically, each memory rank 15 may include a first sub-rank SC1, a second sub-rank SC2, and a third sub-rank SC3, the first sub-rank SC1 including a first magnetic tunnel junction pattern MTJP1 arranged in the first direction D1, the second sub-rank SC2 including a second magnetic tunnel junction pattern MTJP2 arranged in the first direction D1, and the third sub-rank SC3 including a landing pad LPAD arranged in the first direction D1. For the purpose of ease and convenience of explanation, a detailed description of each of the first to third sub-columns SC1, SC2, and SC3 will be omitted.

According to the embodiment shown in fig. 7E, the first, second, and third sub-ranks SC1, SC2, and SC3 of one memory rank 15 of two memory ranks 15 adjacent to each other may be arranged in a specified order in the second direction D2, and the first, second, and third sub-ranks SC1, SC2, and SC3 of another memory rank 15 of the two adjacent memory ranks 15 may be arranged in an opposite order in the second direction D2.

A first boundary of the boundaries between the memory ranks 15 may be adjacent to the first sub-ranks SC1 respectively included in the pair of memory ranks 15 adjacent to each other with the first boundary interposed therebetween. In other words, the first subcolumns SC1 of the pair of memory columns 15 may be adjacent to each other with the first margin interposed therebetween. The first magnetic tunnel junction patterns MTJP1 included in the first sub-column SC1 adjacent to each other with the first boundary interposed therebetween may be arranged in a zigzag form along the first direction D1 when viewed from a plan view. A distance D11 in the second direction D2 between the first sub-columns SC1 adjacent to each other with the first boundary interposed therebetween may be smaller than a distance D5 in the second direction D2 between the second sub-column SC2 and the third sub-column SC3 included in one memory column 15. For example, the distance D11 may be substantially equal to the distance D6 in the second direction D2 between the first sub-rank SC1 and the second sub-rank SC2 included in one memory rank 15. A minimum distance d12 between the first magnetic tunnel junction patterns MTJP1 respectively included in the first sub-columns SC1 adjacent to each other with the first margin interposed therebetween may be smaller than a distance d2 between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP 2. For example, the minimum distance d12 may be substantially equal to the distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP 2.

A second boundary of the boundaries between the memory ranks 15 may be adjacent to the third subcolumns SC3 respectively included in another pair of memory ranks 15 that are adjacent to each other with the second boundary interposed therebetween. In other words, the third subcolumns SC3 of the other pair of memory columns 15 may be adjacent to each other with the second boundary interposed therebetween. A distance D13 in the second direction D2 between the third sub-columns SC3 adjacent to each other with the second boundary interposed therebetween may be smaller than a distance D5 in the second direction D2 between the second sub-column SC2 and the third sub-column SC3 included in one memory column 15. Further, the distance D13 between the adjacent third sub-ranks SC3 in the second direction D2 may also be smaller than the distance D6 between the first sub-rank SC1 and the second sub-rank SC2 included in one memory rank 15 in the second direction D2. Likewise, the minimum distance d14 between the landing pads LPAD respectively included in the third sub-column SC3 adjacent to each other with the second boundary interposed therebetween may be smaller than the distance d2 between the landing pads LPAD and the second magnetic tunnel junction pattern MTJP 2. In addition, the minimum distance d14 may also be smaller than the distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP 2.

According to the embodiments shown in fig. 6 and 7E, when viewed from a plan view, a distance d2 between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP2 adjacent to each other may be greater than a distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP 2. Accordingly, even if the landing pad LPAD is exposed during the patterning process for forming the magnetic tunnel junction patterns MTJP1 and MTJP2, the possibility that the etch by-products generated from the landing pad LPAD will be redeposited on the sidewalls of the magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially reduced or minimized. In other words, according to embodiments of the inventive concept, the magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially prevented or suppressed from being shorted by the etch by-products of the landing pad LPAD, and thus the reliability of the magnetic memory device may be improved.

Fig. 8A to 8C are sectional views corresponding to line I-I' of fig. 4 for illustrating a method of manufacturing a unit memory cell of a magnetic memory device according to some embodiments of the inventive concept. Hereinafter, the same elements as those described in the embodiments of fig. 4, 5 and 6 will be denoted by the same reference numerals or the same reference indicators, and the description thereof will be omitted or simply referred to for the purpose of easy and convenient explanation.

Referring to fig. 4 and 8A, a substrate 110 including a first select transistor SE1 and a second select transistor SE2 may be provided. The first interlayer insulating layer 120 may be formed on the substrate 110. For example, the first interlayer insulating layer 120 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The first interlayer insulating layer 120 may be formed by, for example, a Chemical Vapor Deposition (CVD) process or a Physical Vapor Deposition (PVD) process.

The first and second contact plugs PLG1 and PLG2 may be formed to pass through the first interlayer insulating layer 120. The first contact plug PLG1 may be connected to the first select transistor SE1, and the second contact plug PLG2 may be connected to the second select transistor SE 2. In addition, the second bit line BL2 may be formed in the first interlayer insulating layer 120.

The second interlayer insulating layer 122 may be formed on the first interlayer insulating layer 120. For example, the second interlayer insulating layer 122 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second interlayer insulating layer 122 may be formed by a CVD process or a PVD process.

The first and second bottom electrodes BE1 and BE2 and the landing pad LPAD may BE formed to pass through the second interlayer insulating layer 122. Forming the first and second bottom electrodes BE1 and BE2 and the landing pad LPAD may include: patterning the second interlayer insulating layer 122 to form a first via hole PH1, a second via hole PH2, and a third via hole PH3 exposing the first contact plug PLG1, the second bit line BL2, and the second contact plug PLG2, respectively; forming a conductive layer filling the first to third through holes PH1, PH2, and PH3 on the second interlayer insulating layer 122; and planarizing the conductive layer until a top surface of the second interlayer insulating layer 122 is exposed. Accordingly, the top surfaces of the first and second bottom electrodes BE1 and BE2 and the top surface of the landing pad LPAD may BE disposed at substantially the same level. The first bottom electrode BE1 may BE electrically connected to the first contact plug PLG1, the second bottom electrode BE2 may BE electrically connected to the second bit line BL2, and the landing pad LPAD may BE electrically connected to the second contact plug PLG 2.

Referring to fig. 4 and 8B, an optional bottom electrode layer OBEL, a magnetic tunnel junction layer MTJL, an optional top electrode layer otecl, and a top electrode layer TEL may be sequentially formed on the second interlayer insulating layer 122. Each of the layers OBEL, MTJL, otecl may be formed by, for example, a CVD process or a PVD process.

The optional bottom electrode layer OBEL and the optional top electrode layer otecl may comprise a conductive metal nitride, such as titanium nitride and/or tantalum nitride. In some embodiments, at least one of the optional bottom electrode layer OBEL and the optional top electrode layer otecl may be omitted. Hereinafter, for the purpose of ease and convenience of explanation, an embodiment in which the optional bottom electrode layer OBEL and the optional top electrode layer otecl are formed will be described as an example. However, the embodiments of the inventive concept are not limited thereto.

In some embodiments, the magnetic tunnel junction layer MTJL may include a pinned layer PL, a tunnel shield layer TBL, and a free layer FL, which are sequentially stacked. However, the embodiments of the inventive concept are not limited thereto. In some embodiments, the free layer, the tunnel barrier layer TBL, and the pinned layer may be sequentially stacked. The magnetic tunnel junction layer MTJL will be described in detail later with reference to fig. 9A and/or 9B.

The mask pattern MP may be formed on the top electrode layer TEL. The mask pattern MP may overlap the first and second bottom electrodes BE1 and BE2, respectively, when viewed in a plan view. The mask pattern MP may include, but is not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

Referring to fig. 4 and 8C, a first optional bottom electrode pattern OBEP1, a first magnetic tunnel junction pattern MTJP1, a first optional top electrode pattern otecp 1, and a first top electrode pattern TEP1 may BE sequentially formed on the first bottom electrode BE 1. A second optional bottom electrode pattern OBEP2, a second magnetic tunnel junction pattern MTJP2, a second optional top electrode pattern otecp 2, and a second top electrode pattern TEP2 may BE sequentially formed on the second bottom electrode BE 2. Forming the patterns OBEP1, OBEP2, MTJP1, MTJP2, otecp 1, otecp 2, TEP1, and TEP2 may include sequentially patterning the top electrode layer TEL, the optional top electrode layer otecl, the magnetic tunnel junction layer MTJL, and the optional bottom electrode layer OBEL using the mask pattern MP as an etch mask. In some embodiments, the patterning process may be performed using an Ion Beam Etching (IBE) process.

During the process of patterning the magnetic tunnel junction layer MTJL, the etch by-products generated from the magnetic tunnel junction layer MTJL may be again deposited on the sidewalls of the magnetic tunnel junction patterns MTJP1 and MTJP 2. Therefore, the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be short-circuited. The possibility of short circuits may increase as the distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 decreases. However, according to an embodiment of the inventive concept, the distance d3 between the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially equal to or greater than a minimum separation distance capable of substantially preventing the first and second magnetic tunnel junction patterns MTJP1 and MTJP2 from being shorted by the etch by-products generated from the magnetic tunnel junction layer MTJL.

In general, the landing pad LPAD may be exposed and partially etched during the patterning process for forming the magnetic tunnel junction patterns MTJP1 and MTJP 2. At this time, the etch by-products generated from the landing pad LPAD may be deposited again on the sidewalls of the magnetic tunnel junction patterns MTJP1 and MTJP2, thereby causing short circuits of the magnetic tunnel junction patterns MTJP1 and MTJP 2. The probability of occurrence of a short circuit due to etching of the landing pad LPAD may increase as the distance between the magnetic tunnel junction patterns MTJP1 and MTJP2 and the landing pad LPAD decreases.

However, according to an embodiment of the inventive concept, a distance d1 between the landing pad LPAD and the first magnetic tunnel junction pattern MTJP1 and a distance d2 between the landing pad LPAD and the second magnetic tunnel junction pattern MTJP2 may be greater than a distance d3 between the first magnetic tunnel junction pattern MTJP1 and the second magnetic tunnel junction pattern MTJP2 when viewed in a plan view. Accordingly, even if the landing pad LPAD is exposed during the patterning process for forming the magnetic tunnel junction patterns MTJP1 and MTJP2, it is possible to reduce or minimize the possibility that the etch by-products generated from the landing pad LPAD will be redeposited on the sidewalls of the magnetic tunnel junction patterns MTJP1 and MTJP 2. In other words, according to embodiments of the inventive concept, the magnetic tunnel junction patterns MTJP1 and MTJP2 may be substantially prevented or suppressed from being shorted by the etch by-products of the landing pad LPAD, and thus the reliability of the magnetic memory device may be improved.

Referring again to fig. 4 and 5, a third interlayer insulating layer 124 may be formed on the second interlayer insulating layer 122 to cover the first and second magnetic tunnel junction patterns MTJP1 and MTJP 2. The third interlayer insulating layer 124 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the third interlayer insulating layer 124 may be formed by a CVD process or a PVD process. In some embodiments, the third interlayer insulating layer 124 may be planarized until the top surfaces of the first and second top electrode patterns TEP1 and TEP2 are exposed.

The interconnection contact INC may be formed through the third interlayer insulating layer 124. The interconnect contacts INC may be connected to the landing pads LPAD. The first bit line BL1 and the interconnection pattern INP may be formed on the third interlayer insulating layer 124. The first bit line BL1 may be electrically connected to the first top electrode pattern TEP1, and the interconnection pattern INP may electrically connect the interconnection contact INC to the second top electrode pattern TEP 2. In some embodiments, the interconnect contact INC, the interconnect pattern INP, and the first bit line BL1 may be simultaneously formed using a damascene process.

Fig. 9A and 9B are conceptual diagrams illustrating magnetic tunnel junction patterns according to some embodiments of the inventive concept. The magnetic tunnel junction pattern MTJP may include a first magnetic pattern MP1, a tunnel barrier pattern TBP, and a second magnetic pattern MP 2. One of the first and second magnetic patterns MP1 and MP2 may correspond to a free pattern of a magnetic tunnel junction, and the other of the first and second magnetic patterns MP1 and MP2 may correspond to a pinned pattern of the magnetic tunnel junction. Hereinafter, for the purpose of ease and convenience of explanation, the first magnetic pattern MP1 will be described as a pinned pattern, and the second magnetic pattern MP2 will be described as a free pattern. In contrast, in some embodiments, the first magnetic pattern MP1 may be a free pattern, and the second magnetic pattern MP2 may be a pinned pattern. The resistance value of the magnetic tunnel junction pattern MTJP may be determined according to the magnetization directions of the free pattern and the pinned pattern. For example, the resistance value of the magnetic tunnel junction pattern MTJP when the magnetization directions of the free pattern and the pinned pattern are antiparallel to each other may be much larger than the resistance value of the magnetic tunnel junction pattern MTJP when the magnetization directions of the free pattern and the pinned pattern are parallel to each other. Thus, the resistance value of the magnetic tunnel junction pattern MTJP can be adjusted by changing the magnetization direction of the free pattern. This may be used as a data storage principle of the magnetic storage device according to some embodiments of the inventive concept.

Referring to fig. 9A, the magnetization directions of the first and second magnetic patterns MP1 and MP2 may be substantially parallel to the top surface of the tunnel barrier pattern TBP, and thus the first and second magnetic patterns MP1 and MP2 may beTo form a horizontally magnetized structure. In these embodiments, the first magnetic pattern MP1 may include a layer including an antiferromagnetic material and a layer including a ferromagnetic material. In certain embodiments, the layer comprising antiferromagnetic material may include PtMn, IrMn, MnO, MnS, MnTe, MnF₂、FeCl₂、FeO、CoCl₂、CoO、NiCl₂NiO and/or Cr. In certain embodiments, the layer comprising the antiferromagnetic material can include at least one noble metal. The noble metal may include ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or silver (Ag). The layer comprising ferromagnetic material may comprise CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO₂、MnOFe₂O₃、FeOFe₂O₃、NiOFe₂O₃、CuOFe₂O₃、MgOFe₂O₃EuO and Y₃Fe₅O₁₂At least one of (1).

The second magnetic pattern MP2 may include a material having a changeable magnetization direction. The second magnetic pattern MP2 may include a ferromagnetic material. For example, the second magnetic pattern MP2 may include FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO₂、MnOFe₂O₃、FeOFe₂O₃、NiOFe₂O₃、CuOFe₂O₃、MgOFe₂O₃EuO and Y₃Fe₅O₁₂At least one of (1).

The second magnetic pattern MP2 may include a plurality of layers. For example, the second magnetic pattern MP2 may include a plurality of ferromagnetic layers and a nonmagnetic material layer disposed between the ferromagnetic layers. In this case, the ferromagnetic layer and the nonmagnetic material layer may constitute a synthetic antiferromagnetic layer. The synthetic antiferromagnetic layer may reduce a critical current density of the magnetic memory device and may improve thermal stability of the magnetic memory device.

The tunnel barrier pattern TBP may include at least one of magnesium oxide (MgO), titanium oxide (TiO), aluminum oxide (AlO), magnesium zinc oxide (MgZnO), magnesium boron oxide (MgBO), titanium nitride (TiN), and Vanadium Nitride (VN). In some embodiments, the tunnel barrier pattern TBP may be a single layer formed of magnesium oxide (MgO). Alternatively, the tunnel barrier pattern TBP may include a plurality of layers. The tunnel barrier pattern TBP may be formed using a CVD process.

Referring to fig. 9B, the magnetization directions of the first and second magnetic patterns MP1 and MP2 may be substantially perpendicular to the top surface of the tunnel barrier pattern TBP, and thus the first and second magnetic patterns MP1 and MP2 may constitute a perpendicular magnetization structure. In these embodiments, each of the first and second magnetic patterns MP1 and MP2 may include a magnetic layer having L1₀At least one of a material of a crystal structure, a material having a hexagonal close-packed (HCP) crystal structure, and an amorphous rare earth transition metal (RE-TM) alloy. In some embodiments, each of the first and second magnetic patterns MP1 and MP2 may include a first magnetic pattern having L1₀Fe of crystal structure₅₀Pt₅₀Having L1₀Fe of crystal structure₅₀Pd₅₀Having L1₀Co of crystal structure₅₀Pt₅₀Having L1₀Co of crystal structure₅₀Pd₅₀And has L1₀Fe of crystal structure₅₀Ni₅₀At least one of (1). In some embodiments, each of the first and second magnetic patterns MP1 and MP2 may include a CoPt random alloy or Co₃A Pt ordered alloy having an HCP crystal structure and comprising a platinum content of 10 at.% to 45 at.%. In some embodiments, each of the first and second magnetic patterns MP1 and MP2 may include at least one amorphous RE-TM alloy including at least one selected from the group consisting of iron (Fe), cobalt (Co), and nickel (Ni) and at least one selected from the group consisting of terbium (Tb), dysprosium (Dy), and gadolinium (Gd) of rare earth metals.

In some embodiments, the first and second magnetic patterns MP1 and MP2 may include a material having an interface perpendicular magnetic anisotropy (i-PMA). The interfacial perpendicular magnetic anisotropy may mean that a magnetic layer having an intrinsic horizontal magnetization property has a perpendicular magnetization direction affected by an interface between the magnetic layer and another layer adjacent to the magnetic layer. Here, the intrinsic horizontal magnetization property may mean that the magnetic layer has a magnetization direction parallel to the widest surface of the magnetic layer when no external factor is present. For example, when a magnetic layer having an intrinsic horizontal magnetization property is formed on a substrate and an external factor is not present, the magnetization direction of the magnetic layer may be substantially parallel to the top surface of the substrate.

For example, each of the first and second magnetic patterns MP1 and MP2 may include at least one of cobalt (Co), iron (Fe), and nickel (Ni). In addition, each of the first and second magnetic patterns MP1 and MP2 may further include at least one selected from nonmagnetic materials including boron (B), zinc (Zn), aluminum (Al), titanium (Ti), ruthenium (Ru), tantalum (Ta), silicon (Si), silver (Ag), gold (Au), copper (Cu), carbon (C), and nitrogen (N). For example, each of the first and second magnetic patterns MP1 and MP2 may include CoFe or NiFe, and may further include boron (B). Further, in order to reduce the saturation magnetization of the first and second magnetic patterns MP1 and MP2, each of the first and second magnetic patterns MP1 and MP2 may further include at least one of titanium (Ti), aluminum (Al), silicon (Si), magnesium (Mg), and tantalum (Ta). Each of the first and second magnetic patterns MP1 and MP2 may be formed using a sputtering process or a CVD process.

The magnetic tunnel junction layer MTJL described with reference to fig. 8B may include substantially the same material as the magnetic tunnel junction pattern MTJP of fig. 9A or 9B.

According to some embodiments of the inventive concept, a distance between the landing pad and the magnetic tunnel junction pattern may be greater than a distance between the magnetic tunnel junction patterns. Accordingly, even if the landing pad is exposed during the patterning process for forming the magnetic tunnel junction pattern, the possibility that the magnetic tunnel junction pattern will be shorted by etch by-products generated from the landing pad can be reduced or minimized. In other words, according to some embodiments of the inventive concept, the magnetic tunnel junction pattern may be substantially prevented or suppressed from being shorted by the etch by-products of the landing pad, and thus the reliability of the magnetic storage device may be improved.

Although the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Accordingly, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.

This application claims priority to korean patent application nos. 10-2015-0144268 and 10-2015-015635, filed by the korean intellectual property office at 2015, 15 th and 2015, 11 th and 9 th, respectively, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. A magnetic storage device comprising:

substrate;

landing pads on the substrate;

a first magnetic tunnel junction pattern and a second magnetic tunnel junction pattern, on the substrate, the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern spaced apart from the landing pad;

an interconnect structure electrically connecting the top surface of the second magnetic tunnel junction pattern to the landing pad; and

a first bit line electrically connected to the top surface of the first magnetic tunnel junction pattern and spaced apart from the interconnect structure,

wherein the first magnetic tunnel junction pattern is spaced apart from the landing pad by a first distance,

wherein the second magnetic tunnel junction pattern is spaced apart from the landing pad by a second distance,

wherein the first magnetic tunnel junction pattern is spaced apart from the second magnetic tunnel junction pattern by a third distance,

wherein the first distance is greater than the third distance, and

wherein the second distance is greater than the third distance.

2. The magnetic storage device of claim 1, further comprising:

a first bottom electrode electrically connected to the bottom surface of the first magnetic tunnel junction pattern; and

a second bottom electrode electrically connected to the bottom surface of the second magnetic tunnel junction pattern,

wherein the top surface of the landing pad is disposed at the same level as the top surface of the first bottom electrode and the top surface of the second bottom electrode with respect to the top surface of the substrate.

3. The magnetic memory device of claim 1, further comprising a first selection element and a second selection element on the substrate,

wherein the first selection element is electrically connected to the bottom surface of the first magnetic tunnel junction pattern, and

wherein the second selection element is electrically connected to the top surface of the second magnetic tunnel junction pattern through the landing pad and the interconnect structure.

4. The magnetic storage device of claim 1, further comprising:

second line,

wherein the second bit line is electrically connected to the bottom surface of the second magnetic tunnel junction pattern.

5. The magnetic memory device of claim 1, wherein the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern are disposed at the same level with respect to a top surface of the substrate.

6. The magnetic storage device of claim 1, wherein the first magnetic tunnel junction pattern comprises:

the first free pattern;

a first pinned pattern; and

a first tunnel barrier pattern disposed between the first free pattern and the first pinned pattern,

Wherein the second magnetic tunnel junction pattern includes:

the second free pattern;

a second pinned pattern; and

a second tunnel barrier pattern disposed between the second free pattern and the second pinned pattern,

The stacking sequence of the first free pattern and the first pinned pattern on the substrate is the same as the stacking sequence of the second free pattern and the second pinned pattern on the substrate.

7. A magnetic storage device comprising:

at least one memory column, each memory column including a plurality of unit memory cells arranged in a first direction,

wherein each of the unit memory cells includes:

landing pad;

a first magnetic tunnel junction pattern spaced a first distance from the landing pad;

a second magnetic tunnel junction pattern spaced a second distance from the landing pad and spaced a third distance from the first magnetic tunnel junction pattern; and

an interconnect structure electrically connecting the landing pad to the top surface of the second magnetic tunnel junction pattern and spaced apart from the first bit line electrically connected to the top surface of the first magnetic tunnel junction pattern,

wherein the first distance and the second distance are greater than the third distance.

8. The magnetic memory device of claim 7, wherein the first magnetic tunnel junction patterns included in the memory column are arranged in the first direction, and

wherein the first distance and the second distance are greater than the distance between the first magnetic tunnel junction patterns in the first direction.

9. The magnetic memory device of claim 7, wherein the second magnetic tunnel junction patterns included in the memory column are arranged in the first direction, and

wherein the first distance and the second distance are greater than the distance between the second magnetic tunnel junction patterns in the first direction.

10. The magnetic memory device of claim 7, wherein the first magnetic tunnel junction patterns included in the memory columns are arranged in the first direction,

wherein the second magnetic tunnel junction patterns included in the memory columns are arranged in the first direction, and

The third distance is equal to the distance between the first magnetic tunnel junction patterns in the first direction and the distance between the second magnetic tunnel junction patterns in the first direction.

11. The magnetic memory device of claim 10, wherein the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern are arranged in a zigzag pattern along the first direction.

12. The magnetic memory device of claim 7, wherein the first magnetic tunnel junction patterns included in the memory column are arranged in the first direction to constitute a first sub-column,

wherein the second magnetic tunnel junction patterns included in the memory column are arranged in the first direction to constitute a second sub-column,

wherein the landing pads included in the memory column are arranged in the first direction to constitute a third sub-column,

wherein the first to third sub-columns are spaced apart from each other in a second direction perpendicular to the first direction, and

The second sub-column is arranged between the first sub-column and the third sub-column.

13. The magnetic memory device of claim 12, wherein a distance in the second direction between the second sub-column and the third sub-column is greater than the first sub-column and the second sub-column the distance between the sub-columns in the second direction.

14. The magnetic memory device of claim 12, wherein the first magnetic tunnel junction pattern included in the first sub-column and the second magnetic tunnel junction pattern included in the second sub-column The patterns are arranged in a zigzag pattern along the first direction.

15. The magnetic memory device of claim 12, wherein the second magnetic tunnel junction pattern included in the second sub-column and the landing pads included in the third sub-column are along The first directions are arranged in a zigzag form.

16. The magnetic storage device of claim 12, wherein the at least one memory rank includes a first memory rank and a second memory rank adjacent to each other in the second direction, and

wherein the third sub-column of the first memory column is adjacent to the first sub-column of the second memory column.

17. The magnetic storage device of claim 12, wherein the at least one memory rank includes a first memory rank and a second memory rank adjacent to each other in the second direction, and

wherein the first sub-column of the first memory column is adjacent to the first sub-column of the second memory column.

18. The magnetic storage device of claim 12, wherein

the first bit line is electrically connected to a top surface of the first magnetic tunnel junction pattern included in the first sub-column, and

The magnetic memory device further includes a second bit line electrically connected to a bottom surface of the second magnetic tunnel junction pattern included in the second sub-column.

19. A magnetic storage device comprising:

substrate;

an interlayer insulating layer on the substrate; and

A magnetic memory unit, on the substrate, the magnetic memory unit comprising:

landing pads on the substrate;

a first magnetic tunnel junction pattern and a second magnetic tunnel junction pattern in the interlayer insulating layer and spaced apart from the landing pad;

a first bit line conductively connected to an upper portion of the first magnetic tunnel junction pattern;

a second bit line conductively connected to a lower portion of the second magnetic tunnel junction pattern; and

an interconnection structure, on the landing pad, the interconnection structure passing through the interlayer insulating layer and conductively connecting the landing pad to an upper portion of the second magnetic tunnel junction pattern;

Wherein a first separation distance between the second magnetic tunnel junction pattern and the landing pad is greater than a second separation distance between the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern.

20. The magnetic memory device of claim 19, wherein each of the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern comprises a pinned pattern, a tunnel barrier, sequentially stacked on the substrate Patterns and Free Patterns.

21. The magnetic memory device of claim 20, wherein the pinned pattern in each of the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern is between the free pattern and the free pattern. between the substrates.

22. The magnetic memory device of claim 21, wherein the interconnect structure is conductively coupled to the free pattern of the second magnetic tunnel junction patterns, and the first bit line is conductively coupled to the second magnetic tunnel junction pattern. The free pattern of a magnetic tunnel junction pattern, the second bit line is conductively coupled to the pinned pattern of the second magnetic tunnel junction pattern.

23. The magnetic memory device of claim 19, wherein the first magnetic tunnel junction pattern is spaced apart from the second magnetic tunnel junction pattern and the landing pad in a first direction, and wherein the first magnetic tunnel junction pattern Two magnetic tunnel junction patterns are offset from the first magnetic tunnel junction pattern in a second direction perpendicular to the first direction.

24. The magnetic storage device of claim 19, further comprising:

a first bottom electrode electrically connected to the first magnetic tunnel junction pattern; and

a second bottom electrode electrically connected to the second magnetic tunnel junction pattern,

25. The magnetic memory device of claim 19, further comprising a first selection element and a second selection element on the substrate,