JP2007123512A - Magnetic storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a magnetic storage device capable of reducing a space for a memory cell. <P>SOLUTION: Magnetoresistance effect elements 15(J) are positioned so as to be vertically held between a write line 9a and bit lines B in an area where the write line 9a is crossed with the bit lines B. The magnetoresistance effect elements 15 have a lamination structure including a fixing layer 12, a tunnel insulating layer 13, and a recording layer 14. The fixing layer 12 of the magnetoresistance effect element 15 is electrically connected to the drain of a transistor 3a(T) for element selection via connection members 11, 7a. The write line 9a(WT) is electrically connected to the connection members 11, 7a. The recording layer 14 of the magnetoresistance effect elements 15 is electrically connected to the reading bit line 20a(RB) via a connection member 18a. The writing bit line 24a is positioned at interval above the reading bit line 20a. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a magnetic memory device, and more particularly to a magnetic memory device using a magnetoresistive element having a tunnel magnetoresistive effect.

  The magnetoresistance (MR) effect is a phenomenon in which electric resistance changes when a magnetic field is applied to a magnetic material, and is used in magnetic field sensors, magnetic heads, and the like. In recent years, for example, as described in Non-Patent Documents 1 and 2, as a giant magnetoresistance (GMR) effect material exhibiting a very large magnetoresistance effect, artificial lattice films such as Fe and Cr, C and Cu, etc. Has been proposed.

  In addition, a magnetoresistive element using a laminated structure composed of a ferromagnetic layer, a nonmagnetic layer, a ferromagnetic layer, and an antiferromagnetic layer having a nonmagnetic metal layer that is thick enough to eliminate exchange coupling action between ferromagnetic layers has been proposed. ing. In such a magnetoresistive effect element, the ferromagnetic layer and the antiferromagnetic layer are exchange-coupled to fix the magnetic moment of the ferromagnetic layer, and only the spin of the other ferromagnetic layer is easily inverted by an external magnetic field. I can do it. This is an element known as a so-called spin valve film.

  In this element, since the exchange coupling between the two ferromagnetic layers is weak, the spin can be reversed with a small magnetic field. Therefore, the spin valve film can provide a magnetoresistive element having higher sensitivity than the above artificial lattice film. As the antiferromagnetic material, FeMn, IrMn, PtMn, or the like is used. When this spin valve film is used, an electric current flows in the in-plane direction. However, the spin valve film is used in a reproducing head for high-density magnetic recording because of the above characteristics. ing.

  On the other hand, as described in Non-Patent Document 3, for example, it has been proposed that a larger magnetoresistive effect can be obtained by using the perpendicular magnetoresistive effect in which a current flows in a direction perpendicular to the film surface. For example, as disclosed in Non-Patent Document 4, a method of applying an external magnetic field to a three-layer film including a ferromagnetic layer, an insulating layer, and a ferromagnetic layer has been proposed. This method utilizes the fact that the spins of the two ferromagnetic layers of the three-layer film are parallel or antiparallel to each other by an external magnetic field, and the magnitude of the tunnel current in the direction perpendicular to the film surface is different. That is, this method uses a tunneling magneto-resistance (TMR) effect by a ferromagnetic tunnel junction.

  In recent years, for example, as disclosed in Non-Patent Document 5 and Non-Patent Document 6, a GMR element using the GMR height and a TMR element (magnetoresistance effect element) using the TMR effect are replaced with a nonvolatile magnetic memory semiconductor device ( A technique used for MRAM (Magnetic Random Access Memory) has been proposed, and a pseudo spin valve element and a ferromagnetic tunnel effect element in which a nonmagnetic metal layer is sandwiched between two ferromagnetic layers having different coercive forces have been studied.

  When such a pseudo spin valve element or a ferromagnetic tunnel effect element is used for an MRAM, these elements are arranged in a matrix and a magnetic field generated by passing a current through a predetermined wiring formed separately is generated. Will be applied. Information is written by controlling the magnetization directions in the two magnetic layers constituting each element to be parallel or antiparallel to each other, and the magnetization direction corresponds to “1” or “0”. Will be recorded. On the other hand, information is read using the GMR effect or the TMR effect.

In the MRAM, since the power consumption is smaller when the TMR effect is used than when the GMR effect is used, it is mainly studied to use the TMR element. In an MRAM using a TMR element, the MR ratio at room temperature is as large as 20% or more, and the resistance at the tunnel junction is large. For this reason, a larger output voltage can be obtained, and it is not necessary to perform spin inversion at the time of reading, and reading can be performed with such a small current. Since the TMR element has such a feature, the TMR element is expected to be used for a low power consumption type nonvolatile semiconductor memory device capable of high-speed writing and reading.
JP 2000-353791 A DH Mosca et al., "Oscillatory comprising coupling and giant magnetoresistance in Co / Cu multilayers", Journal of Magnetism and Magnetic Materials 94 (1991) pp.L1-L5 SSPParkin et al., "Oscillatory Magnetic Exchange Coupling through Thin Copper Layers", Physical Review Letters, vol.66, No.16, 22 April 1991, pp.2152-2155 WPPratt et al., "Perpendicular Giant Magnetoresistances of Ag / Co Multilayers", Physical Review Letters, vol.66, No.23, 10 June 1991, pp.3060-3063 T. Miyazaki et al., "Giant magnetic tunneling effect in Fe / Al2O3 / Fe junction", Journal of Magnetism and Magnetic Materials 139 (1995), pp.L231-L234 S. Tehrani et al., "High density submicron magnetoresistive random access memory (invited)", Journal of Applied Physics, vol.85, No.8, 15 April 1999, pp.5822-5827 M. Durlam et al., "A 0.18μm 4Mb Toggling MRAM", 2003 IEDM Tech. Dig., Pp.995-997

  However, the conventional MRAM has the following problems. According to Non-Patent Document 5, in addition to the TMR element and the transistor element, the MRAM memory cell includes a source line, a write line, a bit line, and a connection member that electrically connects the TMR element and the transistor element. Needed. In writing information, a specific TMR element is magnetized by passing a current through both a predetermined write line and a bit line. On the other hand, in reading information, a current flowing through a specific TMR element via a predetermined bit line is detected based on the resistance of the TMR element accompanying magnetization.

  In this way, the bit line needs to be electrically connected to the TMR element in reading information, and in writing information, it is necessary to pass a current through both the bit line and the write line. In addition to this, if the structure is such that the write line is also electrically connected to the TMR element, there arises a problem that the TMR element causes dielectric breakdown due to a difference in timing of current flow. In order to avoid this, for example, as disclosed in Patent Document 1, a structure in which the write line is not electrically connected to the TMR element and the connection member is employed.

  In order to obtain a structure in which the write line and the connection member are electrically separated, it is necessary to fill an interlayer insulating film between the write line and the connection member for each memory cell. For this reason, the entire memory cell requires a region filled with the interlayer insulating film as many as the number of memory cells, and the number of magnetic memory devices (number of chips) obtained from one wafer is limited. was there. This has also become one of the factors that hinder downsizing of the magnetic storage device.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a magnetic memory device capable of reducing the area occupied by memory cells.

  The magnetic memory device according to the present invention has a memory cell including a write line, a bit line, a magnetoresistive effect element, a transistor element, and a connection member. The write line is formed to extend in the first direction. The bit lines are spaced apart from the write lines in the vertical direction, and are formed to extend in a second direction that intersects the first direction. The magnetoresistive element is formed so as to be sandwiched between the write line and the bit line in a region where the write line and the bit line intersect. The transistor element controls the operation of the magnetoresistive element. The connecting member electrically connects the magnetoresistive effect element and the transistor element. The bit line includes a read bit line and a write bit line. The read bit line is electrically connected to the magnetoresistive element. The write bit line is electrically insulated from the magnetoresistive element. The light line is electrically connected to the connection member.

  According to this magnetic memory device, the write bit line is not electrically connected to the magnetoresistive effect element among the write bit line and the write line through which a predetermined current flows during the write operation, so that the write line is magnetically connected. It can be electrically connected to the resistance effect element. As a result, the area where the interlayer insulating film is filled between the write line and the connection member, which is conventionally required to electrically insulate the write line and the connection member, is reduced by the number of memory cells. be able to. As a result, it is possible to increase the number of chips of the magnetic storage device obtained from one wafer. In addition, the magnetic storage device can be reduced in size.

(Circuit and structure of memory cell in magnetic storage device)
Regarding the magnetic memory device according to the embodiment of the present invention, first, a circuit of a memory cell of the magnetic memory device will be described. As shown in FIG. 1, in a magnetic memory device, one memory cell M (within a dotted frame) is composed of an element selection transistor T and a magnetoresistive effect element (ferromagnetic tunnel junction element) J, and the memory A plurality of cells M are formed in a matrix.

  A write line WT and a bit line B for writing and reading information intersect the magnetoresistive effect element J. The bit line B includes two bit lines, a read bit line RB and a write bit line WB. The read bit line RB is electrically connected to one end side of each of the magnetoresistive effect elements J located in one direction (for example, a row). The write bit line WB is not electrically connected to the magnetoresistive effect element J and runs in parallel with the read bit line RB.

  On the other hand, the write line WT is electrically connected to the other end side of each magnetoresistive effect element J located in the other direction (for example, column). The other end side of the magnetoresistive effect element J is connected to the drain side of the element selection transistor T. The source sides of the element selection transistors T located in one direction are electrically connected by the source line S. The gates of the element selection transistors T located in the other direction are electrically connected to each other by the word line WD.

  Next, the structure of the magnetic storage device will be described. As shown in FIG. 2, in the memory cell region MR in the semiconductor substrate 1, the element selection transistor 3 a (T) is formed on the surface of the element formation region (the surface of the semiconductor substrate) partitioned by the element isolation insulating film 2. Yes. The element selection transistor 3 a includes a gate electrode body 4 formed on the surface of the semiconductor substrate 1 with a gate insulating film 5 interposed. A drain region 1a made of an impurity region of a predetermined conductivity type is formed on the surface portion of the semiconductor substrate 1 located on one side with the gate electrode 4 in between, and on the surface portion of the semiconductor substrate 1 located on the other side A source region 1b made of an impurity region of a predetermined conductivity type is formed.

  An interlayer insulating film 6 is formed so as to cover the element selection transistor 3a. A write line 9 a (WT) is formed on the interlayer insulating film 6. A connection member 7a for electrically connecting the write line 9a and the drain region 1a of the element selection transistor 3a is formed so as to penetrate the interlayer insulating film 6. Interlayer insulating films 8 and 10 are formed so as to cover the write line 9a. A magnetoresistive effect element 15 (J) is formed on the interlayer insulating film 10. The magnetoresistive element 15 includes a fixed layer 12, a tunnel insulating layer 13, and a recording layer 14. A connecting member 11 that electrically connects the magnetoresistive effect element 15 and the write line 9 a is formed so as to penetrate the interlayer insulating film 10.

  An interlayer insulating film 17 is formed so as to cover the magnetoresistive effect element 15. A read bit line 20 a (RB) is formed on the interlayer insulating film 17. A connection member 18 a that electrically connects the read bit line 20 a and the magnetoresistive effect element 15 is formed so as to penetrate the interlayer insulating film 17. An interlayer insulating film 21 is formed so as to cover the read bit line 20a. A write bit line 24 a (WB) is formed on the interlayer insulating film 21. An interlayer insulating film 25 is formed so as to cover the write bit line 24a. A predetermined wiring layer 28 a is formed on the interlayer insulating film 25.

  On the other hand, in the peripheral circuit region RR in the semiconductor substrate 1, a transistor 3b constituting a logic circuit is formed. On the transistor 3b, predetermined wiring layers 9b, 20b, 24b, and 28b and connection members 7b, 18b, 22, and 26 that electrically connect the wiring layers 9b, 20b, 24b, and 28b are formed. ing.

  Next, the structure of the memory cell will be described in more detail. As shown in FIG. 3, in the magnetoresistive effect element 15 (J) in which the magnetization as information is performed, the write line 9a and the bit line B intersect with the write line 9a and the bit line B in the vertical direction. Located so as to be sandwiched. The magnetoresistive effect element 14 has a laminated structure of a fixed layer 12, a tunnel insulating layer 13 and a recording layer 14. In the pinned layer 12, the direction of magnetization is fixed. In the recording layer 14, the magnetization direction is changed by injection of a magnetic field generated by a current flowing through a predetermined wiring (write bit line 24 a) or spin-polarized electrons.

  The pinned layer 12 side of the magnetoresistive effect element 15 is electrically connected to the drain of the element selection transistor 3a (T) via the connection members 11 and 7a. A light wire 9a (WT) is electrically connected to the connecting members 11 and 7a. On the other hand, the recording layer 14 side of the magnetoresistive effect element 15 is electrically connected to the read bit line 20a (RB) via the connection member 18a. The write bit line 24a is positioned above the read bit line 20a with a space therebetween.

(Operation of Memory Cell in Magnetic Storage Device)
Next, the operation of the memory cell will be described. The write operation is performed by magnetizing the magnetoresistive effect element 15 by applying a predetermined current to the write bit line 24a and the write line 9a. First, by supplying a predetermined current to each of the selected write bit line 24a and the write line 9a, a magnetic field corresponding to the direction of current flow is generated around the write bit line 24a and the write line 9a. The magnetoresistive effect element 15 located in the region where the selected write bit line 24a and the write line 9a cross each other has a magnetic field generated by the current flowing through the write bit line 24a and a magnetic field generated by the current flowing through the write line 9a. The combined magnetic field acts.

  At this time, the composite magnetic field causes the recording layer 14 of the magnetoresistive effect element 15 to be magnetized in the same direction as the magnetization direction of the pinned layer 12, and the magnetization direction of the recording layer 14 is opposite to the magnetization direction of the pinned layer 12. There is a mode of being magnetized in the direction. In this way, the recording layer 14 and the pinned layer 12 have the same magnetization direction (parallel) and opposite directions (antiparallel), and the magnetization direction is “0” or “1”. Will be recorded as information corresponding to.

  Next, the read operation is performed by applying a predetermined current to the magnetoresistive effect element 15 of a specific memory cell and detecting a difference in resistance value depending on the direction of magnetization. First, the selection transistor 3a of a specific memory cell is turned on, and a predetermined sense signal passes from the read bit line 20a through the specific magnetoresistive effect element 15 via the connection members 11 and 7a and the selection transistor 3a. Flows to the source line S.

  At this time, when the magnetization directions of the recording layer 14 and the pinned layer 12 in the magnetoresistive effect element 15 are the same direction (parallel), the resistance value is relatively low, and the magnetization directions of the recording layer 14 and the pinned layer 12 are mutually different. In the opposite direction (antiparallel), the resistance value is relatively high.

  Thereby, when the magnetization directions of the magnetoresistive effect element 15 are parallel, the intensity of the sense signal flowing through the source line S becomes larger than the signal intensity of a predetermined reference memory cell. On the other hand, when the magnetization direction of the magnetoresistive effect element 15 is antiparallel, the intensity of the sense signal is smaller than the signal intensity of a predetermined reference memory cell. Thus, whether the information written in the specific memory cell is “0” or “1” is determined depending on whether the intensity of the sense signal is larger or smaller than the signal intensity of the predetermined reference memory cell. become.

  In the memory cell in this magnetic memory device, as described above, the read bit line RB electrically connected to the magnetoresistive effect element 15 and the magnetoresistive effect element 15 are not electrically connected as the bit line B. By providing the write bit line WB, the write line WT can be connected to the connection members 11 and 7a that electrically connect the magnetoresistive effect element 15 and the selection transistor T. As a result, the area occupied by the memory cell region can be reduced.

  This will be described together with the structure of the magnetic memory device according to the comparative example. In the magnetic memory device according to the comparative example, first, as shown in FIG. 4, the write line PWT and the bit line PB for writing and reading information to and from the magnetoresistive effect element PJ in the memory cell intersect. The bit line PB is electrically connected to one end side of each of the magnetoresistive effect elements PJ located in one direction (for example, a row).

  On the other hand, the write line PWT is electrically connected to the other end side of each magnetoresistive effect element PJ located in the other direction (for example, column). The other end side of the magnetoresistive effect element PJ is connected to the drain side of the element selection transistor PT. The source sides of the element selection transistors PT positioned in one direction are electrically connected by the source line PS. In addition, the gates of the element selection transistors PT located in the other direction are electrically connected to each other by the word line PWD.

  The structure of the memory cell will be described in detail. As shown in FIG. 5, the magnetoresistive effect element 115 (PJ) that is magnetized as information has a write line 109a (PWT) and a bit line in a region where the write line 109a and the bit line 120 (PB) intersect. It is located so that it may be pinched | interposed into 120 from a vertical direction. The fixed layer 112 side of the magnetoresistive effect element 115 is electrically connected to the drain of the element selection transistor PT via the connection member 107a. The light wire 109a is electrically connected to the connecting member 107a. On the other hand, the recording layer 114 side of the magnetoresistive effect element 115 is electrically connected to the bit line 120 via a connecting member 118a.

  As already described, in the structure in which both the bit line 120 (PB) and the write line 109a (PWT) are electrically connected to the magnetoresistive effect element 115 (PJ), the bit line 120 (PB ) And the write line 109a (PWT) and the timing of current flow may cause the magnetoresistive element 115 (PJ) to break down.

  In order to solve this problem, the memory cell of the magnetic memory device according to the comparative example employs a structure in which the write line 109a (PWT) is not electrically connected to the magnetoresistive effect element 115 (PJ) and the connection member 107a. ing. That is, as shown in FIG. 5, the write line 109a (PWT) is spaced from the connection member 107a by a distance L, and a region for filling an interlayer insulating film (not shown) is secured.

  In contrast, in the memory cell of the magnetic memory device described above, of the write bit line WB and the write line WT through which a predetermined current flows during the write operation, the write bit line WB is electrically connected to the magnetoresistive effect element 15. Therefore, the write line WT can be electrically connected to the magnetoresistive effect element 15 (connecting members 11 and 7a). As a result, in the comparative example, the area filled with the interlayer insulating film between the write line and the connection member, which is necessary for electrically insulating the write line and the connection member, is as many as the number of memory cells. Can be reduced. As a result, it is possible to increase the number of chips of the magnetic storage device obtained from one wafer. In addition, the magnetic storage device can be reduced in size.

  Further, the write line WT is electrically connected to the magnetoresistive effect element 15 together with the read bit line RB. However, no current flows through the read bit line RB during the write operation, which causes problems such as dielectric breakdown. Absent.

(Arrangement mode and structure of magnetoresistive effect element)
In the memory cell region in the magnetic memory device, a plurality of memory cells are arranged in a matrix. Two modes are assumed for the arrangement pattern of the magnetoresistive effect element in the memory cell. First, there is a translational arrangement shown in FIG. In this translational arrangement, in each of the memory cells located along the direction in which the write line 9a extends, the bit line B extends in a plane with respect to the region where the magnetoresistive element (recording layer 14) 15 is located. The connecting member 11 is located on one side in the direction of the movement. The write line 9 a extends toward the connection member 11 immediately below the region where the pinned layer 12 and the tunnel insulating layer 13 of the magnetoresistive effect element 15 are located.

  Next, as another arrangement mode, there is an alternate arrangement shown in FIG. In the alternate arrangement, in each of the memory cells positioned along the direction in which the write line 9a extends, the bit line B extends in a plane with respect to the region where the magnetoresistive effect element (recording layer 14) 15 is positioned. The connection member 11 is positioned on one side of the direction, and the connection member 11 is positioned on the other side of the direction in which the bit line B extends with respect to the region where the magnetoresistive element (recording layer 14) 15 is positioned. The arrangement to be performed is set alternately. The write line 9 a extends toward the connection member 11 immediately below the region where the pinned layer 12 and the tunnel insulating layer 13 of the magnetoresistive effect element 15 are located.

  As described above, in the magnetic memory device, the magnetization direction in the magnetoresistive effect element 15 is information corresponding to “0” or “1”. In order to retain information, it is necessary to maintain the magnetization direction. In order to maintain the direction of magnetization, it is desirable that the planar shape be an anisotropic shape extending in one direction, so that the magnetization remains strongly in the longitudinal direction due to the demagnetizing field due to the anisotropic shape. become.

  Next, the arrangement pattern of the magnetoresistive effect element having such an anisotropic shape will be described by taking a translational arrangement as an example. First, in the arrangement pattern shown in FIG. 8, the direction in which the recording layer 14 of the magnetoresistive element 15 extends is the same as the direction in which the write line 9a extends. In this case, the bit line B extends in a direction orthogonal to the direction in which the recording layer 14 extends.

  Next, in the arrangement pattern shown in FIG. 9, the direction in which the recording layer 14 extends is a direction inclined by 45 ° from the direction in which the write line 9a extends. In this case, the bit line B orthogonal to the write line 9a also extends in a direction inclined by 45 ° from the direction in which the recording layer 14 extends. In this arrangement pattern, the connection member 11 is positioned in the direction in which the recording layer 14 extends. Thus, by extending the recording layer 14 at an angle of 45 ° with respect to the direction in which the write line 9a extends, the distance in the bit line B direction can be further reduced, and the memory cell area occupied in the magnetic memory device can be reduced. The area can be reduced.

  In the arrangement pattern shown in FIG. 10, the direction in which the recording layer 14 extends is inclined by 45 ° in both the direction in which the write line 9a extends and the direction in which the bit line B extends. The connecting member 11 is located on the side of the recording layer 14 in the direction in which the bit line B extends. In this arrangement pattern, the recording layer 14 is inclined at 45 ° with respect to the direction in which the write line 9 a extends, and the connection member 11 is extended in the direction in which the bit line B extends with respect to the recording layer 14. Thus, the distance in the direction of the write line 9a in addition to the direction of the bit line B can be reduced. Thereby, the occupation area of the memory cell region in the magnetic memory device can be further reduced, the number of magnetic memory devices (number of chips) obtained from one wafer can be increased, and the magnetic memory device Can be reduced in size.

  The positions of the end portions of the write lines 9a and WT are not restricted by the position of the magnetoresistive effect element 15, but the write lines 9a and WT have a magnetic field for recording information on the magnetoresistive effect element 15. It only needs to be generated. In order to efficiently apply the generated magnetic field to the magnetoresistive effect element 15, as shown in FIG. 11, the end portions of the write lines 9a and WT are arranged on the end of the recording layer 14 of the magnetoresistive effect element 15 on the plane layout. It is preferable to extend to the portion 99a (refer to the memory cell on the right side of the drawing). If the space between the adjacent memory cells is allowed, the end of the write line WT may protrude planarly from the end 99a of the recording layer 14 of the magnetoresistive effect element 15 (on the left side toward the paper surface). In other words, it is necessary not to enter the area of the adjacent magnetoresistive element 15 in a planar manner.

  In order to efficiently apply the magnetic field generated by the write line 9a to the magnetoresistive effect element 15, a structure in which three sides of the write line 9a are covered with a material having a high magnetic permeability may be employed. As shown in FIG. 12, the write bit line WB is desirably arranged immediately above the magnetoresistive effect element 15 in order to reliably perform the write operation.

  Further, in order to save power in the write operation and the read operation, as shown in FIG. 13, the interlayer insulating film 17 interposed between the magnetoresistive effect element 15 and the read bit line 20a, the read bit line 20a, The film thickness of the interlayer insulating film 21 interposed between the write bit line 24a may be made thinner so that the read bit line 20a and the write bit line 24a are closer to the magnetoresistive effect element 15. Further, as shown in FIG. 14, the fixed layer 12 of the magnetoresistive effect element 15 may be directly connected to the write line 9a. Further, as shown in FIG. 15, the read bit line 20 a may be directly connected to the recording layer 14 of the magnetoresistive effect element 15.

  Thus, by reducing the distance between the write line 9a and the surface of the magnetoresistive effect element 15, the magnetic field generated by the current flowing through the write line 9a is effectively applied to the magnetoresistive effect element 15, and writing can be performed with a small current. It becomes possible. Further, in addition to the write line 9a, the distance between the write bit line 24a and the magnetoresistive effect element 15 is shortened, so that further power saving is expected.

  In order to save power, the bit line B and the write line 9a may be formed thicker than the corresponding wiring layer in the peripheral circuit region. That is, for at least one of the write bit line 24a, the read bit line 20a, and the write line 9a, a corresponding wiring layer in the peripheral circuit region may be formed so as to increase in thickness toward the magnetoresistive element. Good. For example, FIG. 16 shows a structure in which the read bit lines 20a and RW are formed thicker than the corresponding wiring layer 20b in the peripheral circuit region RR.

  In the case of the read bit line 20a and the write line 9a, the read bit line 20a or the write line 9a is made thicker than the corresponding wiring layers 9b and 20b in the peripheral circuit region so that the magnetoresistive effect element 15 is used. You may make it contact. This also makes it possible to reliably write information with less current and to read information more reliably.

  In the magnetic memory device described above, a structure in which the write line 9a is disposed below the magnetoresistive effect element 15 and the read bit line 20a and the write bit line 24a are disposed above the magnetoresistive effect element 15 is taken as an example. However, in contrast to this structure, the read bit line 20a and the write bit line 24a are disposed below the magnetoresistive effect element 15, and the write line 9a is disposed above the magnetoresistive effect element 15. The same effect can be obtained.

(Method for manufacturing magnetic storage device)
Next, an example of a method for manufacturing the magnetic storage device described above will be described. First, as shown in FIG. 17, by forming element isolation insulating film 2 in a predetermined region on the main surface of semiconductor substrate 1, memory cell region MR and peripheral circuit region RR are formed. Gate electrode body 4 is formed on the surface of the semiconductor substrate located in memory cell region MR and peripheral circuit region RR via gate insulating film 5. By introducing impurities of a predetermined conductivity type into the surface of the semiconductor substrate 1 using the gate electrode body 4 or the like as a mask, a drain region 1a and a source region 1b made of impurity regions are formed. Thus, in the memory cell region MR, the element selection transistor 3a including the gate electrode 4, the drain region 1a, and the source region 1b is formed, and in the peripheral circuit region RR, the transistor 3b constituting the logic circuit is formed.

  An interlayer insulating film 6 is formed by, for example, a CVD (Chemical Vapor Deposition) method so as to cover the element selection transistor 3a and the transistor 3b. By performing predetermined photoengraving and etching on the interlayer insulating film 6, contact holes 6a and 6b exposing the surface of the semiconductor substrate 1 are formed. A tungsten layer (not shown) is formed on interlayer insulating film 6 so as to fill contact holes 6a and 6b. By performing CMP (Chemical Mechanical Polishing) on the tungsten layer or etching the entire surface of the tungsten layer by RIE (Reactive Ion Etching), tungsten positioned on the upper surface of the interlayer insulating film 6 is formed. The layer portion is removed, and connection members 7a and 7b are formed in the contact holes 6a and 6b as shown in FIG.

  Next, as shown in FIG. 19, an interlayer insulating film 8 is further formed on interlayer insulating film 6 by, eg, CVD. By performing predetermined photoengraving and etching on the interlayer insulating film 8, an opening 8a for forming a write line is formed in the memory cell region MR. In the peripheral circuit region RR, an opening 8b for forming a predetermined wiring layer is formed. For example, a copper film (not shown) is formed on the interlayer insulating film 8 so as to fill the openings 8a and 8b. By subjecting the copper film to a CMP process, the copper film located on the upper surface of the interlayer insulating film 8 is removed, and a write line 9a is formed in the opening 8a in the memory cell region MR. In the peripheral circuit region RR, a wiring layer 9b is formed.

  Next, as shown in FIG. 20, an interlayer insulating film 10 is further formed on interlayer insulating film 8 by, for example, a CVD method. By performing predetermined photoengraving and etching on the interlayer insulating film 10, a contact hole 10a exposing the surface of the write line 9a is formed. For example, a tungsten layer (not shown) is formed on interlayer insulating film 10 so as to fill contact hole 10a, and the tungsten layer is positioned on the upper surface of interlayer insulating film 10 by performing, for example, CMP processing or the like. The tungsten layer is removed, and the connection member 11 is formed in the contact hole 10a.

  Next, the magnetoresistive effect element 15 is formed on the interlayer insulating film 10 in the memory cell region MR. The magnetoresistive effect element 15 is composed of a laminated film of a pinned layer 12, a tunnel insulating layer 13 and a recording layer 14. First, for example, a platinum manganese film (antiferromagnetic material) having a film thickness of about 20 nm and a cobalt alloy film (ferromagnetic material) having a film thickness of about 3 nm are sequentially formed as a film to be a fixed layer. Next, an aluminum oxide film having a thickness of about 1 nm is formed as a film to be a tunnel insulating layer. Then, a nickel alloy film having a thickness of about 3 nm is formed as a film to be a recording layer (none of which is shown). The platinum manganese film to the nickel alloy film are formed by, for example, MBE (Molecular Beam Epitaxy) method.

  Thereafter, the nickel alloy film, the aluminum oxide film, the cobalt alloy film, and the platinum manganese film are subjected to predetermined etching, whereby a predetermined layer including the fixed layer 12, the tunnel insulating layer 13, and the recording layer 14 is provided as shown in FIG. A magnetoresistive effect element 15 having a shape is formed.

  Next, as shown in FIG. 22, a protective film 16 is formed so as to cover the magnetoresistive effect element 15 so that the magnetoresistive effect element 15 thus formed is not damaged by subsequent dry etching, cleaning, or the like. The An interlayer insulating film 17 is further formed on the interlayer insulating film 10 so as to cover the protective film 16. Next, an interlayer insulating film 19 is further formed on the interlayer insulating film 17.

  A predetermined connection member and a wiring layer are formed on the interlayer insulating films 19 and 17 by a dual damascene method. First, by performing predetermined photoengraving and etching on the interlayer insulating film 19, an opening (not shown) for forming a read bit line is formed in the memory cell region MR. In the peripheral circuit region RR, an opening 19a for forming a wiring layer is formed.

  Next, by performing predetermined photoengraving and etching on the interlayer insulating film 17, a contact hole 17a exposing the surface of the recording layer 14 of the magnetoresistive effect element 15 is formed in the memory cell region MR. In the peripheral circuit region RR, a contact hole 17b exposing the surface of the wiring layer 9b is formed. In addition, after forming contact holes exposing the surface of the recording layer 14 and the surface of the wiring layer 9 b in the interlayer insulating films 19 and 17, an opening 19 a and the like may be formed in the interlayer insulating film 19.

  Next, for example, a copper film (not shown) is formed on interlayer insulating film 19 so as to fill contact holes 17a, 17b, opening 19a and the like. The copper film is subjected to, for example, a CMP process to remove a portion of the copper film located on the upper surface of the interlayer insulating film 19. In the memory cell region MR, the contact hole 17 a is electrically connected to the recording layer 14. A connection member 18a to be connected is formed, and a read bit line 20a electrically connected to the connection member 18a is formed in the opening. On the other hand, in the peripheral circuit region RR, a connection member 18b electrically connected to the wiring layer 9b is formed in the contact hole 17b, and a wiring layer electrically connected to the connection member 18b is formed in the opening 19a. 20b is formed.

  Next, as shown in FIG. 23, an interlayer insulating film 21 is further formed on the interlayer insulating film 17 so as to cover the read bit line 20a and the wiring layer 20b. Next, an interlayer insulating film 23 is further formed on the interlayer insulating film 21. A predetermined connection member and a wiring layer are formed on the interlayer insulating films 23 and 21 by a dual damascene method. First, by performing predetermined photoengraving and etching on the interlayer insulating film 23, an opening (not shown) for forming a write bit line is formed in the memory cell region MR. In the peripheral circuit region RR, an opening 23a for forming a wiring layer is formed.

  Next, by performing predetermined photoengraving and etching on the interlayer insulating film 21, a contact hole 21a exposing the surface of the wiring layer 20b is formed in the peripheral circuit region RR. The contact holes that expose the surface of the wiring layer 20b may be formed in the interlayer insulating films 23 and 21, and then the opening 23a and the like may be formed in the interlayer insulating film 23.

  Next, for example, a copper film (not shown) is formed on interlayer insulating film 23 so as to fill contact hole 21a, opening 23a and the like. The copper film is subjected to, for example, a CMP process to remove a portion of the copper film located on the upper surface of the interlayer insulating film 23, and a write bit line 24a is formed in the opening in the memory cell region MR. On the other hand, in the peripheral circuit region RR, the connection member 22 electrically connected to the wiring layer 20b is formed in the contact hole 21a, and the wiring layer electrically connected to the connection member 22 in the opening 23a. 24b is formed.

  Next, as shown in FIG. 24, an interlayer insulating film 25 is formed on the interlayer insulating film 23 so as to cover the write bit line 24a and the wiring layer 24b. Next, an interlayer insulating film 27 is further formed on the interlayer insulating film 25. A predetermined connection member and a wiring layer are formed on the interlayer insulating films 27 and 25 by a dual damascene method. First, by performing predetermined photoengraving and etching on the interlayer insulating film 27, an opening 27a for forming a predetermined wiring layer is formed in the memory cell region MR. In the peripheral circuit region RR, an opening 27b for forming a predetermined wiring layer is formed. Next, by performing predetermined photoengraving and etching on the interlayer insulating film 25, a contact hole 25a exposing the surface of the wiring layer 24b is formed in the peripheral circuit region RR.

  Next, for example, a copper film (not shown) is formed on interlayer insulating film 27 so as to fill contact hole 25a and openings 27a and 27b. By performing a CMP process on the copper film, the copper film located on the upper surface of the interlayer insulating film 27 is removed, and a wiring layer 28a is formed in the opening in the memory cell region MR. In the peripheral circuit region RR, a connection member 26 electrically connected to the wiring layer 24b is formed in the contact hole 25a, and a wiring layer 28b electrically connected to the connection member 26 is formed in the opening 27b. Is done. Thus, the magnetic memory device shown in FIG. 2 is formed.

  In the above-described manufacturing method of the magnetic memory device, the tungsten layer has been described as an example of the connection member 7a and the like. However, for example, silicon may be applied. Moreover, you may apply metals, such as copper, titanium, or a tantalum. Furthermore, such metal alloys and nitrides of such metals can also be applied. Further, although the CMP method or the RIE method has been described as an example of the method for forming the connection member 7a and the like, for example, a plating method, a sputtering method, a CVD method, or the like may be applied. When copper is used as the metal, a so-called damascene method can be applied, and a wiring layer can be formed in parallel with the connection member 7a.

  Further, the single damascene method has been described as an example of the method of forming the write line 9a. However, when the write line 9a is formed simultaneously with the connecting member 7a, the dual damascene method can be applied. Furthermore, by using a metal such as silicon, tungsten, aluminum, or titanium, an alloy of such a metal, or a compound of such a metal as a wiring material, wiring can be formed by dry etching.

  Also, a method for forming the read bit line 20a, the connection member 18a, the wiring layer 20b, and the connection member 18b, a method for forming the write bit line 24a, the wiring layer 24b, and the connection member 22 positioned above the magnetoresistive element 15, and Although the dual damascene method has been described as an example of the method for forming the wiring layers 28a, 28b and the connection member 26, the connection member and the wiring layer may be formed separately by applying a single damascene method. Note that the film thickness of the interlayer insulating film interposed between the wiring layers differs depending on the device to be applied, but in this magnetic memory device, the film thickness is, for example, about 40 nm.

  The magnetoresistive effect element 15 has been described by taking aluminum oxide as an example of the tunnel insulating layer 13 of the magnetoresistive effect element 15, but the tunnel insulating layer 13 is preferably a nonmagnetic material, for example, aluminum, silicon, tantalum. A metal such as magnesium, an oxide of the metal, a nitride of the metal, an alloy of the metal, an oxide of the alloy, and a nitride of the alloy are preferable. The tunnel insulating layer 13 is preferably formed as a relatively thin film having a thickness of about 0.3 to 5 nm. Thus, when the tunnel insulating layer is made of a nonmagnetic material, the so-called giant magnetoresistance effect in the direction perpendicular to the film surface can be used.

Further, the pinned layer 12 of the magnetoresistive effect element 15 is exemplified by a laminated structure of a platinum manganese alloy film and a cobalt iron alloy film, and the recording layer 14 is exemplified by a nickel iron alloy film. The layer 14 is preferably made of a ferromagnetic material, for example, a magnetic material mainly composed of nickel, iron and / or cobalt. Furthermore, additives such as boron, nitrogen, and silicon may be introduced into the magnetic material in order to improve the magnetic characteristics and thermal stability. Furthermore, it is also possible to apply a half metal such as NiMnSb or Co ₂ MnGe. In the half metal, there is an energy gap in one spin band. By using this, a larger magnetic effect can be obtained, and as a result, a large signal output can be obtained.

  In the fixed layer, the magnetization direction can be more fixed by adopting a laminated structure of an antiferromagnetic layer and a ferromagnetic layer. That is, the antiferromagnetic layer fixes the spin direction of the ferromagnetic layer, so that the magnetization direction of the ferromagnetic layer is kept constant. The antiferromagnetic layer is preferably a compound of manganese and at least one of a ferromagnetic material such as iron or a noble metal.

  In the manufacturing method described above, the case where the pinned layer, the tunnel insulating layer, and the recording layer constituting the magnetoresistive effect element are formed by the MBE method is taken as an example. In addition to the MBE method, for example, a sputtering method, It can also be formed by chemical vapor deposition or vapor deposition.

  In the above-described method for manufacturing a magnetic memory device, the case where the pinned layer 12 of the magnetoresistive effect element 15 is directly connected to the connection member 11 has been described as an example. However, the pinned layer 12 and the connection member 11 are formed. A conductive layer may be interposed between the interlayer insulating film 8. In this case, the conductive layer may be formed in the same shape as the planar shape of the fixed layer 12 so as to overlap the fixed layer 12. As a material for the conductive layer, it is preferable to apply a low-resistance metal such as platinum, ruthenium, copper, aluminum, tantalum or the like. Further, the film thickness of the conductive layer is preferably set to, for example, 300 nm or less so that the flatness of the fixed layer 12, the tunnel insulating layer 13 and the recording layer 14 formed on the conductive layer is not impaired.

  In the case where the fixing layer 12 is formed in the same size as the recording layer 14, the conductive layer needs to be formed larger than the fixing layer 14 so that the conductive layer is connected to the connection member 7a. Is larger than the pinned layer, there is no problem as a magnetoresistive element.

  In this way, when the connecting member 11 is made of copper, for example, by interposing a predetermined conductive layer between the interlayer insulating film 8 and the magnetoresistive effect element 15, the magnetoresistive effect element 15 is patterned by etching. At this time, the copper connecting member 11 can be prevented from corroding. Further, by applying a material having a resistance lower than the resistance of the pinned layer 12 of the magnetoresistive effect element 15 as the conductive layer, the resistance of the current path at the time of reading can be lowered, and the reading speed is improved. Can also be planned.

  Further, in the magnetic memory device described above, a protective film is provided so as to cover the magnetoresistive effect element 15 in order to prevent the magnetoresistive effect element 15 from being damaged in the process after the magnetoresistive effect element is formed. The case of forming 16 has been described as an example. As damage that the magnetoresistive effect element 15 may receive in the manufacturing process, for example, there is a heat treatment when an interlayer insulating film is formed. When a silicon oxide film is formed as an interlayer insulating film, the silicon oxide film is formed under an oxidizing atmosphere at a temperature of about 400 ° C.

  At this time, the magnetic film may be oxidized under an oxidizing atmosphere, which may deteriorate the magnetic characteristics of the magnetoresistive element. By covering the magnetoresistive effect element with the protective film 16 such as a silicon nitride film, the protective film functions as a barrier for this oxidation and can protect the magnetoresistive effect element.

  In order to prevent such oxidation, the interlayer insulating film may have a two-layer structure of a thin film that can be formed under a non-oxidizing atmosphere such as a silicon nitride film and an oxidizing insulating film. In this case, of the two-layer interlayer insulating film, the silicon nitride film serves as a protective film for the magnetoresistive element.

  Further, as the protective film, a film containing at least one material among an insulating metal nitride, an insulating metal carbide, and a metal oxide formed by oxidation treatment of a metal having a lower free energy of oxide generation than Fe is used. preferable. By using such a material, it is possible to suppress the magnetoresistive element from being oxidized during the oxidation process in the manufacturing process of the magnetic memory semiconductor device using the magnetic material thin film containing at least Fe. As a result, a magnetic memory semiconductor device that is easy to manufacture and has stable operating characteristics can be obtained.

  When a material having a relatively high dielectric constant, such as a silicon nitride film, is used as an oxide barrier for a mixed device including a memory cell including a magnetoresistive element and a logic circuit, It must be noted. That is, for example, in a device composed of a logic circuit, the capacitance and wiring resistance between metal wiring layers are set in consideration of the operation speed and access timing of the device. Therefore, if a material with a high dielectric constant is placed in the logic circuit section, the capacitance between the metal wiring layers in the logic circuit section may fall outside the predetermined design parameter range, and the device may not perform a desired operation. . In order to avoid this, it is preferable that the protective film is formed so as to cover only the magnetoresistive effect element 15, and the protective film is not formed in the peripheral circuit region RR where the logic circuit is formed.

  In the magnetic storage device using the magnetoresistive effect element described above, it is possible to read the stored information without destroying the storage state. This eliminates the need for rewriting and increases the reading speed. Further, since the magnetization reversal speed is 1 nanosecond or less, information can be written at a very high speed. Furthermore, with respect to the magnetization reversal operation, it is generally said that a fatigue phenomenon in which the characteristics deteriorate due to repeated reversal does not occur. That is, the magnetic storage device called MRAM can provide a non-volatile memory device with virtually no limit on the number of operations.

  The above-described feature is useful as a single memory device, but it works even more effectively in the case of a mixed device in which the memory cell is mixed with a logic circuit. That is, in the case of a mixed device, an interactive handling environment of information in a network environment or mobile communication is improved based on high-speed operation. Furthermore, by applying the magnetic storage device to a computer, a portable terminal or the like, it is possible to greatly reduce power consumption and improve the operating environment.

  In the magnetic memory device described above, the magnetic memory device using the semiconductor substrate has been described. However, the relationship between the magnetoresistive effect element and the wiring layer related to the write line and the bit line is not limited to information storage. For example, the present invention can be widely applied to patterned magnetic elements such as a magnetic sensor, a magnetic recording head, and a magnetic recording medium.

  Further, in the magnetic memory device described above, a memory cell in which one memory cell is provided with one magnetoresistive element has been described as an example. However, two or more magnetoresistive elements are provided in one memory cell. These memory cells may be stacked on each other.

  The embodiments disclosed herein are merely examples in all respects, and the present invention is not limited thereto. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows the equivalent circuit of the memory cell in the magnetic memory device which concerns on embodiment of this invention. 4 is a cross-sectional view showing the structure of a memory cell region and a peripheral circuit region in the same embodiment. 4 is a partial perspective view showing a structure of one memory cell in a memory cell region in the same embodiment. FIG. 4 is a diagram showing an equivalent circuit of a memory cell in a magnetic memory device according to a comparative example in the embodiment. FIG. 4 is a partial perspective view showing a structure of one memory cell in a memory cell region of a magnetic memory device according to a comparative example in the embodiment. FIG. 5 is a partial plan view showing a first example of a planar shape of a magnetoresistive effect element in the embodiment. FIG. In the embodiment, it is a partial plan view showing a second example of the planar shape of the magnetoresistive effect element. In the same embodiment, it is a fragmentary top view which shows the 3rd example of the planar shape of a magnetoresistive effect element. In the same embodiment, it is a fragmentary top view which shows the 4th example of the planar shape of a magnetoresistive effect element. FIG. 10 is a partial plan view showing a fifth example of the planar shape of the magnetoresistive effect element in the embodiment. In the same embodiment, it is a top view which shows the positional relationship of a magnetoresistive effect element and a write line. In the same embodiment, it is a top view which shows the positional relationship of a magnetoresistive effect element and a write bit line. FIG. 16 is a cross-sectional view showing a structure of a memory cell portion according to a modification in the embodiment. FIG. 16 is a cross-sectional view showing a structure of a memory cell portion according to another modification example in the embodiment. FIG. 22 is a cross-sectional view showing a structure of a memory cell portion according to still another modification in the embodiment. FIG. 22 is a cross-sectional view showing a structure of a memory cell portion according to still another modification in the embodiment. FIG. 6 is a cross-sectional view showing a step of the method for manufacturing the magnetic memory device in the embodiment. FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the same embodiment. FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the same embodiment. FIG. 20 is a cross-sectional view showing a step performed after the step shown in FIG. 19 in the same embodiment. FIG. 21 is a partial enlarged cross-sectional view showing a portion of the magnetoresistive effect element in the step shown in FIG. 20 in the same embodiment. FIG. 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in the same embodiment. FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22 in the same embodiment. FIG. 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the same embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 1a drain region, 1b source region, 2 element isolation insulating film, 3a, T element selection transistor, 3b transistor, 4 gate electrode body, 5 gate insulating film, 6, 8, 10, 17, 19, 21 , 23, 25, 27 Interlayer insulating film, 6a, 8b, 10a, 17a, 21a, 25a Contact hole, 7a, 11, 18a, 18b, 22, 26 Connection member, 9a, WT write line, 9b, 20b, 24b, 28a, 28b Wiring layer, 12 pinned layer, 13 tunnel insulating layer, 14 recording layer, 15 J magnetoresistive effect element, 16 protective film, 20a, RB read bit line, 24a, WB write bit line, WD word line, S Source line, B bit line, M Memory cell.

Claims (10)

A light line formed to extend in a first direction;
A bit line that is vertically spaced from the write line and extends in a second direction intersecting the first direction;
A magnetoresistive effect element formed so as to be sandwiched between the write line and the bit line in a region where the write line and the bit line intersect;
A transistor element for controlling the operation of the magnetoresistive element;
A memory cell including a connection member that electrically connects the magnetoresistive element and the transistor element;
The bit line comprises a read bit line and a write bit line;
The read bit line is electrically connected to the magnetoresistive element;
The write bit line is electrically insulated from the magnetoresistive element;
The magnetic storage device, wherein the write line is electrically connected to the connection member. The connecting member is
A first connecting member;
The magnetic storage device according to claim 1, further comprising a second connection member that electrically connects the first connection member and the magnetoresistive effect element.   The magnetic memory device according to claim 2, wherein the second connection member is formed of a material different from a material constituting the magnetoresistive effect element. A plurality of the memory cells are formed in a matrix,
In each of the memory cells located along the first direction, as a mode of arrangement of the memory cells, the memory cell is arranged on one side in the second direction with respect to a region where the magnetoresistive effect element is planarly located. The magnetic storage device according to claim 1, wherein the magnetic storage device is in a translational arrangement in which the connection member is located. The magnetoresistive element includes an anisotropic region in which a planar shape extends in a third direction in order to maintain the direction of magnetization,
5. The magnetic memory device according to claim 4, wherein in the magnetoresistive element, the third direction is set to intersect both the first direction and the second direction. 6. The first direction and the second direction are orthogonal to each other,
The magnetic storage device according to claim 5, wherein the third direction is a direction inclined by 45 ° with respect to the first direction and the second direction. A plurality of the memory cells are formed in a matrix,
In each of the memory cells positioned along the first direction, as a mode of arrangement of the memory cells, the one side in the second direction with respect to the region where the magnetoresistive element is positioned in a plane Alternating arrangement in which the arrangement in which the connecting member is located and the arrangement in which the connecting member is located on the other side in the second direction with respect to the region in which the magnetoresistive effect element is located in a plane are alternately set The magnetic storage device according to claim 1.   The said write line is formed so that it may extend to the edge part of the area | region of the said corresponding magnetoresistive effect element, and it may overlap with the said magnetoresistive effect element planarly. Magnetic storage device.   The magnetic storage device according to claim 1, wherein the write bit line is disposed immediately above the magnetoresistive effect element.   10. The memory cell region in which a plurality of the memory cells are formed and a peripheral circuit region in which a logic circuit for controlling each of the memory cells is disposed on a predetermined semiconductor substrate. The magnetic storage device described in 1.

Images