JP2003007738A - Method for manufacturing ic package - Google Patents
Method for manufacturing ic packageInfo
- Publication number
- JP2003007738A JP2003007738A JP2001183032A JP2001183032A JP2003007738A JP 2003007738 A JP2003007738 A JP 2003007738A JP 2001183032 A JP2001183032 A JP 2001183032A JP 2001183032 A JP2001183032 A JP 2001183032A JP 2003007738 A JP2003007738 A JP 2003007738A
- Authority
- JP
- Japan
- Prior art keywords
- manufacturing
- package
- substrate
- transparent resin
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 26
- 239000011347 resin Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 239000004593 Epoxy Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229920003023 plastic Polymers 0.000 claims description 2
- 239000000523 sample Substances 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- 229910010293 ceramic material Inorganic materials 0.000 claims 1
- 239000004033 plastic Substances 0.000 claims 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000004804 winding Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＩＣパッケージの製
造方法に関する。TECHNICAL FIELD The present invention relates to a method of manufacturing an IC package.
【０００２】[0002]
【従来の技術】これまで光をＩＣチップにあてるＩＣパ
ッケージは図４に示すように、枠４７を有する個片の基
板４１にＩＣチップ４５をのせワイヤ４６をはり、枠４
７にあわせるようにガラス製の板状のふた４９をのせて
いた。2. Description of the Related Art Up to now, as shown in FIG. 4, an IC package which applies light to an IC chip has an IC chip 45 mounted on an individual substrate 41 having a frame 47, a wire 46 being attached thereto, and a frame 4
A plate-shaped lid 49 made of glass was placed so as to fit 7.
【０００３】[0003]
【発明が解決しようとする課題】従来の光を通すＩＣパ
ッケージは、１個1個別別に製造されているため生産性
が著しく低く、それゆえ非常に高価なものとなってい
た。Since the conventional light-transmitting IC packages are manufactured individually one by one, the productivity is remarkably low, and therefore, it is very expensive.
【０００４】[0004]
【課題を解決するための手段】上記の問題点を解決する
ために、本発明は複数以上のＩＣチップを載せられる基
板を用い、透明樹脂をＩＣチップおよびワイヤを被うよ
うに厚く形成し、硬化させた後で、基板を切断すること
により１個1個のＩＣパッケージにする。In order to solve the above problems, the present invention uses a substrate on which a plurality of IC chips can be mounted, and a transparent resin is formed thick so as to cover the IC chips and the wires. After curing, the substrate is cut into individual IC packages.
【０００５】[0005]
【発明の実施の形態】本発明は、光をＩＣチップにあて
られるＩＣパッケージの製造方法に関するものである。
以下にこの発明の実施例を図面に基づいて説明する。BEST MODE FOR CARRYING OUT THE INVENTION The present invention relates to a method of manufacturing an IC package in which light is applied to an IC chip.
Embodiments of the present invention will be described below with reference to the drawings.
【０００６】図１は、本発明の製造方法の工程順を示す
ＩＣパッケージの断面図を示す。FIG. 1 is a sectional view of an IC package showing the order of steps in the manufacturing method of the present invention.
【０００７】図１(ａ)に示すように、外部電極１２と内
部電極配線１３を有する基板１１が用意される。この基
板１１内には複数以上のたくさんのＩＣチップが搭載さ
れ、最終的に個片にされる。従って基板のサイズは大型
であり、外部電極１２も内部電極配線１３も繰り返しの
パターンとなっている。基板１１の材料は、セラミック
やガラスエポキシやポリイミドやガラスなどが挙げられ
る。As shown in FIG. 1A, a substrate 11 having an external electrode 12 and an internal electrode wiring 13 is prepared. Many or more IC chips are mounted in the substrate 11 and finally separated into individual pieces. Therefore, the size of the substrate is large, and the external electrodes 12 and the internal electrode wirings 13 have a repeating pattern. Examples of the material of the substrate 11 include ceramic, glass epoxy, polyimide, glass and the like.
【０００８】次に図１(ｂ)に示すように、ＩＣチップ１
５を内部電極配線の所望の位置に接着する。尚、ＩＣチ
ップ１５の接着する位置には、内部電極配線１３はなく
て良い場合もある。たとえば、ＩＣチップの表面をでき
るだけ低くする必要がある場合や、ＩＣチップを電気的
に導通する必要がない場合や、ＩＣチップを放熱する必
要があまりない場合などである。次にＩＣチップ１５の
表面の電極と内部電極配線とをワイヤ１６で接続する。
このワイヤの材料として、金(Ａｕ)、金合金、アルミニ
ウム(Ａｌ)、アルミニウム合金、銅(Ｃｕ)、銅合金など
の金属が使われる。Next, as shown in FIG. 1B, the IC chip 1
5 is adhered to a desired position of the internal electrode wiring. In some cases, the internal electrode wiring 13 may not be provided at the position where the IC chip 15 is bonded. For example, there are cases where it is necessary to make the surface of the IC chip as low as possible, where it is not necessary to electrically conduct the IC chip, and where there is not much need to radiate heat from the IC chip. Next, the electrodes on the surface of the IC chip 15 and the internal electrode wiring are connected by the wires 16.
As a material of this wire, a metal such as gold (Au), gold alloy, aluminum (Al), aluminum alloy, copper (Cu), or copper alloy is used.
【０００９】次に図１(ｃ)に示すように透明樹脂１７を
塗布する。この透明樹脂１７は塗布する時には液状なの
で、ＩＣチップ１５を移動させたり、ＩＣチップ１５に
ダメッジを与えたり、ワイヤ１６を曲げたり、ワイヤ１
６にダメッジを与えたり、ワイヤ１６と電極配線１３お
よびＩＣチップ１５との接着場所にダメッジを与えたり
することはない。この透明樹脂１７として、シリケート
ガラスを主成分とする材料がある。また透明プラスティ
ックもある。さらに、赤外線や紫外線に対して透明なエ
ポキシ樹脂も挙げられる。また、塗布する透明樹脂１７
の厚みは、最終的にワイヤ１６の最も高い所より高くな
るように設計されなければならない。透明樹脂１７を硬
化するために、熱処理を行ったり、材料によっては紫外
線をあてて硬化する。硬化によって透明樹脂１７が縮小
しても、ワイヤが透明樹脂１７よりはみ出さないように
する。次に図１(ｄ)に示すように、次に図１(ｄ)に示す
ように、ＩＣチップ１５の間で透明樹脂１７および基板
１１を切断する。この切断の方法として、ダイシング装
置を用いて行う方法やワイヤーソーを用いて行う方法や
レーザーや高圧水を用いて切断する方法がある。また、
ダイシングで行う場合、最初比較的幅の広いブレードを
用いて浅く切断しその後幅の狭いブレードで切断するこ
とで、切断面にクラックが入ることを防止する方法を用
いることもできる。Next, as shown in FIG. 1C, a transparent resin 17 is applied. Since the transparent resin 17 is liquid when applied, the IC chip 15 is moved, the IC chip 15 is damaged, the wire 16 is bent, and the wire 1
No damage is given to 6 and no damage is given to the bonding position of the wire 16 with the electrode wiring 13 and the IC chip 15. As the transparent resin 17, there is a material containing silicate glass as a main component. There is also transparent plastic. Furthermore, an epoxy resin that is transparent to infrared rays and ultraviolet rays can also be used. In addition, the transparent resin 17 to be applied
Must be designed so that it is ultimately higher than the highest point of the wire 16. In order to cure the transparent resin 17, heat treatment is performed or, depending on the material, ultraviolet rays are applied to cure the transparent resin 17. Even if the transparent resin 17 shrinks due to curing, the wire is prevented from protruding from the transparent resin 17. Next, as shown in FIG. 1D, the transparent resin 17 and the substrate 11 are cut between the IC chips 15 as shown in FIG. 1D. The cutting method includes a method using a dicing device, a method using a wire saw, and a method using laser or high-pressure water. Also,
In the case of dicing, it is possible to use a method in which a relatively wide blade is first used to cut shallowly, and then a narrow blade is used to prevent cracks from forming on the cut surface.
【００１０】このようにして、図１(ｅ)に示すように、
ＩＣチップ１５が透明樹脂で被われたＩＣパッケージを
得る。さて、ＩＣパッケージの電気特性の測定方法とし
て、従来と同じく１個のパッケージになった後で測定す
ることはもちろん可能である。そのほかに、図１(ｄ)で
基板を切断する前に測定することもできる。すなわち、
基板の電極に合せてプローブカードを作成しウエハ測定
の時と同じ方法で測定できる。従って多数のＩＣパッケ
ージを１回のプロービングで測定することも可能であ
る。Thus, as shown in FIG. 1 (e),
An IC package in which the IC chip 15 is covered with a transparent resin is obtained. As a method of measuring the electrical characteristics of the IC package, it is of course possible to measure the IC package after it has been formed into one package, as in the conventional case. Alternatively, the measurement can be performed before cutting the substrate in FIG. That is,
It is possible to make a probe card according to the electrodes on the substrate and perform the measurement in the same manner as in the wafer measurement. Therefore, it is possible to measure many IC packages with one probing.
【００１１】図２は、図１(ｃ)の平面図を示す。基板２
１内に多数のＩＣチップ２５が搭載されている。ＩＣチ
ップ２５およびワイヤ２６は透明樹脂２７で被われてい
る。図３は、図１(ｄ)の平面図を示す。点線で示す位置
で切断される。透明樹脂３７および基板３１はＩＣチッ
プ３５の間で切断される。FIG. 2 shows a plan view of FIG. 1 (c). Board 2
A large number of IC chips 25 are mounted in one unit. The IC chip 25 and the wires 26 are covered with a transparent resin 27. FIG. 3 shows a plan view of FIG. It is cut at the position indicated by the dotted line. The transparent resin 37 and the substrate 31 are cut between the IC chips 35.
【００１２】[0012]
【発明の効果】以上、説明したように基板内に多数のＩ
Ｃパッケージを一挙に作り込み、最後に切断して１個1
個のＩＣパッケージにするので、生産性が大幅に向上し
製造費も大幅に低減する。また、切断する前に１枚の基
板になっている時に電気特性を測定できるので、ウエハ
プローバーと同様の思想で多数のＩＣの電気特性を一挙
に測定できることになり、テストに要する費用を大幅に
削減できる。透明樹脂を用いているため光は自由にＩＣ
チップに射し込む。特にＩＣがイメージセンサーやＣＣ
Ｄなどの撮像素子である場合には、有効である。またＩ
Ｃチップおよびワイヤは透明樹脂で被われているため、
外部環境に対して信頼性が高い。As described above, a large number of I's are formed in the substrate as described above.
Make a C package all at once and cut it at the end to get 1
Since it is an individual IC package, productivity is greatly improved and manufacturing cost is also significantly reduced. In addition, since the electrical characteristics can be measured before it is cut into one substrate, the electrical characteristics of many ICs can be measured all at once with the same idea as the wafer prober, and the cost required for the test can be greatly increased. Can be reduced. Light is freely IC because it uses a transparent resin
Hit the tip. Especially IC is image sensor and CC
This is effective in the case of an image pickup device such as D. Also I
Since the C chip and wire are covered with transparent resin,
Highly reliable for the external environment.
【図１】本発明のＩＣパッケージの製造方法を示す図で
ある。FIG. 1 is a diagram showing a method for manufacturing an IC package of the present invention.
【図２】図１(ｃ)の平面図を示す図である。FIG. 2 is a diagram showing a plan view of FIG. 1 (c).
【図３】図１(ｄ)の平面図を示す図である。FIG. 3 is a diagram showing a plan view of FIG. 1 (d).
【図４】従来のＩＣパッケージを示す図である。FIG. 4 is a diagram showing a conventional IC package.
１１、２１、３１、４１ 半導体基板 １２，４２ 外部電極 １３、２３、３３、４３ 内部電極配線 １５，２５，３５，４５ ＩＣチップ １６、２６，３６，４６ ワイヤ １７、２７，３７ 透明樹脂 ４７ 枠 ４９ ふた 11, 21, 31, 41 Semiconductor substrate 12,42 External electrode 13, 23, 33, 43 Internal electrode wiring 15, 25, 35, 45 IC chips 16,26,36,46 wire 17, 27, 37 Transparent resin 47 frames 49 lid
Claims (10)
にＩＣチップを載せてＩＣチップ内の電極と前記内部電
極配線とをワイヤで接続する工程と透明樹脂を塗布しＩ
Ｃチップおよびワイヤを被う工程とＩＣチップ間で基板
と透明樹脂を切断する工程とからなることを特徴とする
ＩＣパッケージの製造方法1. A step of mounting an IC chip on a substrate having external electrodes and internal electrode wiring, connecting electrodes in the IC chip and the internal electrode wiring with wires, and applying a transparent resin I
A method of manufacturing an IC package, comprising a step of covering the C chip and the wire and a step of cutting the substrate and the transparent resin between the IC chips.
硬化する工程を付加することを特徴とする請求項１記載
のＩＣパッケージの製造方法2. The method of manufacturing an IC package according to claim 1, further comprising a step of hardening the transparent resin by heat treatment.
する前記基板はガラスエポキシ材料であることを特徴と
する請求項１記載のＩＣパッケージの製造方法3. The method of manufacturing an IC package according to claim 1, wherein the substrate having the external electrodes and the internal electrode wiring is made of a glass epoxy material.
する前記基板はセラミック材料であることを特徴とする
請求項１記載のＩＣパッケージの製造方法4. The method of manufacturing an IC package according to claim 1, wherein the substrate having the external electrodes and the internal electrode wiring is made of a ceramic material.
分とする材料であることを特徴とする請求項１記載のＩ
Ｃパッケージの製造方法5. The I according to claim 1, wherein the transparent resin is a material containing silicate glass as a main component.
C package manufacturing method
ポキシ樹脂であることを特徴とする請求項１記載のＩＣ
パッケージの製造方法6. The IC according to claim 1, wherein the transparent resin is an epoxy resin transparent to infrared rays.
Package manufacturing method
ポキシ樹脂であることを特徴とする請求項１記載のＩＣ
パッケージの製造方法7. The IC according to claim 1, wherein the transparent resin is an epoxy resin transparent to ultraviolet rays.
Package manufacturing method
あることを特徴とする請求項１記載のＩＣパッケージの
製造方法8. The method of manufacturing an IC package according to claim 1, wherein the transparent resin is a plastic material.
ケージの電気特性を基板全体を用いて測定する工程を含
むことを特徴とする請求項１記載のＩＣパッケージの製
造方法9. The method of manufacturing an IC package according to claim 1, further comprising the step of measuring the electrical characteristics of the IC package using the entire substrate before cutting the substrate.
特性を測定することを特徴とする請求項９記載のＩＣパ
ッケージの製造方法10. The method of manufacturing an IC package according to claim 9, wherein the electrical characteristics are measured using a probe card jig.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001183032A JP2003007738A (en) | 2001-06-18 | 2001-06-18 | Method for manufacturing ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001183032A JP2003007738A (en) | 2001-06-18 | 2001-06-18 | Method for manufacturing ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003007738A true JP2003007738A (en) | 2003-01-10 |
Family
ID=19023037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001183032A Pending JP2003007738A (en) | 2001-06-18 | 2001-06-18 | Method for manufacturing ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003007738A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004256816A (en) * | 2003-02-27 | 2004-09-16 | Eternal Chemical Co Ltd | Material composition for packaging photosensitive elements and method of using same |
-
2001
- 2001-06-18 JP JP2001183032A patent/JP2003007738A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004256816A (en) * | 2003-02-27 | 2004-09-16 | Eternal Chemical Co Ltd | Material composition for packaging photosensitive elements and method of using same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6714418B2 (en) | Method for producing an electronic component having a plurality of chips that are stacked one above the other and contact-connected to one another | |
| US6689640B1 (en) | Chip scale pin array | |
| JP4403631B2 (en) | Manufacturing method of chip-shaped electronic component and manufacturing method of pseudo wafer used for manufacturing the same | |
| US9269671B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| US20020133943A1 (en) | Method for manufacturing circuit device | |
| US20020180040A1 (en) | Super thin/super thermal ball grid array package | |
| CN105590872B (en) | Method of manufacturing semiconductor device | |
| US5771157A (en) | Chip-on-board printed circuit assembly using aluminum wire bonded to copper pads | |
| US20250183135A1 (en) | Lead stabilization in semiconductor packages | |
| JPH04264758A (en) | Semiconductor chip carrier | |
| JP2002299546A (en) | Chip-like electronic component, manufacturing method therefor, pseudo wafer used for manufacturing and manufacturing method therefor | |
| US20180197809A1 (en) | Semiconductor device with frame having arms and related methods | |
| JP2002373950A (en) | Method for manufacturing hermetically sealed ic package | |
| US20080036054A1 (en) | Packaging System For Semiconductor Devices | |
| JP4813693B2 (en) | Method for manufacturing hermetically sealed IC package | |
| JP2003007738A (en) | Method for manufacturing ic package | |
| JP2002373953A (en) | Method for manufacturing hermetically sealed ic package | |
| JP2002373906A (en) | Manufacturing method for ic package | |
| JP3303162B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3468386B2 (en) | Method for manufacturing semiconductor device | |
| JP4813692B2 (en) | Method for manufacturing hermetically sealed IC package | |
| JP2002373954A (en) | Method for manufacturing hermetically sealed ic package | |
| KR100207902B1 (en) | Multi chip package using lead frame | |
| JP3424649B2 (en) | Failure analysis method for semiconductor device | |
| JP2002373951A (en) | Method for manufacturing hermetically sealed ic package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20040303 |