JP2002373954A - Method for manufacturing hermetically sealed ic package - Google Patents
Method for manufacturing hermetically sealed ic packageInfo
- Publication number
- JP2002373954A JP2002373954A JP2001182443A JP2001182443A JP2002373954A JP 2002373954 A JP2002373954 A JP 2002373954A JP 2001182443 A JP2001182443 A JP 2001182443A JP 2001182443 A JP2001182443 A JP 2001182443A JP 2002373954 A JP2002373954 A JP 2002373954A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- epoxy resin
- package
- chip
- internal electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000003822 epoxy resin Substances 0.000 claims abstract description 20
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 20
- 239000011521 glass Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000000523 sample Substances 0.000 claims description 2
- 229910010293 ceramic material Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は気密封止ＩＣパッケ
ージの製造方法に関する。The present invention relates to a method for manufacturing a hermetically sealed IC package.
【０００２】[0002]
【従来の技術】これまでの気密封止ＩＣパッケージは図
に示すように、枠４７を有する個片の基板４１にＩＣチ
ップ４５をのせワイヤ４６をはり、枠４７にあわせるよ
うに板状のふた４９をのせていた。2. Description of the Related Art As shown in FIG. 1, a conventional hermetically sealed IC package has an IC chip 45 mounted on an individual substrate 41 having a frame 47 and a wire 46 mounted thereon. 49 was on it.
【０００３】[0003]
【発明が解決しようとする課題】従来の気密封止ＩＣパ
ッケージは、１個1個別別に製造されているため生産性
が著しく低く、それゆえ非常に高価なものとなってい
た。The conventional hermetically sealed IC packages are manufactured individually and individually, resulting in extremely low productivity and, therefore, very expensive.
【０００４】[0004]
【課題を解決するための手段】上記の問題点を解決する
ために、本発明は複数以上のＩＣチップを載せられる基
板を用い、デスペンサーを用いてエポキシ樹脂をＩＣチ
ップ間に厚く形成し、板状のふたを被せた後で、基板を
切断することにより１個1個のＩＣパッケージにする。In order to solve the above problems, the present invention uses a substrate on which a plurality of IC chips are mounted, and forms a thick epoxy resin between the IC chips using a dispenser. After covering the plate-like lid, the substrate is cut into individual IC packages.
【０００５】[0005]
【発明の実施の形態】本発明は、ＩＣチップの表面を空
気などの気体で取り囲んだ気体封止型のパッケージの製
造方法に関するものである。以下にこの発明の実施例を
図面に基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a method for manufacturing a gas-sealed package in which the surface of an IC chip is surrounded by a gas such as air. Embodiments of the present invention will be described below with reference to the drawings.
【０００６】図１は、本発明の製造方法の工程順を示す
ＩＣパッケージの断面図を示す。FIG. 1 is a sectional view of an IC package showing a process sequence of the manufacturing method of the present invention.
【０００７】図１(ａ)に示すように、外部電極１２と内
部電極配線１３を有する基板１１が用意される。この基
板内には複数以上のたくさんのＩＣチップが搭載され、
最終的に個片にされる。従って基板のサイズは大型であ
り、外部電極１２も内部電極配線１３も繰り返しのパタ
ーンとなっている。基板１１の材料は、セラミックやガ
ラスエポキシやポリイミドやガラスなどが挙げられる。As shown in FIG. 1A, a substrate 11 having external electrodes 12 and internal electrode wirings 13 is prepared. Many or more IC chips are mounted on this board,
Finally, it is singulated. Therefore, the size of the substrate is large, and the external electrode 12 and the internal electrode wiring 13 have a repeating pattern. The material of the substrate 11 includes ceramic, glass epoxy, polyimide, glass, and the like.
【０００８】次に図１(ｂ)に示すように、ＩＣチップ１
５を内部電極配線の所望の位置に接着する。尚、ＩＣチ
ップ１５の接着する位置には、内部電極配線１３はなく
て良い場合もある。たとえば、ＩＣチップの表面をでき
るだけ低くする必要がある場合や、ＩＣチップを電気的
に導通する必要がない場合や、ＩＣチップを放熱する必
要があまりない場合などである。次にＩＣチップ１５の
表面の電極と内部電極配線とをワイヤ１６で接続する。
このワイヤの材料として、金(Ａｕ)、金合金、アルミニ
ウム(Ａｌ)、アルミニウム合金、銅(Ｃｕ)、銅合金など
の金属が使われる。[0008] Next, as shown in FIG.
5 is bonded to a desired position of the internal electrode wiring. In some cases, the internal electrode wiring 13 may not be provided at the position where the IC chip 15 is bonded. For example, there is a case where the surface of the IC chip needs to be as low as possible, a case where there is no need to electrically conduct the IC chip, and a case where there is little need to radiate the heat of the IC chip. Next, the electrodes on the surface of the IC chip 15 and the internal electrode wiring are connected by wires 16.
As a material of the wire, a metal such as gold (Au), a gold alloy, aluminum (Al), an aluminum alloy, copper (Cu), or a copper alloy is used.
【０００９】次に図１(ｃ)に示すようにデスペンサー１
８を用いてエポキシ樹脂１７をＩＣチップ１５およびワ
イヤ１６と接続している基板１１の内部電極配線１３の
間に、それらを取り囲むように描画塗布する。塗布する
エポキシ樹脂１７の厚みは、最終的にワイヤ１６の最も
高い所より高くなるように設計されなければならない。Next, as shown in FIG.
Using 8, an epoxy resin 17 is drawn and applied between the internal electrode wires 13 of the substrate 11 connected to the IC chip 15 and the wires 16 so as to surround them. The thickness of the epoxy resin 17 to be applied must be designed so as to be finally higher than the highest point of the wire 16.
【００１０】次に図１(ｄ)はデスペンサー１８で塗布描
画を終えた状態を示す。エポキシ樹脂１７はＩＣチップ
１５およびワイヤ１６が接続する基板１６の内部配線１
３の間に厚く形成されている。Next, FIG. 1D shows a state in which coating and drawing have been completed by the dispenser 18. Epoxy resin 17 is used for internal wiring 1 of substrate 16 to which IC chip 15 and wire 16 are connected.
3 is formed thick.
【００１１】次に図１(ｅ)に示すように、板状のふた１
９を接着する。この場合、エポキシ樹脂１７の上に接着
材料を付着してからふた１９を接着する方法、あるいは
ふた１９の方にエポキシ樹脂１７が来る位置に接着材を
塗布してからふた１９を接着する方法、あるいはエポキ
シ樹脂１７とふた１９を熱処理で接着する方法などがあ
る。この板状のふた１９として、光を通すことが必要で
あればガラスや透明プラスチックなどのその光に透明な
物質からなる材料にする。光を通す必要がなければ、セ
ラミックやガラスエポキシやポリイミドなどの材料を用
いることができる。またテープ状のシートでも用途によ
って使うこともできる。Next, as shown in FIG.
9 is adhered. In this case, a method in which an adhesive material is applied onto the epoxy resin 17 and then the lid 19 is bonded, or a method in which an adhesive is applied to a position where the epoxy resin 17 comes to the lid 19 and then the lid 19 is bonded, Alternatively, there is a method of bonding the epoxy resin 17 and the lid 19 by heat treatment. If it is necessary to transmit light, the plate-shaped lid 19 is made of a material made of a substance transparent to the light, such as glass or transparent plastic. If it is not necessary to transmit light, a material such as ceramic, glass epoxy, or polyimide can be used. Also, a tape-shaped sheet can be used depending on the application.
【００１２】エポキシ樹脂の硬化を行うための熱処理
は、図１(ｄ)の工程と図１(ｅ)の工程との間で行っても
良いし、ふた１９を接着してから行っても良い。ただ熱
処理後のエポキシ樹脂１７の厚みはワイヤ１６の最高点
より高くする必要がある。次に図１(ｆ)に示すように、
エポキシ樹脂１７の中間地点で基板を切断する。この切
断の方法として、ダイシング装置を用いて行う方法やワ
イヤーソーを用いて行う方法やレーザーや高圧水を用い
て切断する方法がある。また、ダイシングで行う場合、
最初比較的幅の広いブレードを用いて浅く切断しその後
幅の狭いブレードで切断することで、切断面にクラック
が入ることを防止する方法を用いることもできる。The heat treatment for curing the epoxy resin may be performed between the step shown in FIG. 1D and the step shown in FIG. 1E, or may be performed after the lid 19 is bonded. . However, the thickness of the epoxy resin 17 after the heat treatment needs to be higher than the highest point of the wire 16. Next, as shown in FIG.
The substrate is cut at an intermediate point of the epoxy resin 17. Examples of the cutting method include a method using a dicing device, a method using a wire saw, and a method using a laser or high-pressure water. Also, when performing dicing,
It is also possible to use a method in which cracks are prevented from entering the cut surface by first cutting shallow with a relatively wide blade and then cutting with a narrow blade.
【００１３】このようにして、図１(ｇ)に示すように、
ＩＣチップ１５が気体で封止されたＩＣパッケージを得
る。さて、ＩＣパッケージの電気特性の測定方法とし
て、従来と同じく１個のパッケージになった後で測定す
ることはもちろん可能である。そのほかに、図１(ｆ)で
基板を切断する前に測定することもできる。すなわち、
基板の電極に合せてプローブカードを作成しウエハ測定
の時と同じ方法で測定できる。従って多数のＩＣパッケ
ージを１回のプロービングで測定することも可能であ
る。In this manner, as shown in FIG.
An IC package in which the IC chip 15 is sealed with a gas is obtained. Now, as a method of measuring the electrical characteristics of the IC package, it is of course possible to measure the IC package after it has been made into one package as in the conventional case. In addition, the measurement can be performed before cutting the substrate in FIG. That is,
A probe card is prepared in accordance with the electrodes of the substrate, and the measurement can be performed in the same manner as when measuring the wafer. Therefore, it is possible to measure many IC packages by one probing.
【００１４】図２は、図１(ｄ)の平面図を示す。基板２
１内に多数のＩＣチップ２５が搭載されている。ＩＣチ
ップ２５およびワイヤ２６は露出している。ＩＣチップ
の間にはエポキシ樹脂２７が壁状に形成されている。FIG. 2 is a plan view of FIG. 1 (d). Substrate 2
Many IC chips 25 are mounted in one. The IC chip 25 and the wires 26 are exposed. Epoxy resin 27 is formed in a wall shape between the IC chips.
【００１５】図３は、図１(ｆ)の平面図を示す。点線で
示す位置で切断される。エポキシ樹脂３７のほぼ中間位
置で切断される。FIG. 3 shows a plan view of FIG. 1 (f). It is cut at the position shown by the dotted line. It is cut at almost the middle position of the epoxy resin 37.
【００１６】[0016]
【発明の効果】以上、説明したように基板内に多数のＩ
Ｃパッケージを一挙に作り込み、最後に切断して１個1
個のＩＣパッケージにするので、生産性が大幅に向上し
製造費も大幅に低減する。また、切断する前に１枚の基
板になっている時に電気特性を測定できるので、ウエハ
プローバーと同様の思想で多数のＩＣの電気特性を一挙
に測定できることになり、テストに要する費用を大幅に
削減できる。As described above, as described above, a large number of I
Make C package all at once, cut at the end
Since individual IC packages are used, productivity is greatly improved and manufacturing costs are significantly reduced. In addition, since electrical characteristics can be measured when a single substrate is cut before cutting, the electrical characteristics of a large number of ICs can be measured all at once with the same concept as a wafer prober, greatly reducing the cost required for testing. Can be reduced.
【図１】本発明のＩＣパッケージの製造方法を示す図で
ある。FIG. 1 is a diagram showing a method of manufacturing an IC package according to the present invention.
【図２】図１(ｄ)の平面図を示す図である。FIG. 2 is a plan view of FIG. 1 (d).
【図３】図１(ｆ)の平面図を示す図である。FIG. 3 is a diagram showing a plan view of FIG. 1 (f).
【図４】従来のＩＣパッケージを示す図である。FIG. 4 is a diagram showing a conventional IC package.
１１、２１，３１、４１ 半導体基板 １２、４２ 外部電極 １３、２３、３３、４３ 内部電極配線 １５、２５、３５、４５ ＩＣチップ １６、２６、３６、４６ ワイヤ １７、２７、３７ エポキシ樹脂 １８ デスペンサー １９、４９ ふた ４７ 枠 11, 21, 31, 41 Semiconductor substrate 12, 42 External electrode 13, 23, 33, 43 Internal electrode wiring 15, 25, 35, 45 IC chip 16, 26, 36, 46 Wire 17, 27, 37 Epoxy resin 18 Spencer 19, 49 Lid 47 frame
Claims (9)
にＩＣチップを載せてＩＣチップ内の電極と前記内部電
極配線とをワイヤで接続する工程とデスペンサーを用い
てＩＣチップ間にエポキシ樹脂を形成する工程と板状の
ふたを前記エポキシ樹脂に接着する工程と前記エポキシ
樹脂の中間地点で切断する工程とからなることを特徴と
する気密封止ＩＣパッケージの製造方法A step of mounting an IC chip on a substrate having external electrodes and internal electrode wiring, connecting electrodes in the IC chip and the internal electrode wiring with wires, and using an epoxy resin between the IC chips using a dispenser. Forming a hermetic seal, bonding a plate-shaped lid to the epoxy resin, and cutting at an intermediate point of the epoxy resin.
工程を付加することを特徴とする請求項１記載のＩＣパ
ッケージの製造方法2. The method for manufacturing an IC package according to claim 1, further comprising a step of performing a heat treatment to cure the epoxy resin.
する前記基板はガラスエポキシ材料であることを特徴と
する請求項１記載のＩＣパッケージの製造方法3. The method according to claim 1, wherein the substrate having the external electrodes and the internal electrode wiring is made of a glass epoxy material.
する前記基板はセラミック材料であることを特徴とする
請求項１記載のＩＣパッケージの製造方法4. The method according to claim 1, wherein the substrate having the external electrodes and the internal electrode wiring is made of a ceramic material.
を特徴とする請求項１記載のＩＣパッケージの製造方法5. The method according to claim 1, wherein the plate-like lid is a glass plate.
ことを特徴とする請求項１記載のＩＣパッケージの製造
方法6. The method according to claim 1, wherein the plate-like lid is a ceramic plate.
あることを特徴とする請求項１記載のＩＣパッケージの
製造方法7. The method according to claim 1, wherein the plate-like lid is a tape-like sheet.
ジの電気特性を基板全体を用いて測定する工程を含むこ
とを特徴とする請求項１記載のＩＣパッケージの製造方
法8. The method for manufacturing an IC package according to claim 1, further comprising a step of measuring electric characteristics of the IC package using the entire substrate before cutting the substrate.
性を測定することを特徴とする特許請求の範囲第８項記
載のＩＣパッケージの製造方法9. The method for manufacturing an IC package according to claim 8, wherein electric characteristics are measured using a probe card-shaped jig.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001182443A JP2002373954A (en) | 2001-06-15 | 2001-06-15 | Method for manufacturing hermetically sealed ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001182443A JP2002373954A (en) | 2001-06-15 | 2001-06-15 | Method for manufacturing hermetically sealed ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002373954A true JP2002373954A (en) | 2002-12-26 |
Family
ID=19022542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001182443A Pending JP2002373954A (en) | 2001-06-15 | 2001-06-15 | Method for manufacturing hermetically sealed ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002373954A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010177674A (en) * | 2010-02-09 | 2010-08-12 | Kyocera Corp | Method of manufacturing electronic device |
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2001
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010177674A (en) * | 2010-02-09 | 2010-08-12 | Kyocera Corp | Method of manufacturing electronic device |
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