JP2002373951A - Method for manufacturing hermetically sealed ic package - Google Patents
Method for manufacturing hermetically sealed ic packageInfo
- Publication number
- JP2002373951A JP2002373951A JP2001182440A JP2001182440A JP2002373951A JP 2002373951 A JP2002373951 A JP 2002373951A JP 2001182440 A JP2001182440 A JP 2001182440A JP 2001182440 A JP2001182440 A JP 2001182440A JP 2002373951 A JP2002373951 A JP 2002373951A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- manufacturing
- substrate
- photosensitive material
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000000126 substance Substances 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims description 28
- 239000011521 glass Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 239000000523 sample Substances 0.000 claims description 2
- 229910010293 ceramic material Inorganic materials 0.000 claims 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は気密封止ICパッケ
ージの製造方法に関する。The present invention relates to a method for manufacturing a hermetically sealed IC package.
【0002】[0002]
【従来の技術】これまでの気密封止ICパッケージは図
に示すように、枠47を有する個片の基板41にICチ
ップ45をのせワイヤ46をはり、枠47にあわせるよ
うに板状のふた49をのせていた。2. Description of the Related Art As shown in FIG. 1, a conventional hermetically sealed IC package has an IC chip 45 mounted on an individual substrate 41 having a frame 47 and a wire 46 mounted thereon. 49 was on it.
【0003】[0003]
【発明が解決しようとする課題】従来の気密封止ICパ
ッケージは、1個1個別別に製造されているため生産性
が著しく低く、それゆえ非常に高価なものとなってい
た。The conventional hermetically sealed IC packages are manufactured individually and individually, resulting in extremely low productivity and, therefore, very expensive.
【0004】[0004]
【課題を解決するための手段】上記の問題点を解決する
ために、本発明は複数以上のICチップを載せられる基
板を用い、感光性物質をICチップ間に厚く形成し、板
状のふたを被せた後で、基板を切断することにより1個
1個のICパッケージにする。その際、ワイヤ領域およ
び基板内の電極配線を保護するために露出すべきICチ
ップの表面以外を感光性物質で被う。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention uses a substrate on which a plurality of IC chips are mounted, a photosensitive substance is formed thick between the IC chips, and a plate-shaped lid is provided. And then cut the board to remove
Make one IC package. At this time, a portion other than the surface of the IC chip to be exposed to protect the wire region and the electrode wiring in the substrate is covered with a photosensitive material.
【0005】[0005]
【発明の実施の形態】本発明は、ICチップの表面を空
気などの気体で取り囲んだ気体封止型のパッケージの製
造方法に関するものである。以下にこの発明の実施例を
図面に基づいて説明する。図1は、本発明の製造方法の
工程順を示すICパッケージの断面図を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a method for manufacturing a gas-sealed package in which the surface of an IC chip is surrounded by a gas such as air. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of an IC package showing a process sequence of a manufacturing method of the present invention.
【0006】図1(a)に示すように、外部電極12と内
部電極配線13を有する基板11が用意される。この基
板内には複数以上のたくさんのICチップが搭載され、
最終的に個片にされる。従って基板のサイズは大型であ
り、外部電極12も内部電極配線13も繰り返しのパタ
ーンとなっている。基板11の材料は、セラミックやガ
ラスエポキシやポリイミドやガラスなどが挙げられる。As shown in FIG. 1A, a substrate 11 having external electrodes 12 and internal electrode wirings 13 is prepared. Many or more IC chips are mounted on this board,
Finally, it is singulated. Therefore, the size of the substrate is large, and the external electrode 12 and the internal electrode wiring 13 have a repeating pattern. The material of the substrate 11 includes ceramic, glass epoxy, polyimide, glass, and the like.
【0007】次に図1(b)に示すように、ICチップ1
5を内部電極配線の所望の位置に接着する。尚、ICチ
ップ15の接着する位置には、内部電極配線13はなく
て良い場合もある。たとえば、ICチップの表面をでき
るだけ低くする必要がある場合や、ICチップを電気的
に導通する必要がない場合や、ICチップを放熱する必
要があまりない場合などである。次にICチップ15の
表面の電極と内部電極配線とをワイヤ16で接続する。
このワイヤの材料として、金(Au)、金合金、アルミニ
ウム(Al)、アルミニウム合金、銅(Cu)、銅合金など
の金属が使われる。[0007] Next, as shown in FIG.
5 is bonded to a desired position of the internal electrode wiring. In some cases, the internal electrode wiring 13 may not be provided at the position where the IC chip 15 is bonded. For example, there is a case where the surface of the IC chip needs to be as low as possible, a case where there is no need to electrically conduct the IC chip, and a case where there is little need to radiate the heat of the IC chip. Next, the electrodes on the surface of the IC chip 15 and the internal electrode wiring are connected by wires 16.
As a material of the wire, a metal such as gold (Au), a gold alloy, aluminum (Al), an aluminum alloy, copper (Cu), or a copper alloy is used.
【0008】次に図1(c)に示すように感光性物質17
を塗布する。この感光性物質17は塗布する時には液状
なので、ICチップ15を移動させたり、ICチップ1
5にダメッジを与えたり、ワイヤ16を曲げたり、ワイ
ヤにダメッジを与えたり、ワイヤと電極配線およびIC
との接着場所にダメッジを与えたりすることはない。こ
の感光性物質17として、ネガレジスト、ポジレジス
ト、感光性ポリイミドなどがある。また、塗布する感光
性物質17の厚みは、最終的にワイヤ16の最も高い所
より高くなるように設計されなければならない。Next, as shown in FIG.
Is applied. Since the photosensitive substance 17 is in a liquid state when applied, the IC chip 15 is moved or the IC chip 1 is moved.
5, wire 16 is bent, wire is damaged, wire and electrode wiring and IC
There is no damaging to the place where it adheres. The photosensitive material 17 includes a negative resist, a positive resist, and a photosensitive polyimide. Also, the thickness of the photosensitive material 17 to be applied must be designed so as to be finally higher than the highest point of the wire 16.
【0009】次に図1(d)に示すように、ICチップ1
5の露出すべき領域のみが露出されるように作成された
マスク18を用いて光をあてる。ネガ型の感光性物質で
は光があたる所が硬化する。ポジ型の場合は、逆に光が
あたらない所が硬化する。次に図1(e)に示すように、
現像することにより、ICチップ15の露出すべき領域
のある所の感光性物質17がなくなり、それ以外の領域
は厚い壁状の感光性物質17が形成される。これを熱処
理することにより、感光性物質17はさらに強固にな
る。この熱処理により感光性物質17は縮小する場合が
あるが、縮小して高さが低くなってもワイヤ16の最高
点よりも感光性物質17を高くしワイヤが露出しなよう
にしなければならない。また、感光性物質17と基板1
1内の内部電極配線やワイヤとの位置関係を余り考慮す
る必要がないためICチップ15間の距離を少なくでき
る。このことはICパッケージを小さくできることにつ
ながる。Next, as shown in FIG.
Light is applied using a mask 18 formed so that only the region 5 to be exposed is exposed. In the case of a negative-type photosensitive material, a portion exposed to light cures. In the case of the positive type, on the other hand, the area where no light is irradiated cures. Next, as shown in FIG.
By the development, the photosensitive material 17 in the area where the IC chip 15 is to be exposed is eliminated, and in the other area, the thick wall-shaped photosensitive substance 17 is formed. By subjecting this to a heat treatment, the photosensitive substance 17 is further strengthened. Although the photosensitive material 17 may be reduced by this heat treatment, the photosensitive material 17 must be higher than the highest point of the wire 16 so that the wire is not exposed even when the photosensitive material 17 is reduced and the height is reduced. Also, the photosensitive substance 17 and the substrate 1
The distance between the IC chips 15 can be reduced because there is no need to consider the positional relationship with the internal electrode wirings and wires in the device 1. This leads to a smaller IC package.
【0010】次に図1(f)に示すように、板状のふた1
9を接着する。この場合、感光性物質17の上に接着材
料を付着してからふた19を接着する方法、あるいはふ
た19の方に感光性物質17が来る位置に接着材を塗布
してからふた19を接着する方法、あるいは感光性物質
17とふた19を熱処理で接着する方法などがある。こ
の板状のふた19として、光を通すことが必要であれば
ガラスや透明プラスチックなどのその光に透明な物質か
らなる材料にする。光を通す必要がなければ、セラミッ
クやガラスエポキシやポリイミドなどの材料を用いるこ
とができる。またテープ状のシートでも用途によって使
うこともできる。Next, as shown in FIG.
9 is adhered. In this case, a method of bonding the lid 19 after attaching an adhesive material on the photosensitive substance 17 or applying an adhesive to a position where the photosensitive substance 17 comes to the lid 19 and then bonding the lid 19 is applied. Or a method of bonding the photosensitive substance 17 and the lid 19 by heat treatment. If it is necessary to transmit light, the plate-shaped lid 19 is made of a material made of a substance transparent to the light, such as glass or transparent plastic. If it is not necessary to transmit light, a material such as ceramic, glass epoxy, or polyimide can be used. Also, a tape-shaped sheet can be used depending on the application.
【0011】次に図1(g)に示すように、感光性物質1
7の中間地点で基板を切断する。この切断の方法とし
て、ダイシング装置を用いて行う方法やワイヤーソーを
用いて行う方法やレーザーや高圧水を用いて切断する方
法がある。また、ダイシングで行う場合、最初比較的幅
の広いブレードを用いて浅く切断しその後幅の狭いブレ
ードで切断することで、切断面にクラックが入ることを
防止する方法を用いることもできる。このようにして、
図1(h)に示すように、ICチップ15が気体で封止さ
れたICパッケージを得る。Next, as shown in FIG.
The substrate is cut at the midpoint of 7. Examples of the cutting method include a method using a dicing device, a method using a wire saw, and a method using a laser or high-pressure water. Further, in the case of dicing, a method of preventing a crack from entering a cut surface by first cutting shallowly with a relatively wide blade and then cutting with a narrow blade can be used. In this way,
As shown in FIG. 1H, an IC package in which the IC chip 15 is sealed with a gas is obtained.
【0012】さて、ICパッケージの電気特性の測定方
法として、従来と同じく1個のパッケージになった後で
測定することはもちろん可能である。そのほかに、図1
(g)で基板を切断する前に測定することもできる。すな
わち、基板の電極に合せてプローブカードを作成しウエ
ハ測定の時と同じ方法で測定できる。従って多数のIC
パッケージを1回のプロービングで測定することも可能
である。Now, as a method of measuring the electrical characteristics of an IC package, it is of course possible to measure the electrical characteristics of a single package after the package has been formed as in the conventional case. In addition, Figure 1
It can also be measured before cutting the substrate in (g). That is, a probe card can be prepared in accordance with the electrodes of the substrate, and measurement can be performed in the same manner as in the case of wafer measurement. Therefore many ICs
It is also possible to measure the package in one probing.
【0013】図2は、図1(e)の平面図を示す。基板2
1内に多数のICチップ25が搭載されている。ICチ
ップ25の表面の1部のみが露出している。それ以外の
領域は感光性物質27で被われている。特にICチップ
の電極やワイヤや基板電極配線23もは感光性物質27
で被われている。写真食刻法を用いているので感光性物
質は精度良くパターニングされている。図3は、図1
(g)の平面図を示す。点線で示す位置で切断される。感
光性物質37のほぼ中間位置で切断される。尚、イメー
ジセンサーやCCDなどの撮像素子はICチップのセン
サーの一部のみが光にあたれば良いので、本発明を最も
有効に利用できる。FIG. 2 shows a plan view of FIG. Substrate 2
Many IC chips 25 are mounted in one. Only a part of the surface of the IC chip 25 is exposed. The other area is covered with the photosensitive substance 27. In particular, the electrodes and wires of the IC chip and the wiring 23 of the substrate electrode are also made of a photosensitive substance 27.
It is covered with. Since the photolithography method is used, the photosensitive material is accurately patterned. FIG.
(g) shows a plan view. It is cut at the position shown by the dotted line. The photosensitive material 37 is cut at a substantially intermediate position. Note that the image sensor such as an image sensor or a CCD only needs to partially expose the sensor of the IC chip to light, so that the present invention can be used most effectively.
【0014】[0014]
【発明の効果】以上、説明したように基板内に多数のI
Cパッケージを一挙に作り込み、最後に切断して1個1
個のICパッケージにするので、生産性が大幅に向上し
製造費も大幅に低減する。ICチップの表面の露出すべ
き領域以外の領域は感光性物質で被われている。特にI
Cチップの電極やワイヤと接続している領域やワイヤお
よび基板内の内部電極配線は感光性物質で被われてい
て、機械的にかつ湿度などの環境から保護されているた
め従来に比較し大幅に信頼性および品質が向上してい
る。さらにICパッケージに切断する領域と内部電極配
線の間隔を考慮する必要がないためICパッケージ間の
距離を狭くできる。従ってICパッケージを小さくする
ことができるとともに1枚の基板から取ることができる
ICパッケージの数を増やすことができる。さらに、感
光性物質の厚みは精密に制御できるためサイズの正確な
ICパッケージができる。また、切断する前に1枚の基
板になっている時に電気特性を測定できるので、ウエハ
プローバーと同様の思想で多数のICの電気特性を一挙
に測定できることになり、テストに要する費用を大幅に
削減できる。As described above, as described above, a large number of I
Make C package all at once, cut at the end
Since individual IC packages are used, productivity is greatly improved and manufacturing costs are significantly reduced. The area other than the area to be exposed on the surface of the IC chip is covered with a photosensitive material. Especially I
The area connected to the electrodes and wires of the C-chip and the wires and the internal electrode wiring inside the board are covered with a photosensitive material and are mechanically protected from the environment such as humidity. Reliability and quality have improved. Further, since there is no need to consider the interval between the region to be cut into the IC package and the internal electrode wiring, the distance between the IC packages can be reduced. Therefore, the size of the IC package can be reduced, and the number of IC packages that can be obtained from one substrate can be increased. Further, since the thickness of the photosensitive material can be precisely controlled, an IC package having an accurate size can be obtained. In addition, since electrical characteristics can be measured when a single substrate is cut before cutting, the electrical characteristics of a large number of ICs can be measured all at once with the same concept as a wafer prober, greatly reducing the cost required for testing. Can be reduced.
【図1】本発明のICパッケージの製造方法を示す図で
ある。FIG. 1 is a diagram showing a method of manufacturing an IC package according to the present invention.
【図2】図1(e)の平面図を示す図である。FIG. 2 is a plan view of FIG. 1 (e).
【図3】図1(g)の平面図を示す図である。FIG. 3 is a diagram showing a plan view of FIG. 1 (g).
【図4】従来のICパッケージを示す図である。FIG. 4 is a diagram showing a conventional IC package.
11、21,31、41 半導体基板 12,42 外部電極 13,23,33,43 内部電極配線 15、25,35,45 ICチップ 16、26、36、46 ワイヤ 17、27、37 感光性物質 18 マスク 19、49 ふた 47 枠 11, 21, 31, 41 Semiconductor substrate 12, 42 External electrode 13, 23, 33, 43 Internal electrode wiring 15, 25, 35, 45 IC chip 16, 26, 36, 46 Wire 17, 27, 37 Photosensitive material 18 Mask 19, 49 Lid 47 frame
Claims (10)
にICチップを載せてICチップ内の電極と前記内部電
極配線とをワイヤで接続する工程と感光性物質を塗布す
る工程と写真食刻法を用いてICチップの表面で露出す
べき領域を除いた領域に感光性物質を形成する工程と板
状のふたを前記感光性物質の厚膜に接着する工程と前記
感光性物質の中間地点で切断する工程とからなることを
特徴とする気密封止ICパッケージの製造方法1. A step of mounting an IC chip on a substrate having external electrodes and internal electrode wiring, connecting an electrode in the IC chip to the internal electrode wiring with a wire, applying a photosensitive substance, and performing photolithography. Forming a photosensitive material in a region other than a region to be exposed on the surface of an IC chip by using a method, bonding a plate-shaped lid to a thick film of the photosensitive material, and an intermediate point of the photosensitive material And a method of manufacturing a hermetically sealed IC package.
にICチップを載せてICチップ内の電極と前記内部電
極配線とをワイヤで接続する工程と感光性物質を塗布す
る工程と写真食刻法を用いてICチップの表面で露出す
べき領域を除いた領域に感光性物質を形成する工程と熱
処理を行い前記感光性物質を硬化させる工程と板状のふ
たを前記感光性物質の厚膜に接着する工程と前記感光性
物質の中間地点で切断する工程とからなることを特徴と
する気密封止ICパッケージの製造方法2. A step of mounting an IC chip on a substrate having external electrodes and internal electrode wirings, connecting electrodes in the IC chip and the internal electrode wirings with wires, applying a photosensitive substance, and performing photolithography. Forming a photosensitive material in a region excluding a region to be exposed on the surface of the IC chip by using a method, performing a heat treatment to cure the photosensitive material, and removing a plate-shaped lid from the photosensitive material thick film And a step of cutting at an intermediate point of the photosensitive material.
はガラスエポキシ材料であることを特徴とする請求項1
または2記載のICパッケージの製造方法3. The substrate having an external electrode and an internal electrode wiring is made of a glass epoxy material.
Or the method for manufacturing an IC package according to 2.
はセラミック材料であることを特徴とする請求項1また
は2記載のICパッケージの製造方法4. The method for manufacturing an IC package according to claim 1, wherein the substrate having the external electrodes and the internal electrode wiring is made of a ceramic material.
徴とする請求項1または2記載のICパッケージの製造
方法5. The method for manufacturing an IC package according to claim 1, wherein the plate-like lid is a glass plate.
を特徴とする請求項1または2記載のICパッケージの
製造方法6. The method for manufacturing an IC package according to claim 1, wherein the plate-shaped lid is a ceramic plate.
ことを特徴とする請求項1または2記載のICパッケー
ジの製造方法7. The method for manufacturing an IC package according to claim 1, wherein the plate-like lid is a tape-like sheet.
域はICチップの電極でワイヤで接続する領域を含むこ
とを特徴とする請求項1または2記載のICパッケージ
の製造方法8. The method for manufacturing an IC package according to claim 1, wherein the area covered with the photosensitive material on the surface of the IC chip includes an area connected to the electrode of the IC chip by a wire.
電気特性を基板全体を用いて測定する工程を含むことを
特徴とする請求項1または2記載のICパッケージの製
造方法9. The method for manufacturing an IC package according to claim 1, further comprising a step of measuring electric characteristics of the IC package using the whole substrate before cutting the substrate.
特性を測定することを特徴とする請求項9記載のICパ
ッケージの製造方法10. The method for manufacturing an IC package according to claim 9, wherein the electrical characteristics are measured using a probe card-shaped jig.
Priority Applications (1)
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JP2001182440A JP2002373951A (en) | 2001-06-15 | 2001-06-15 | Method for manufacturing hermetically sealed ic package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001182440A JP2002373951A (en) | 2001-06-15 | 2001-06-15 | Method for manufacturing hermetically sealed ic package |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2002373951A true JP2002373951A (en) | 2002-12-26 |
Family
ID=19022539
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2001182440A Pending JP2002373951A (en) | 2001-06-15 | 2001-06-15 | Method for manufacturing hermetically sealed ic package |
Country Status (1)
Country | Link |
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JP (1) | JP2002373951A (en) |
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2001
- 2001-06-15 JP JP2001182440A patent/JP2002373951A/en active Pending
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