JP2002100875A - Printed wiring board and capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board which incorporates capacitors with which appropriate connection is provided. SOLUTION: Chip capacitors 20 are housed in a core substrate 30. The chip capacitors 20 is electrically connected to first the second electrodes 21 and 22 coated with a copper plating film 29 through via holes 46 plated with copper. Thanks to the copper plating film 29, the surfaces of the first and second electrodes 21 and 22 are smooth and no resin residue is left out when a non- through hole 43 is opened at a connection layer 40, for raised connection reliability between the via holes 46 and the chip capacitors 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board on which electronic components such as IC chips are mounted, and more particularly to a printed wiring board having a built-in capacitor.

[0002]

2. Description of the Related Art At present, in a printed wiring board for a package substrate, a chip capacitor is sometimes mounted on a surface in order to reduce a loop inductance from a power supply to a power supply / ground of an IC chip. However, the reactance of the loop inductance depends on the frequency. Therefore, I
With an increase in the driving frequency of the C chip, even if a chip capacitor is mounted, the reactance of the loop inductance cannot be reduced as much as required in performance.

For this reason, the present inventor has an idea of accommodating a chip capacitor in a printed wiring board. As a technique for embedding a capacitor in a substrate, see Japanese Unexamined Patent Publication No.
6472, JP-A-7-263619, JP-A-10-
No. 256429, JP-A-11-45555, JP-A-1
1-112678 and JP-A-11-31868.

Japanese Patent Application Laid-Open No. 6-326472 discloses a technique for embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, power supply noise is reduced, and a space for mounting a chip capacitor is not required, and the size of the insulating substrate can be reduced. In addition, Japanese Patent Application Laid-Open
No. 263619 discloses a technique for embedding a capacitor in a substrate made of ceramic, alumina, or the like. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.

[0005]

However, the above-described technique cannot shorten the distance of the capacitor from the IC chip so much, and in the higher frequency region of the IC chip, the inductance is reduced as required at present. I couldn't do that. In particular, in a multilayer build-up wiring board made of resin, a capacitor made of ceramic,
Due to the difference in the coefficient of thermal expansion between the core substrate made of resin and the interlayer resin insulation layer, disconnection between the terminal of the chip capacitor and the via hole, peeling between the chip capacitor and the interlayer resin insulation layer, cracks in the interlayer resin insulation layer And high reliability could not be achieved over a long period of time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a printed wiring board capable of reducing loop inductance.

Another object of the present invention is to provide a printed wiring board which incorporates a capacitor and which can achieve high reliability and a capacitor.

[0008]

According to one aspect of the present invention, there is provided a printed wiring board comprising a resin insulating layer and a conductive circuit laminated on a core substrate, wherein a capacitor is provided in the core substrate. Is a technical feature.

A circuit formed by a build-up method in which an interlayer resin insulating layer is provided on a core substrate, a via hole or a through hole is formed in the interlayer resin insulating layer, and a conductive circuit as a conductive layer is formed. I have. They include
Either a semi-additive method or a full-additive method can be used.

According to the first aspect, since the capacitor is arranged in the printed wiring board, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. Further, since the capacitor is accommodated in the thick core substrate, the printed wiring board does not become thick even if the interlayer resin insulating layer and the conductive circuit are laminated on the core substrate.

It is desirable to fill the void with a resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if a stress originating from the capacitor is generated, the stress can be reduced by the filled resin. The resin also has the effect of reducing adhesion and migration between the capacitor and the core substrate.

According to a second aspect of the present invention, there is provided a printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate, wherein at least a part of a coating layer of an electrode of a chip capacitor is exposed. And electrically connecting the electrodes exposed from the coating layer by plating.

According to the second and third aspects, at least a part of the electrode of the chip capacitor is exposed from the coating layer and housed in the printed wiring board, and the electrode exposed from the coating layer is electrically connected by plating. At this time, it is desirable that the metal exposed from the coating layer is a metal whose main component is Cu. The reason for this is that the connectivity when plating is formed on the exposed metal is increased, there is no difference in electrical characteristics, and the connection resistance can be reduced.

According to a fourth aspect of the present invention, there is provided a printed wiring board formed by laminating a resin insulating layer and a conductive circuit on a core substrate, wherein a metal film is formed on an electrode of a chip capacitor and housed in the printed wiring board. A technical feature is that an electrical connection is made to the electrode on which the metal film is formed by plating.

In the fourth and fifth aspects, the electrodes of the chip capacitor on which the metal film is formed are electrically connected to the via holes formed by plating. Here, the electrode of the chip capacitor is made of metallized and has irregularities on the surface, but the surface is smoothed by the metal film and the via hole is formed, so when the through hole is formed in the resin coated on the electrode As a result, no resin residue remains, and the connection reliability between the via hole and the electrode can be improved. Furthermore, since the via hole is formed by plating on the plated electrode, the connectivity between the electrode and the via hole is high, and even if a heat cycle test is performed, disconnection between the electrode and the via hole may occur. Absent.

It is desirable that the metal film of the electrode of the capacitor is provided with any one of copper, nickel and noble metal. This is because a layer of tin or zinc in the built-in capacitor easily induces migration at a connection portion with the via hole. Therefore, occurrence of migration can be prevented.

According to the sixth aspect of the present invention, since a chip capacitor having an electrode formed inside the outer edge is used, a large external electrode can be obtained even when conduction is established through a via hole, and the allowable range of alignment is widened. Disappears.

In the seventh aspect, since the chip capacitors having the electrodes formed in a matrix are used, it becomes easy to accommodate the large-sized chip capacitors in the core substrate. Further, even after various thermal histories, the printed wiring board is less likely to warp.

According to the present invention, a plurality of chip capacitors for multi-cavity are connected and used as the capacitor.
That is, since a large-sized chip capacitor is used, a large-capacity chip capacitor can be used. further,
Even after various thermal histories, the printed wiring board is less likely to warp.

A ninth aspect of the present invention is a printed wiring board formed by laminating a resin insulating layer and a conductive circuit on a core substrate, wherein a capacitor is accommodated in the core substrate, and a printed circuit board is provided on a surface of the printed wiring board. A technical feature is that the capacitor is mounted.

In the ninth aspect, a capacitor is provided on the surface in addition to the capacitor housed in the substrate. Since the capacitor is housed in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance is reduced, and power can be supplied instantaneously. Because a capacitor is provided, a large-capacity capacitor can be attached.
Large power can be easily supplied to the IC chip.

According to the tenth aspect, since the capacitance of the capacitor on the surface is larger than the capacitance of the capacitor in the inner layer,
There is no shortage of power supply in the high frequency range, and the desired IC
The operation of the chip is ensured.

According to the eleventh aspect, since the inductance of the capacitor on the surface is equal to or greater than the inductance of the capacitor in the inner layer, there is no shortage of power supply in a high frequency region, and a desired operation of the IC chip is ensured.

Further, the surface of the chip capacitor may be subjected to a roughening treatment. As a result, the adhesion between the ceramic chip capacitor and the resin adhesive layer and the interlayer resin insulating layer is high, and the adhesive layer and the interlayer resin insulating layer are peeled off at the interface even when the heat cycle test is performed. There is no.

According to a twelfth aspect of the present invention, there is provided a capacitor for incorporating a printed wiring board, which is characterized in that a surface of a metallized electrode of a chip capacitor is coated with a copper plating film.

In the twelfth aspect, since a metal film is formed on the electrode of the chip capacitor and the surface is smoothed, when a through hole is formed in the resin accommodated in the printed wiring board and coated on the electrode, Since no resin residue remains, the connection reliability between the via hole and the electrode can be improved.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 6 shows a cross section of the printed wiring board 10, and FIG. 7 shows a state where the IC chip 90 is mounted on the printed wiring board 10 shown in FIG.

As shown in FIG. 6, the printed wiring board 10
The chip capacitor 20 includes a core substrate 30 that houses the chip capacitor 20, and an interlayer resin insulation layer 60 that forms the build-up layers 80A and 80B. Core substrate 30
Are a housing layer 31 for housing the capacitor 20 and a connection layer 40
Consists of Via holes 46 and conductor circuits 48 are formed in the connection layer 40, and via holes 66 and conductor circuits 68 are formed in the interlayer resin insulation layer 60. In the present embodiment, the build-up layer has one interlayer resin insulation layer 6.
However, the build-up layer may include a plurality of interlayer resin insulation layers.

The chip capacitor 20 includes a first electrode 21 and a second electrode 22 as shown in FIG.
A first conductive film 24 connected to the first electrode 21 side and a second conductive film 25 connected to the second electrode 22 side. Are arranged facing each other. The first electrode 21 and the second electrode 22
The metal layer 26 made of copper metallization is coated with
8 are covered. In the present embodiment, the first electrode 21 and the second electrode 22 are connected via via holes 46 made of plating. In the printed wiring board of the first embodiment, FIG.
As shown in (B), the metal layer 26 is exposed from the coating layer 28 on the upper surfaces of the first electrode 21 and the second electrode 22 of the chip capacitor 20. For this reason, as shown in FIG.
The connectivity between the first and second electrodes 21 and 22 and the via holes 46 made of plating is increased, and the connection resistance can be reduced.

Further, a roughened layer 23a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. Therefore, the adhesion between the chip capacitor 20 made of ceramic and the adhesive layer 40 made of resin is high, and the adhesive layer 40 does not peel off at the interface even when the heat cycle test is performed. The roughened layer 23a can be formed by polishing the surface of the chip capacitor 20 after firing, or by performing a roughening process before firing.

As shown in FIG. 7, the upper build-up layer 8
Bumps 76 for connecting to pads 92S1, 92S2, 92P1, and 92P2 of IC chip 90 are formed in via hole 66 of 0A. On the other hand, pads 96S1, 96S2, 96P1, 96P2 of the daughter board 94 are provided in the via holes 66 of the lower buildup layer 80B.
A bump 76 is provided for connection to the substrate. A through hole 36 is formed in the core substrate 30.

Signal pad 92S2 of IC chip 90
Are connected to the signal pad 96S2 of the daughter board 94 via the bump 76, the conductor circuit 68, the via hole 66, the through hole 36, the via hole 66, and the bump 76. On the other hand, the signal pad 9 of the IC chip 90
2S1 is connected to a signal pad 96S1 of the daughter board 94 via a bump 76-via hole 66-through hole 36-via hole 66-bump 76.

Power supply pad 92P1 of IC chip 90
Is connected to the first electrode 21 of the chip capacitor 20 via the bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P1 of the daughter board 94 is connected to the bump 76-via hole 66.
-Through hole 36-Conductor circuit 48-Via hole 46
To the first electrode 21 of the chip capacitor 20.

Power supply pad 92P2 of IC chip 90
Is connected to the second electrode 22 of the chip capacitor 20 via a bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P2 of the daughter board 94 is connected to the bump 76 and the via hole 66.
-Through hole 36-Conductor circuit 48-Via hole 46
Is connected to the second electrode 22 of the chip capacitor 20 via the.

In the printed wiring board 10 of this embodiment, I
Since the chip capacitor 20 is disposed immediately below the C chip 90, the distance between the IC chip and the capacitor is shortened, so that power can be instantaneously supplied to the IC chip. That is, the loop length that determines the loop inductance can be reduced.

Further, a through hole 36 is provided between the chip capacitors 20 so that a signal line does not pass through the chip capacitor 20. For this reason, it is possible to prevent reflection due to impedance discontinuity due to the high dielectric substance that occurs when passing through the capacitor, and propagation delay due to passage through the high dielectric substance.

An external board (daughter board) 94 connected to the back side of the printed wiring board and the first terminal 21 and the second terminal 22 of the capacitor 20 are connected to via holes formed in the connection layer 40 on the IC chip side. 46 and through a through hole 36 formed in the core substrate. That is, since a through hole is formed in the housing layer 31 having the core material and which is difficult to process, and the terminal of the capacitor is not directly connected to the external substrate, the connection reliability can be improved.

In this embodiment, as shown in FIG. 6, the lower surface of the through hole 37 of the core substrate 30 and the chip capacitor 20
An adhesive 32 is interposed therebetween, and a resin filler 32 a is filled between the side surface of the through hole 37 and the chip capacitor 20. Here, the thermal expansion coefficients of the adhesive 32 and the resin filler 32a are set to be smaller than those of the core substrate 30 and the adhesive layer 40, that is, close to the chip capacitor 20 made of ceramic. Therefore, in the heat cycle test, the core substrate and the adhesive layer 40 and the chip capacitor 20
Even if internal stress is generated due to the difference in the coefficient of thermal expansion between the core substrate and the adhesive layer 40, cracks, peeling, and the like hardly occur, and high reliability can be achieved. In addition, the occurrence of migration can be prevented.

The manufacturing process of the printed wiring board according to the first embodiment will be described with reference to FIGS. First, a through hole 37 for accommodating a chip capacitor is formed in a laminated plate 31α formed by laminating four prepregs 35 in which a core material is impregnated with an epoxy resin, and a laminated plate 31β formed by laminating two prepregs 35 is formed. Prepare (FIG. 1A). Here, as the prepreg, a material containing a reinforcing material such as BT, phenol resin or glass cloth other than epoxy can be used. However, a substrate made of ceramic, AIN, or the like cannot be used as the core substrate. This is because the substrate has poor external formability, and may not be able to accommodate a capacitor, and may cause voids even when filled with resin. Next, after stacking the laminated plate 31α and the laminated plate 31β to form the accommodation layer 31, the upper surfaces of the first and second electrodes 21 and 22 are formed in the through holes 37 as described above with reference to FIG. The chip capacitor 20 from which the coating 28 has been peeled off is accommodated (FIG. 1B). Here, the through hole 37 and the chip capacitor 2
It is preferable that an adhesive 32 is interposed between the first and second adhesive layers.
The melting point of the resin and the interlayer resin insulating layer used in the present application is 300 ° C. or less, and when a temperature of 350 ° C. or more is applied, the resin is melted, softened, or carbonized.

Next, a resin film (connecting layer) 40α is laminated on both sides of a laminated layer composed of the laminated plate 31α and the laminated plate 31β for accommodating the chip capacitor 20 (FIG. 1).
(C)). And it presses from both surfaces and makes a surface flat. Thereafter, the core substrate 30 including the housing layer 31 housing the chip capacitor 20 and the connection layer 40 is formed by heating and curing (FIG. 1D). In the present embodiment, the housing layer 31 housing the capacitor 20 and the connection layer 40
The pressure is applied to both surfaces to form the core substrate 30, so that the surface is flattened. Thereby, in a process described later, the interlayer resin insulating layer 6 is formed so as to have high reliability.
0 and the conductor circuit 68 can be stacked.

It is preferable that the side surface of the through hole 37 of the core substrate is filled with the resin filler 32a to improve the airtightness. Further, here, the resin film 40α is laminated without using a metal layer, but a resin film (RCC) having a metal layer disposed on one side may be used. That is, a double-sided plate, a single-sided plate, a resin plate having no metal film, and a resin film can be used.

Next, a through hole 33 of 300 to 500 μm for a through hole is formed in the interlayer resin insulating layer 40, the core substrate and the interlayer resin insulating layer 40 by a drill (FIG. 2).
(A)). Then, the first electrode 21 and the second electrode 21 of the chip capacitor 20 are applied to the interlayer resin insulation layer 40 on the upper surface side by a CO2 laser, a YAG laser, an excimer laser, or a UV laser.
A non-through hole 43 is formed to reach the electrode 22 (see FIG. 2).
(B)). In some cases, an area mask having a through hole may be placed in correspondence with the position of the non-through hole to perform the area processing with a laser. Further, in the case where via holes having different sizes and diameters are formed, they may be formed by a mixed laser.

Thereafter, a desmear process is performed. Continued
After applying the palladium catalyst on the surface, the core substrate 30 is immersed in the electroless plating solution to uniformly deposit the electroless copper plating film 44 (FIG. 2C). A roughened layer can be formed on the surface of the electroless copper plating film 44. The roughened layer has Ra (average roughness height) = 0.01 to 5 μm. Particularly desirable is a range of 0.5 to 3 μm.

Then, a photosensitive dry film is stuck on the surface of the electroless plating film 44, a mask is placed, exposure and development are performed, and a resist 51 having a predetermined pattern is formed (FIG. 3A). Here, electroless plating is used, but it is also possible to form a metal film of copper, nickel, or the like by sputtering. Sputtering is disadvantageous in cost, but has the advantage of improving the adhesion to the resin. And
The core substrate 30 is immersed in the electrolytic plating solution, and a current is passed through the electroless plating film 44 to deposit the electrolytic copper plating film 45 (FIG. 3B). Then, the resist 51 is replaced with 5% KOH
Then, the electroless plating film 44 under the resist 51 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, the non-through hole 43 of the interlayer resin insulating layer 40 is provided with the via hole 46, and the surface of the connection layer 40 is provided. In the conductor circuit 48, a through hole 36 is formed in the through hole 33 of the core substrate 30 (FIG. 3C).

A roughened layer is provided on the surface of the conductor layer of the conductor circuit 48, the via hole 46, and the through hole 36. The roughened layer is formed by an oxidation (blackening) -reduction treatment, an electroless plating film of an alloy made of Cu-Ni-P, or an etching treatment of an etching solution containing a cupric complex and an organic acid salt. The roughened layer has Ra (average roughness height) = 0.01 to
5 μm. Particularly desirable is a range of 0.5 to 3 μm. Although the roughened layer is formed here, it is also possible to directly fill the resin and attach a resin film as described later without forming the roughened layer.

Subsequently, the resin layer 3 is formed in the through hole 36.
8 is filled. As the resin layer, either a resin having no conductivity such as a resin such as an epoxy resin as a main component or a conductive resin containing a metal paste such as copper may be used. In this case, the thermosetting epoxy resin is filled with a material such as silica which is included for matching the coefficient of thermal expansion as a resin filler. After filling the through hole 36 with the resin 38,
The resin film 60α is attached (FIG. 4A). Note that a resin may be applied instead of attaching a resin film. After attaching the resin film 60α, the opening diameter 20 is formed in the insulating layer 60α by photo and laser.
A via hole 63 having a thickness of about 250 μm is formed and then thermally cured (FIG. 4B). Thereafter, a catalyst is applied to the core substrate, and the core substrate is immersed in the electroless plating to uniformly deposit an electroless plating film 64 having a thickness of 0.9 μm on the surface of the interlayer resin insulating layer 60. 70 (FIG. 4C).

Immersion in the electrolytic plating solution, and the electroless plating film 6
A current is passed through the substrate 4 to form an electrolytic copper plating film 65 on the non-formed portion of the resist 70 (FIG. 5A). Resist 7
Then, the electroless plating film 64 under the plating resist is dissolved and removed, and the conductor circuit 68 including the electroless plating film 64 and the electrolytic copper plating film 65 and the via hole 6 are removed.
6 is obtained (FIG. 5B).

A roughened surface (not shown) is formed on the surface of the conductor circuit 68 and the via hole 66 by using an etching solution containing a second copper complex and an organic acid, and the surface is further substituted with Sn. Good.

A solder bump is formed on the above-mentioned printed wiring board. After applying a solder resist composition to both sides of the substrate and performing a drying process, a photomask film (not shown) on which a circular pattern (mask pattern) is drawn is placed in close contact with the substrate, and is exposed to ultraviolet light. And developing. Further, a heat treatment is further performed to form a solder resist layer (thickness: 20 μm) 72 having an opening 72a in a solder pad portion (including a via hole and a land portion thereof) (FIG. 5C).

Then, the solder paste is filled into the openings 72a of the solder resist layer 72 (not shown). Thereafter, the solder filled in the opening 72a is reflowed at 200 ° C. to form a solder bump (solder body) 76 (see FIG. 6). In order to improve corrosion resistance, a metal layer such as Ni, Au, Ag, or Pd may be formed in the opening 72a by plating or sputtering.

Next, mounting of the IC chip on the printed wiring board and mounting on the daughter board will be described with reference to FIG. Solder pads 92S1, 9 of IC chip 90 are applied to solder bumps 76 of completed printed wiring board 10.
The IC chip 90 is mounted so that the 2S2, 92P1, and 92P2 correspond to each other, and the IC chip 90 is attached by performing reflow. Similarly, the pads 96S1 of the daughter board 94 are attached to the solder bumps 76 of the printed wiring board 10,
By reflowing 96S2, 96P1, 96P2,
The printed wiring board 10 is attached to the daughter board 94.

The resin film described above includes a hardly soluble resin,
Contains soluble particles, hardeners and other components.
Each is described below.

The resin film used in the production method of the present invention comprises particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) in a resin which is hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a “slightly soluble resin”). It is dispersed. The terms “sparingly soluble” and “soluble” as used in the present invention, when immersed in a solution containing the same acid or oxidizing agent for the same time, have a relatively high dissolution rate and are called “soluble” for convenience. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

Further, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

The soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed on the interlayer resin insulating layer using an acid or an oxidizing agent. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, an opening for a via hole can be formed in an interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly-soluble resin include, for example, epoxy resin, phenol resin, polyimide resin,
Examples thereof include polyphenylene resin, polyolefin resin, and fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, phenol novolak epoxy resin, alkylphenol novolak epoxy resin, biphenol F epoxy resin, and naphthalene epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin film used in the present invention, the soluble particles are desirably substantially uniformly dispersed in the poorly soluble resin. It is possible to form a roughened surface with unevenness of uniform roughness, and even if via holes and through holes are formed in the resin film, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby,
Since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film desirably contains a curing agent and other components in addition to the soluble particles and the hardly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

The other components include, for example, fillers such as inorganic compounds and resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the printed wiring board can be improved by matching the thermal expansion coefficient, improving heat resistance and chemical resistance, and the like.

Further, the resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more.

Next, a printed wiring board according to a first modification of the first embodiment of the present invention will be described with reference to FIG. The printed wiring board 10 according to the first modification has conductive pins 84 provided thereon, and is formed so as to be connected to a daughter board via the conductive pins 84. The core substrate 30 includes a housing layer 31 having a through hole 37 and connection layers 40 provided on both surfaces of the housing layer 31. The via holes 46 connected to the electrodes 21 and 22 of the chip capacitor 20 are provided in the connection layers 40 provided on both sides of the housing layer 31, and are connected to the IC chip 90 and the conductive pins 84. I have. In this first modification, FIG.
As shown in (C), the electrode 2 of the chip capacitor 20
1,2 coatings have been completely removed.

In the first embodiment described above, the core substrate 30
Although only the chip capacitor 20 accommodated in the first embodiment is provided, a large-capacity chip capacitor 86 is mounted on the front and back surfaces in the first modification.

The IC chip instantaneously consumes a large amount of power and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in the first modified example, the chip capacitor 20 and the chip capacitor 8 for power supply are mounted on the printed wiring board.
6 is provided. The effect of the chip capacitor will be described with reference to FIG.

FIG. 18 shows the voltage supplied to the IC chip on the vertical axis and the time on the horizontal axis. Here, the two-dot chain line C
Indicates voltage fluctuation of a printed wiring board without a power supply capacitor. When the power supply capacitor is not provided, the voltage greatly decreases. A broken line A indicates a voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. Although the voltage does not drop much as compared with the two-dot chain line C, the rate-limiting power supply cannot be performed sufficiently because the loop length is long. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board including the chip capacitor described above with reference to FIG. Although the loop length has been shortened,
Since a large-capacity chip capacitor cannot be accommodated in the core substrate 30, the voltage fluctuates. here,
A solid line E indicates the voltage fluctuation of the printed wiring board of the first modification in which the chip capacitor 20 in the core substrate described above with reference to FIG. 8 and the large-capacity chip capacitor 86 are mounted on the surface. By providing the chip capacitor 20 near the IC chip and the chip capacitor 86 having a large capacity (and a relatively large inductance), the voltage fluctuation is suppressed to the minimum.

Next, a printed wiring board according to a second modification will be described with reference to FIGS. The configuration of the second modification is substantially the same as that of the first embodiment. However, in the first embodiment described above, the coating of the electrodes 21 and 22 of the chip capacitor 20 is partially removed to remove the metal layer 2.
The surface of No. 6 was exposed. On the other hand, in the second modification, the chip capacitor 20 completely removes the coating of the metal layer 26 as shown in FIG. 11A, and then, as shown in FIG. Is coated with a copper plating film 29. The coating of the plating film is formed by plating such as electrolytic plating and electroless plating. Then, the first and second electrodes 2 covered with the copper plating film 29 as shown in FIG.
Electrical connections are made to the first and second via holes 46 made of copper plating. Here, the electrode 2 of the chip capacitor
Nos. 1 and 22 are metallized and have irregularities on the surface. Therefore, in the step of forming the non-through holes 43 in the connection layer 40 shown in FIG. 2B of the first embodiment, resin may remain on the irregularities. In this case, the resin residue may cause a connection failure between the first and second electrodes 21 and 22 and the via hole 46. On the other hand, in the second modified example, when the surfaces of the first and second electrodes 21 and 22 are smoothed by the copper plating film 29 and the non-through holes 43 are formed in the connection layer 40 coated on the electrodes, There is no resin residue, and the connection reliability with the electrodes 21 and 22 when the via hole 46 is formed can be improved.

Further, the electrode 2 on which the copper plating film 29 is formed
Since the via holes 46 are formed by plating on the first and second electrodes 22, the connectivity between the electrodes 21 and 22 and the via holes 46 is high.
No disconnection occurs between 2 and via hole 46.

In this case, the covering layer 28 was removed and the copper plating film 29 was provided at the stage of accommodation in the printed wiring board.
It is also possible to cover the copper plating film 29 directly on the substrate. That is, in the second modified example, after providing an opening to the copper plating film 29 of the electrode with a laser, a desmear treatment or the like is performed,
Via holes are formed by copper plating. Therefore, even if an oxide film is formed on the surface of the copper plating film 29, the oxide film can be removed by the laser and desmear treatments, so that proper connection can be established.

Further, a roughened layer 23a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. Therefore, the adhesion between the chip capacitor 20 made of ceramic and the adhesive layer 40 made of resin is high, and the adhesive layer 40 does not peel off at the interface even when the heat cycle test is performed.

Next, the configuration of the printed wiring board according to the third modification will be described with reference to FIGS. The configuration of the printed wiring board 10 of the third modification is substantially the same as that of the above-described first embodiment. However, the chip capacitors 120 housed in the core substrate 30 are different.
FIG. 13 shows a plan view of the chip capacitor. FIG. 13A shows a chip capacitor before cutting for multi-cavity production, and a dashed line in the drawing shows a cutting line. In the printed wiring board of the third embodiment described above, FIG.
As shown in the plan view of FIG. 2B, a first electrode 21 and a second electrode 22 are provided on the side edges of the chip capacitor. FIG.
(C) shows the chip capacitor for multi-cavity before cutting in the third modified example, and a dashed line in the drawing shows a cutting line. In the printed wiring board of the third modification, FIG.
As shown in the plan view, a first electrode 21 and a second electrode 22 are provided inside the side edge of the chip capacitor.

In the printed wiring board of the third modified example, since the chip capacitor 120 having the electrode formed inside the outer edge is used, a large-capacity chip capacitor can be used. In the third modification, the surface of the chip capacitor is roughened.

Next, the configuration of a printed wiring board according to a fourth modification of the present invention will be described with reference to FIGS. FIG. 14 shows a printed wiring board 10 according to a fourth modification.
FIG. 15 is a plan view of a chip capacitor 220 housed in the core substrate 30 of the printed wiring board 10. In the above-described first embodiment, a plurality of small-capacity chip capacitors are accommodated in the core substrate.
In the modification, a large-capacity large-sized chip capacitor 220 having electrodes formed in a matrix is accommodated in the core substrate 30. Here, the chip capacitor 220 is connected to the first electrode 2
The first conductive film 24 connected to the first and second electrodes 22, the dielectric 23, the first electrode 21, the second conductive film 25 connected to the second electrode 22 side, and the first conductive film 24. Second conductive film 2
5 and connection electrodes 27 on the upper and lower surfaces of the chip capacitor which are not connected to the chip capacitor 5. The IC chip side and the daughter board side are connected via the electrodes 27.

In the printed wiring board of the fourth modification, a large-sized chip capacitor 220 is used, so that a large-capacity chip capacitor can be used. Further, since the large-sized chip capacitor 220 is used, the printed wiring board 10 does not warp even when the heat cycle is repeated. In the fourth modification, the surface of the chip capacitor is subjected to a roughening treatment.

A printed wiring board according to a fifth modification will be described with reference to FIGS. FIG. 16 shows a cross section of the printed wiring board. FIG. 17A shows a chip capacitor before cutting for multi-cavity, in which a dashed line indicates a normal cutting line, and FIG. 17B is a plan view of the chip capacitor. . As shown in FIG. 17B, in this modification, a large number of chip capacitors (three in the example in the figure) are connected and used in large format.

In the fifth modification, a large-sized chip capacitor 20 is used, so that a large-capacity chip capacitor can be used. Further, since the large-sized chip capacitor 20 is used, the printed wiring board 10 does not warp even when the heat cycle is repeated. In the fifth modification, the surface of the chip capacitor is roughened.

A printed wiring board according to a sixth modification will be described with reference to FIG. FIG. 19 shows a cross section of the printed wiring board. In the first embodiment described above with reference to FIG. 6, one chip capacitor 20 is accommodated in the recess 32 of the core substrate 30. On the other hand, in the sixth modification, a plurality of chip capacitors 20 are accommodated in the recess 32. In the sixth modification, chip capacitors can be built in at a high density. In the sixth modification, the surface of the chip capacitor is roughened.

In the above-described embodiment, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, it is also possible to use a plate-like capacitor in which a conductive film is provided on a ceramic plate. Further, in the above-described embodiment, the surface of the capacitor is subjected to a roughening treatment to improve the adhesiveness with the resin, but instead, the surface of the capacitor may be subjected to a silane coupling treatment.

Here, with respect to the printed wiring board of the second modification, the inductance of the chip capacitor 20 embedded in the core substrate and the inductance of the chip capacitor mounted on the back surface (the surface on the daughter board side) of the printed wiring board were measured. The following values are shown. In case of single capacitor Embedded type 137pH Backside mounted type 287pH When 8 capacitors are connected in parallel Embedded type 60pH Backside mounted type 72pH As shown above, when using a single capacitor, it is connected in parallel to increase the capacity In addition, the inductance can be reduced by incorporating a chip capacitor.

Next, the result of the reliability test will be described. Here, in the printed wiring board of the second modified example, the change rate of the capacitance of one chip capacitor was measured. Capacitance change rate (measuring frequency 100Hz) (measuring frequency 1kHz) Steam 168 hours: 0.3% 0.4% HAST 100 hours: -0.9% -0.9% TS 1000cycles: 1.1% 1.3%

In the Steam test, steam was applied and the humidity was kept at 100%. In the HAST test, the relative humidity was 100%,
It was left at an applied voltage of 1.3 V and a temperature of 121 ° C. for 100 hours. In the TS test, 30 minutes at -125 ° C and 30 minutes at 55 ° C
The test of standing for 1000 minutes was repeated 1000 times.

In the above reliability test, it was found that a printed wiring board having a built-in chip capacitor could achieve the same reliability as the existing surface mount type capacitor. As described above, in the TS test,
Due to the difference in the coefficient of thermal expansion between the ceramic capacitor and the core substrate made of resin and the interlayer resin insulation layer, even if internal stress occurs, disconnection between the terminal of the chip capacitor and the via hole, It was found that peeling from the insulating layer and cracking of the interlayer resin insulating layer did not occur, and high reliability could be achieved for a long period of time.

[0092]

According to the structure of the present invention, the electric characteristics caused by the inductance do not decrease. Further, even under the reliability condition, the electrical characteristics and the printed wiring board do not cause peeling or cracking. Therefore, no problem occurs between the capacitor and the via hole. Further, since the resin is filled between the core substrate and the capacitor, even if stress caused by the capacitor or the like is generated, the stress is reduced and migration does not occur. Therefore, there is no influence such as peeling or melting of the connection portion between the electrode of the capacitor and the via hole. Therefore, desired performance can be maintained even if a reliability test is performed.
Also, even when the capacitor is covered with copper, the occurrence of migration can be prevented.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view of the printed wiring board according to the first embodiment.

FIG. 7 is a cross-sectional view of the printed wiring board according to the first embodiment.

FIG. 8 is a cross-sectional view of a printed wiring board according to a first modification of the first embodiment.

FIGS. 9A and 9B are cross-sectional views of the chip capacitor of the first embodiment, and FIG. 9C is a cross-sectional view of the chip capacitor of the first modification.

FIG. 10 is a cross-sectional view of a printed wiring board according to a second modification of the first embodiment.

FIGS. 11A and 11B are cross-sectional views of a chip capacitor of a second modification.

FIG. 12 is a cross-sectional view of a printed wiring board according to a third modification of the first embodiment.

FIGS. 13A, 13B, 13C, and 13D are plan views of a chip capacitor.

FIG. 14 is a sectional view of a printed wiring board according to a fourth modification of the present invention.

FIG. 15 is a plan view of a chip capacitor of a printed wiring board according to a fourth modification.

FIG. 16 is a cross-sectional view of a printed wiring board according to a modification of the fifth modification.

FIG. 17 is a plan view of a chip capacitor of a printed wiring board according to a fifth modification.

FIG. 18 is a graph showing a change in supply voltage to an IC chip and time.

FIG. 19 is a sectional view of a printed wiring board according to a sixth modification.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Printed wiring board 20 Chip capacitor 21 First electrode 22 Second electrode 26 Metal layer 28 Coating layer 29 Copper plating film 30 Core substrate 31 Enclosure layer 36 Through hole 37 Through hole 40 Connection layer 43 Non-through hole 46 Via hole 48 Conductor circuit Reference Signs List 60 interlayer resin insulation layer 66 via hole 68 conductive circuit 84 conductive pin 90 IC chip 94 daughter board

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01G 4/38 H05K 3/32 Z H05K 1/18 H01G 1/035 C 3/32 E 4/38 A ( 72) Inventor Wang East Winter 1-1, Ibigawa-cho, Ibi-gun, Gifu Prefecture, Japan Ogaki-Kita Plant (72) Inventor Eiro Yabashi 1-1, Ibikawa-cho, Ibi-gun, Gifu Prefecture, Ogaki-Kita Plant (72) Inventor Seiji Shirai 1-1 North of Ibigawa-cho, Ibi-gun, Gifu F-term (reference) in the Ogaki-Kita Plant of Ibiden Co., Ltd. JJ08 JJ09 JJ11 JJ15 JJ23 KK07 LL13 MM28 5E319 AA03 AA10 AB06 AC02 AC16 BB20 CC70 CD04 CD15 CD26 GG20 5E336 AA08 AA13 AA16 BB03 BB15 BC15 BC26 BC31 CC32 CC37 CC53 DD23 DD3 9 EE15 GG01 GG11 5E346 AA04 AA12 AA15 AA25 AA32.

Claims (12)

[Claims] 1. A printed wiring board comprising a resin insulating layer and a conductor circuit laminated on a core substrate, wherein a capacitor is housed in the core substrate. 2. A printed wiring board comprising a resin insulating layer and a conductive circuit laminated on a core substrate, wherein at least a part of a coating layer of an electrode of a chip capacitor is exposed and accommodated in the printed wiring board. A printed wiring board, wherein the electrodes exposed from the coating layer are electrically connected by plating. 3. An electrode exposed from the chip capacitor is a metal mainly composed of copper.
A printed wiring board according to claim 1. 4. A printed wiring board comprising a resin insulating layer and a conductor circuit laminated on a core substrate, wherein a metal film is formed on an electrode of a chip capacitor and accommodated in the printed wiring board. A printed wiring board characterized in that the formed electrodes are electrically connected by plating. 5. The printed wiring board according to claim 4, wherein the metal film formed on the electrode of the chip capacitor is a plating film mainly composed of copper. 6. The printed wiring board according to claim 1, wherein a chip capacitor having an electrode formed inside an outer edge is used as the capacitor. 7. The printed wiring board according to claim 1, wherein a chip capacitor having electrodes formed in a matrix is used as said chip capacitor. 8. The printed wiring board according to claim 1, wherein a plurality of chip capacitors for multi-cavity are connected and used as said capacitor. 9. A printed wiring board comprising a resin insulating layer and a conductive circuit laminated on a core substrate, wherein a chip capacitor is accommodated in the core substrate, and a capacitor is provided on a surface of the printed wiring board. A printed wiring board characterized by being mounted. 10. The printed wiring board according to claim 9, wherein the capacitance of the chip capacitor on the front surface is equal to or larger than the capacitance of the chip capacitor in the core substrate. 11. The printed wiring board according to claim 9, wherein the inductance of the chip capacitor on the surface is equal to or greater than the inductance of the chip capacitor in the inner layer. 12. A built-in capacitor for a printed wiring board, wherein a surface of a metallized electrode of a chip capacitor is coated with a copper plating film.