JP2002246504A - Method for producing multilayer printed wiring board incorporating semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for producing a multilayer printed wiring board incorporating a highly reliable semiconductor element efficiently. SOLUTION: A multilayer printed wiring board incorporating semiconductor elements are produced to take out multiple units (B). It is then cut into pieces thus obtaining individual multilayer printed wiring boards 10 (C). According to the method, the multilayer printed wiring board 10 can be produced efficiently. When a copper transition layer 38 is provided on an aluminum pad 22, resin can be prevented from remaining on the pad 22 and connectivity and reliability of the die pad 22 and a via hole 60 are enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board incorporating a semiconductor element such as an IC chip.

[0002]

2. Description of the Related Art IC chips are manufactured by wire bonding,
The electrical connection with the printed wiring board has been established by a mounting method such as TAB or flip chip. Wire bonding is to bond the IC chip to the printed wiring board with an adhesive and connect the pad of the printed wiring board and the pad of the IC chip with a wire such as a gold wire, and then to protect the IC chip and the wire. To a sealing resin such as a thermosetting resin or a thermoplastic resin.

[0003] In TAB, bumps of an IC chip and pads of a printed wiring board are connected together by a wire called a lead by soldering or the like, and then sealed with a resin. The flip chip has been performed by connecting an IC chip and a pad portion of a printed wiring board via a bump, and filling a gap between the bump and the resin with a resin.

[0004] However, each mounting method is based on I
Electrical connection is made between the C chip and the printed wiring board via connection lead components (wires, leads, bumps). Each of these lead components is easily cut and corroded, which may cause the connection with the IC chip to be interrupted or a malfunction to occur. Also, in each mounting method, sealing is performed with a thermoplastic resin such as an epoxy resin to protect the IC chip, but if the resin is filled with air bubbles, the air bubbles become a starting point,
This leads to destruction of lead components, corrosion of IC pads, and a decrease in reliability. For sealing with thermoplastic resin, it is necessary to create a resin loading plunger and mold according to each part, and even for thermosetting resin, consider materials such as lead parts and solder resist Since it is necessary to select a suitable resin, the cost of each resin is also increased.

On the other hand, instead of mounting an IC chip on the outside of a printed wiring board (package substrate) as described above, a semiconductor element is embedded in a substrate and a build-up layer is formed thereon to provide electrical connection. Japanese Patent Laid-Open No. 9-321408 (USP5)
875100), JP-A-10-256429 and JP-A-11-126978.

Japanese Patent Application Laid-Open No. 9-321408 (USP 587)
No. 5100), a semiconductor element having a stud bump formed on a die pad is embedded in a printed wiring board, and a wiring is formed on the stud bump to make an electrical connection. However, since the stud bump has an onion shape and a large variation in height, when an interlayer insulating layer is formed, the smoothness is reduced, and even if a via hole is formed, the stud bump is easily disconnected. Further, the stud bumps are planted one by one by bonding, so that they cannot be arranged collectively, and there is a problem in terms of productivity.

Japanese Patent Laid-Open No. Hei 10-256429 discloses a structure in which a semiconductor element is housed in a ceramic substrate and is electrically connected in a flip-chip form. However, ceramic has poor external formability, and the semiconductor element is not easily accommodated. In addition, the bumps had large variations in height. Therefore, the smoothness of the interlayer insulating layer is impaired, and the connection is reduced.

Japanese Patent Application Laid-Open No. 11-126978 discloses a multilayer printed wiring board in which electronic components such as a semiconductor element are embedded in a space accommodating portion, connected to a conductor circuit, and stored through via holes. ing. However, since the accommodating portion is an air gap, it is easy to cause a positional shift and disconnection to a pad of the semiconductor element is apt to occur. Further, since the die pad and the conductor circuit are directly connected, there is a problem that an oxide film is easily formed on the die pad and the insulation resistance is increased.

Furthermore, a highly reliable printed circuit board with a built-in semiconductor element cannot be efficiently manufactured.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to efficiently provide a multilayer printed wiring board incorporating a highly reliable semiconductor element. An object is to propose a manufacturing method that can be manufactured.

[0011]

Means for Solving the Problems As a result of intensive studies, the present inventor has created a method of forming a transition layer on a die pad of a semiconductor device. Even if the semiconductor element having the transition layer is housed in a printed wiring board,
Even if an interlayer insulating layer is formed thereon and a via hole is formed, a desired size and shape can be obtained.

The reason for providing the transition layer on the die pad of the IC chip will be described. The pads of the IC chip are generally made of aluminum or the like. When via holes in the interlayer insulating layer were formed by photoetching with the die pad having no transition layer formed thereon, the resin was likely to remain on the surface of the pad after exposure and development if the die pad was still formed. In addition, the adhesion of the developing solution caused discoloration of the pad. On the other hand, even when a via hole was formed by a laser, if the process was performed under the condition that the die pad was not burnt, resin residue was left on the pad. Further, in a later step, when the substrate was immersed in an acid, an oxidizing agent, or an etching solution, or passed through various annealing steps, discoloration and dissolution of the IC chip pad occurred. Further, the pad of the IC chip is made with a diameter of about 40 μm, and the via hole is larger than that, so that disconnection is likely to occur at the time of displacement.

On the other hand, by providing a transition layer made of copper or the like on the die pad, it is possible to use a solvent and prevent resin residue on the pad. Also,
No discoloration or dissolution of the pad occurs even when the pad is immersed in an acid, an oxidizing agent, or an etching solution in a later step, or undergoes various annealing steps. This improves the connectivity and reliability between the pad and the via hole. Further, the via hole can be reliably connected by interposing a transition layer having a diameter larger than 40 μm on the pad of the IC chip. Desirably, the transition layer has a diameter equal to or greater than the diameter of the via hole.

Further, since the transition layer is formed, the operation and electrical inspection of the semiconductor element can be easily performed before or after the semiconductor element is housed in the printed wiring board. This is because a transition layer larger than the die pad is formed, so that the probe pins are easily brought into contact. As a result, the availability of the product can be determined in advance, and productivity and cost can be improved.

Therefore, by forming the transition, the semiconductor element can be suitably accommodated in the printed wiring. That is, it can be said that a semiconductor element having a transition layer is a semiconductor element to be embedded in a printed wiring board. The transition layer is formed on the die pad,
A thin film layer is formed, and a thick layer is formed thereon. It can be formed of at least two layers.

The transition layer defined in the present invention will be described. The transition layer means an intermediate mediation layer provided for directly connecting an IC chip as a semiconductor element and a printed wiring board without using a conventional IC chip mounting technique. It is characterized in that it is formed of two or more metal layers and is larger than a die pad of an IC chip as a semiconductor element. Thereby, electrical connection and alignment are improved, and via holes can be formed by laser or photoetching without damaging the die pad. Therefore, embedding, accommodation, accommodation, and connection of the IC chip in the printed wiring board can be ensured. In addition, it is possible to directly form a metal which is a conductor layer of a printed wiring board on the transition layer.
Examples of the conductor layer include via holes in an interlayer resin insulating layer and through holes on a substrate.

Although each of them functions only by a multilayer printed wiring board, in some cases, the connection to a mother board or a daughter board as an external board is required for the function as a package board as a semiconductor device.
GAs, solder bumps or PGAs (conductive connection pins) may be provided. In addition, with this configuration, the wiring length can be made shorter than in the case where the connection is made by the conventional mounting method, and the loop inductance can be reduced.

According to the present invention, a multi-layer printed wiring board having a semiconductor element is manufactured for multiple pieces, and cut into individual pieces to obtain individual multi-layer printed wiring boards. For this reason, the highly reliable multilayer printed wiring board can be efficiently manufactured.

The resin substrate for incorporating electronic components such as an IC chip used in the present invention is a resin in which a reinforcing material such as a glass epoxy resin or a core material is impregnated in an epoxy resin, a BT resin, a phenol resin or the like, or an epoxy resin. A laminate of prepregs impregnated with is used, but those generally used for printed wiring boards can be used. In addition, a double-sided copper-clad laminate, a single-sided plate, a resin plate having no metal film, and a resin sheet can be used. However, if a temperature of 350 ° C. or more is applied, the resin will melt and carbonize.

A conductive metal film is formed on the entire surface of the IC chip by physical vapor deposition such as evaporation or sputtering. The metals include tin, chrome, titanium,
It is preferable to form one or more layers of a metal such as nickel, zinc, cobalt, gold, and copper. As the thickness, 0.001 to
It is preferable to form it between 2.0 μm. In particular, 0.01
It is desirable to form it between 1.0 μm and 1.0 μm. In particular, it is preferable to use nickel, chromium, or titanium. This is because there is no penetration of moisture from the interface and the metal adhesion is excellent.

A metal film may be further provided on the metal film by electroless plating or the like. The upper metal film is preferably formed by forming one or more layers of a metal such as nickel, copper, gold, and silver.

The metal film is thickened by electroless or electrolytic plating. Types of plating to be formed include nickel, copper, gold, silver, zinc, and iron. It is preferable to use copper because the electrical characteristics, economy, and the conductor layer, which is a build-up formed later, are mainly copper. The thickness is preferably in the range of 1 to 20 μm.
If the thickness is larger than that, an undercut occurs at the time of etching, and a gap may be generated at the interface between the formed transition layer and the via hole. afterwards,
An etching resist is formed, exposed and developed to expose portions of the metal other than the transition layer, and etching is performed to form a transition layer on the pads of the IC chip.

In addition to the above-mentioned method of manufacturing a transition layer, a dry film resist is formed on a metal film formed on an IC chip and a core substrate, and a portion corresponding to the transition layer is removed. After thickening, the resist can be peeled off, and a transition layer can be similarly formed on the pad of the IC chip using an etching solution.

In the present invention, prepregs having through holes for accommodating IC chips are stacked and pressed from above and below.
The epoxy resin exudes from the prepreg and covers the upper surface of the IC chip. Thereby, the upper surfaces of the IC chip and the core substrate obtained by curing the resin such as the prepreg are completely flat. For this reason, when forming the build-up layer, via holes and wiring can be appropriately formed, and the reliability of wiring of the multilayer printed wiring board can be improved.

Further, in a preferred embodiment of the present invention, a heat sink is attached to the back surface of the semiconductor element embedded in the printed wiring board. Thus, heat generated in the semiconductor element is released, the printed wiring board is not warped, and no disconnection is caused, thereby improving reliability.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] An embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 15, the multilayer printed wiring board 10 of the first embodiment
0, an interlayer resin insulating layer 50, and an interlayer resin insulating layer 150. Via holes 60 and conductor circuits 58 are formed in the interlayer resin insulation layer 50,
Via holes 160 and conductive circuits 158 are formed in interlayer resin insulating layer 150.

On the interlayer resin insulation layer 150, a solder resist layer 70 is provided. The conductor circuit 158 below the opening 71 of the solder resist layer 70 is provided with a solder bump 76 for connecting to an external board (not shown) such as a daughter board or a mother board.

In the multilayer printed wiring board 10 of this embodiment,
The IC chip 20 is built in the core substrate 30, and the transition layer 38 is provided on the pad 22 of the IC chip 20. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using a lead component or a sealing resin. Further, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer 50 is also flattened and the film thickness becomes uniform. Further, the transition layer allows the upper via hole 6 to be formed.
Even when 0 is formed, the stability of the shape can be maintained.

Further, by providing a copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented. Also, in a later step, the resin can be immersed in an acid, an oxidizing agent, an etching solution, or the like. Discoloration and dissolution of the pad 22 do not occur even after various annealing processes. This improves the connectivity and reliability between the pads of the IC chip and the via holes. Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, a via hole having a diameter of 60 μm can be reliably connected.

A. First, the multilayer printed wiring board 1 described above with reference to FIG.
Semiconductor element (IC chip) housed, housed or embedded in 0
3 showing a cross section of a semiconductor element 20 in the configuration of FIG.
This will be described with reference to FIG. 4A and FIG.

As shown in FIG. 3B, a die pad 22 and a wiring (not shown) are provided on the upper surface of the semiconductor element 20, and a passivation film 24 covers the die pad 22 and the wiring. The die pad 22 includes
An opening in the passivation film 24 is formed. On the die pad 22, a transition layer 38 mainly made of copper is formed. The transition layer 38
It comprises a thin film layer 33 and an electrolytic plating film 37.

[First Manufacturing Method] Subsequently, the method of manufacturing the semiconductor device described above with reference to FIG.
This will be described with reference to FIGS.

(1) First, a wiring 21 and a die pad 2 are formed on a silicon wafer 20A shown in FIG.
2 (see FIG. 1A and FIG. 4A which shows a plan view of FIG. 1B, and FIG. 1B shows a cross section taken along line BB of FIG. 4A). There). (2) Next, a passivation film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (FIG. 1C).

(3) Physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form a conductive metal film (thin film layer) 33 on the entire surface (FIG. 2A).
The thickness is preferably in the range of 0.001 to 2.0 μm. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimal range is from 0.01 to 1.0 μm. As a metal to be formed, a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the first manufacturing method, the thin film layer 33 is formed of chromium.

(4) Thereafter, a resist layer of any of a liquid resist, a photosensitive resist, and a dry film is formed on the thin film layer 33. A mask (not shown) on which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and exposed and developed, and the plating resist 35 is formed.
To form a non-formed portion 35a. Thick layer (electrolytic plating film) on the non-formed portion 35a of the resist layer by applying electrolytic plating
37 are provided (FIG. 2B). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron.
Since the electrical characteristics, economy, and the conductor layer which is a build-up formed later are mainly copper, copper is preferably used. In the first manufacturing method, copper is used. Its thickness is 1
It is preferable to carry out in the range of up to 20 μm.

(5) After the plating resist 35 is removed with an alkaline solution or the like, the metal film 33 under the plating resist 35 is coated with sulfuric acid-hydrogen peroxide, ferric chloride, cupric chloride, cupric complex-organic. By removing with an etching solution such as an acid salt, the transition layer 38 is formed on the pad 22 of the IC chip.
Is formed (FIG. 2C).

(6) Next, a roughened surface 38α is formed by spraying an etching solution on the substrate by spraying and etching the surface of the transition layer 38 (FIG. 3A).
reference). The roughened surface can be formed by using electroless plating or oxidation-reduction treatment.

(7) Finally, the semiconductor wafer 20 is formed by dividing the silicon wafer 20A on which the transition layer 38 is formed into individual pieces by dicing or the like (FIG. 3).
(B) and FIG. 4 (B) which is a plan view of FIG. 3 (B)). Then, if necessary, the divided semiconductor elements 2
An operation check of 0 or an electrical inspection may be performed. Since the semiconductor element 20 has the transition layer 38 larger than the die pad 22, the probe pins can be easily applied to the semiconductor element 20, and the inspection accuracy is high.

[Second Manufacturing Method] A semiconductor device 20 according to a second manufacturing method will be described with reference to FIG. In the semiconductor device according to the first manufacturing method described above with reference to FIG.
3 and an electrolytic plating film 37. On the other hand, in the second manufacturing method, as shown in FIG. 7B, the transition layer 38 has a three-layer structure including the thin film layer 33, the electroless plating film 36, and the electrolytic plating film 37. It is configured.

Subsequently, a method of manufacturing a semiconductor device according to the second manufacturing method described above with reference to FIG.
This will be described with reference to FIGS.

(1) First, the wiring 21 and the die pad 22 are formed on the silicon wafer 20A shown in FIG. 5A (FIG. 5B). (2) Next, a passivation film 24 is formed on the die pad 22 and the wiring (FIG. 5C).

(3) Physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A to form a conductive metal film (first thin film layer) 33 on the entire surface (FIG. 5).
(D)). The thickness is preferably in the range of 0.001 to 2.0 μm. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimal range is from 0.01 to 1.0 μm. Metals to be formed include tin, chromium, titanium, nickel,
It is preferable to use one selected from zinc, cobalt, gold, and copper. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the second manufacturing method, the first thin film layer 33 is formed of chromium.

(4) Sputtering on the first thin film layer 33
An electroless plating layer (second thin film layer) 36 is laminated by vapor deposition and electroless plating (FIG. 6A). The thickness is 0.01
The thickness is preferably from 5.0 to 5.0 μm, particularly preferably from 0.1 to 3 μm. In that case, the metals that can be laminated are nickel, copper,
It is better to choose from gold and silver. In particular, it is good to form with either copper or nickel. Copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. In the second manufacturing method, the second thin film layer 36 is formed by electroless copper plating. In addition, the desirable first thin film layer and the second
Combinations with thin film layers are chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of bonding to metals and electrical conductivity.

(5) Thereafter, a resist layer is formed on the second thin film layer 3
6 is formed. A mask (not shown) is placed on the resist layer, and a non-formed portion 35a is formed on the resist 35 through exposure and development. Electroplating is performed to provide a thick layer (electrolytic plating film) 37 in the non-formed portion 35a of the resist layer (FIG. 6B). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Electrical properties, economics, and because the conductor layer that is a build-up formed later is mainly copper, it is better to use copper,
In the second manufacturing method, copper is used. The thickness is 1 to 20 μm
Range is good.

(6) After removing the plating resist 35 with an alkali solution or the like, the electroless plating film 36 and the metal film 33 under the plating resist 35 are removed by using sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, The transition layer 38 is formed on the pad 22 of the IC chip by removing the copper oxide complex with an etching solution such as an organic acid salt (FIG. 6C).

(7) Next, a roughened surface 38α is formed by spraying an etching solution on the substrate by spraying and etching the surface of the transition layer 38 (FIG. 7A).
reference). The roughened surface can be formed by using electroless plating or oxidation-reduction treatment.

(8) Finally, the semiconductor wafer 20 is formed by dividing the silicon wafer 20A on which the transition layer 38 is formed into individual pieces by dicing or the like (FIG. 7).
(B)).

[Third Manufacturing Method] A method of manufacturing the semiconductor device 20 according to the third manufacturing method will be described with reference to FIG. The structure of the semiconductor element of the third manufacturing method is shown in FIG.
Is substantially the same as the first manufacturing method described above with reference to FIG.
However, in the first manufacturing method, the transition layer 38 was formed by forming the thickening layer 37 in the non-resist forming portion using a semi-additive process. In contrast, the third
In the manufacturing method (1), a transition layer 38 is formed by forming a thick layer 37 uniformly using a full additive process, then providing a resist, and removing a non-resist-formed portion by etching.

The manufacturing method of the third manufacturing method will be described with reference to FIG. (1) As described above with reference to FIG. 2B in the first manufacturing method, physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A, and the conductive metal film 3 is formed on the entire surface.
3 is formed (FIG. 8A). The thickness is 0.00
The range is preferably from 1 to 2.0 μm. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimum range is preferably formed in the range of 0.01 to 1.0 μm. As a metal to be formed, a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the third manufacturing method, the thin film layer 33
Is formed by chromium.

(2) A thick layer (electrolytic plating film) 37 is uniformly provided on the thin film layer 33 by performing electrolytic plating (FIG. 8).
(B)). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Electrical properties, economics,
Further, since the conductor layer which is a build-up formed later is mainly made of copper, copper is preferably used. In the third manufacturing method, copper is used. The thickness is preferably in the range of 1 to 20 μm. If the thickness is larger than that, an undercut occurs during the etching described later, and a gap may be generated at the interface between the formed transition layer and the via hole.

(3) Thereafter, a resist layer 35 is formed on the thick layer 37 (FIG. 8C).

(4) The metal film 3 in the portion where the resist 35 is not formed
3 and the thickening layer 37 are removed with an etching solution such as sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt, and the resist 35 is peeled off to remove the IC. A transition layer 38 on the chip pads 22
Is formed (FIG. 8D). Subsequent steps are the same as in the first manufacturing method, and a description thereof will be omitted.

[Fourth Manufacturing Method] A method of manufacturing the semiconductor device 20 according to the fourth manufacturing method will be described with reference to FIG. In the semiconductor device according to the third manufacturing method described above with reference to FIG. 8, the transition layer 38 has a two-layer structure including the thin film layer 33 and the electrolytic plating film 37. On the other hand, in the fourth manufacturing method, as shown in FIG. 9D, the transition layer 38 has a three-layer structure including the thin film layer 33, the electroless plating film 36, and the electrolytic plating film 37. It is configured.

The manufacturing method of the fourth manufacturing method will be described with reference to FIG. (1) Similar to the second manufacturing method described above with reference to FIG. 6A in the first manufacturing method, the second thin film layer is formed on the first thin film layer 33 by sputtering, vapor deposition, and electroless plating. 36 are laminated (FIG. 9A). The thickness is 0.01 to 5.0 μm
It is particularly desirable that the thickness be 0.1 to 3 μm. In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it is good to form with either copper or nickel. Copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. In the fourth manufacturing method, the second thin film layer 36 is formed by electroless copper plating. Note that a desirable combination of the first thin film layer and the second thin film layer is chromium-copper, chromium-nickel, titanium-
Copper and titanium-nickel. It is superior to other combinations in terms of bonding to metals and electrical conductivity.

(2) The second thin film layer 3 is formed by performing electrolytic copper plating.
A thick layer (electrolytic plating film) 37 is provided evenly on 6 (FIG. 9B). The type of plating to be formed is copper,
Nickel, gold, silver, zinc, iron and the like. Its thickness is 1
It is preferable to carry out in the range of up to 20 μm.

(3) Thereafter, a resist layer 35 is formed on the thick layer 37 (FIG. 9C).

(4) The first thin film layer 33, the second thin film layer 36, and the thickening layer 37 where the resist 35 is not formed are formed by using sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, and cupric copper. After removal with an etchant such as a complex-organic acid salt, the resist 3
By peeling 5, a transition layer 38 is formed on the pads 22 of the IC chip (FIG. 9D). Subsequent steps are the same as in the first manufacturing method, and a description thereof will be omitted.

B. Multilayer Printed Wiring Board Incorporating Semiconductor Element Next, the method of manufacturing the multilayer printed wiring board described above with reference to FIG.
This will be described with reference to FIGS.

(1) A 0.5 mm thick insulating resin substrate 30A obtained by laminating and curing a prepreg impregnated with a resin such as BT (bismaleimide triazine) resin or epoxy on a core material such as glass cloth is used as a starting material. I do. First, a through hole 32 for accommodating an IC chip is formed in the insulating resin substrate 30A (see FIG. 10A). Here, the resin substrate 30A in which the core material is impregnated with the resin is used, but a resin substrate having no core material may be used.

(2) Thereafter, the IC chip 20 according to the above-described first to fourth manufacturing methods is housed in the through hole 32 of the insulating resin substrate 30A (see FIG. 10B).

(3) Then, the insulating resin substrate 30A for accommodating the IC chip 20 and a prepreg impregnated with a core material such as glass cloth or a resin such as BT or epoxy are laminated and cured to a thickness of 0%. .2 mm insulating resin substrate (core substrate) 30B and an uncured prepreg 30C in which a core material such as glass cloth is impregnated with a resin such as epoxy.
(Thickness: 0.1 mm)
(C)). Here, the resin substrate 30B in which the core material is impregnated with the resin is used, but a resin substrate having no core material may be used. Further, instead of the prepreg, various thermosetting resins or a sheet obtained by impregnating a core material with a thermosetting resin and a thermoplastic resin can be used.

(4) Stainless (SUS) pressed plate 10
At 0A and 100B, the above-described laminate is pressed from above and below. At this time, the epoxy resin 3 is removed from the prepreg 30C.
Oα exudes and fills the space between the through hole 32 and the IC chip 20 and covers the upper surface of the IC chip 20. Thereby, the upper surfaces of the IC chip 20 and the insulating resin substrate 30A become completely flat. (FIG. 11A). For this reason, when forming the build-up layer in a step described later, the via hole and the wiring can be appropriately formed, and the reliability of the wiring of the multilayer printed wiring board can be improved.

(5) Thereafter, the core substrate 30 accommodating the IC chip 20 is formed by heating and curing the uncured epoxy resin 30α (FIG. 11B).

(6) A substrate having a thickness of 50 μm
m of a thermosetting epoxy resin sheet at a temperature of 50-150.
Vacuum compression lamination at a pressure of 5 kg / cm ² while raising the temperature to 0 ° C., and an interlayer resin insulation layer 5 mainly composed of a thermosetting resin.
0 is provided (see FIG. 11C). The degree of vacuum during vacuum compression is 10 mmHg.

(7) Next, using a CO ₂ gas laser having a wavelength of 10.4 μm, a beam diameter of 5 mm, a top hat mode,
Under the conditions of a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot, a via hole opening 48 having a diameter of 60 μm is provided in the interlayer resin insulating layer 50 (see FIG. 12A).
Opening 4 using an oxidizing agent such as chromic acid or permanganic acid
The resin residue in 8 is removed. By providing the copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented, thereby improving the connectivity and reliability between the pad 22 and via holes 60 described later. Further, by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm,
Via hole openings 48 having a diameter of m can be reliably connected. Here, the resin residue is removed using an oxidizing agent, but it is also possible to perform desmearing using oxygen plasma.

(8) Next, the surface of the interlayer resin insulating layer 50 is roughened with permanganic acid to form a roughened surface 50α (FIG. 1).
2 (B)).

(9) An electroless plating film 52 is provided on the interlayer resin insulating layer 50 on which the roughened surface 50α is formed (FIG. 12).
(C)). Copper and nickel can be used as the electroless plating. As its thickness, from 0.3 μm
The range of 1.2 μm is good. If it is less than 0.3 μm, it may not be possible to form a metal film on the interlayer resin insulation layer. If the thickness exceeds 1.2 μm, the metal film remains due to the etching, and a short circuit between conductors is easily caused. A plating film was formed under the following plating solution and plating conditions. [Electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyryl 100 mg / l Polyethylene glycol (PEG) 0.10 g / l [Electroless Plating Condition] Dipped at a liquid temperature of 34 ° C. for 40 minutes.

Other than the above, using the same apparatus as in the above-described plasma processing, sputtering using a Ni—Cu alloy as a target was performed at a pressure of 0.6 Pa, a temperature of 80 ° C., and a power of 200
The process is performed under the condition of W for 5 minutes to form a Ni—Cu alloy 52 on the surface of the interlayer resin insulating layer 50. At this time, the thickness of the formed Ni—Cu alloy layer 52 is 0.2 μm (see FIG. 12C).

(10) A commercially available photosensitive dry film is affixed to the substrate 30 that has been subjected to the above processing, a photomask film is placed, and after exposure at 100 mJ / cm ² ,
Develop with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 20 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 13A). The additive in the electrolytic plating aqueous solution was Capparaside H manufactured by Atotech Japan.
L.

[Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (captoside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

(11) Plating resist 54 is made of 5% NaO
After removing with H, the plating film layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and a thickness of 16 μm comprising the plating film layer 52 and the electrolytic plating film 56 is formed. Are formed, and roughened surfaces 58α and 60α are formed by an etching solution containing a cupric complex and an organic acid (see FIG. 13B). In this embodiment, FIG.
As described above with reference to (A), since the upper surface of the core substrate 30 is formed completely smooth, the via hole 60
Accordingly, the connection to the transition layer 38 can be appropriately established. For this reason, it is possible to improve the reliability of the multilayer printed wiring board.

(12) Next, the above steps (6) to (11) are repeated to form a further upper interlayer resin insulating layer 150 and a conductor circuit 158 (including via holes 160) (FIG. 13 ( C)).

(13) Next, a cresol novolak-type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight, and a 50% epoxy group was acrylated. Oligomer for imparting properties (molecular weight 4000) 46.67
15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) of 80% by weight dissolved in methyl ethyl ketone, imidazole hardener (trade name: 2E4MZ-CN)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., trade name: R604) as a photosensitive monomer,
Similarly, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name:
1.5 parts by weight of DPE6A) and 0.71 part by weight of a dispersant antifoaming agent (manufactured by San Nopco, trade name: S-65) are placed in a container, stirred and mixed to prepare a mixed composition. Of benzophenone (manufactured by Kanto Kagaku) and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at ° C is obtained. The viscosity was measured using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm and rotor No. 4 at 6 rpm.
According to

(14) Next, the above-mentioned solder resist composition is applied to the substrate 30 at a thickness of 20 μm,
After performing a drying process at 70 ° C. for 30 minutes for 0 minute, a 5 mm-thick photomask on which a pattern of the opening of the solder resist resist is drawn is brought into close contact with the solder resist layer 70, and an ultraviolet ray of 1000 mJ / cm ² is applied. And developing with a DMTG solution to form an opening 71 having a diameter of 200 μm (see FIG. 14A).

(15) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 was formed was replaced with nickel chloride (2.3 × 10 ⁻¹ mol / l) and sodium hypophosphite (2.8 × 10 ^-1 mol / l) and an electroless nickel plating solution having a pH of 4.5 containing sodium citrate (1.6 × 10 ^-1 mol / l) for 20 minutes.
Then, a nickel plating layer 72 having a thickness of 5 μm is formed. Further, the substrate was subjected to potassium gold cyanide (7.6 × 10 ^−3).
mol / l), ammonium chloride (1.9 × 10 ^-1 mo)
1 / l), sodium citrate (1.2 × 10 ^-1 mol)
/ L), sodium hypophosphite (1.7 × 10 ^-1 mol)
/ L) is immersed for 7.5 minutes at 80 ° C. in an electroless plating solution containing
By forming the gold plating layer 74 of the length m, the conductor circuit 158 can be formed.
Then, a solder pad 75 is formed (see FIG. 14B).

(16) Thereafter, the solder resist layer 70
A solder paste is printed in the opening 71 of the substrate and reflowed at 200 ° C. to form a solder bump.
Then, it is divided by dicing or the like to obtain individual multilayer printed wiring boards 10 (FIG. 14C). In FIG. 14C, the multilayer printed wiring board is shown as being divided into two for convenience of illustration, but is divided into 16 divisions, 32 divisions, and 64 divisions.
A large number of multilayer printed wiring boards with built-in IC chips are manufactured at the same time by division or the like.

In the first embodiment, FIGS.
Through the steps described above with reference to (B), a multi-layer printed wiring board including a semiconductor element is manufactured for multi-cavity production. Then, as shown in FIG. 14 (C), individual multilayer printed wiring boards are obtained by cutting into individual pieces. Therefore, the highly reliable multilayer printed wiring board 10 can be efficiently manufactured (see FIG. 15).

In the above embodiment, the interlayer resin insulating layer 5
A thermosetting epoxy resin sheet was used for Nos. 0 and 150.
This epoxy resin contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each is described below.

The epoxy resin used in the production method of the present invention is a resin in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) are hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a “slightly soluble resin”). It is distributed in. The terms "sparingly soluble" and "soluble" used in the present invention are referred to as "soluble" for convenience when those immersed in a solution comprising the same acid or oxidizing agent for the same time have a relatively high dissolution rate. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and acid or oxidizing agents. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

Further, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the above-mentioned soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

As the soluble metal particles, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin sheet can be ensured, and the thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin sheet. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed by using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, an opening for a via hole can be formed in an interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, phenol novolak epoxy resin, alkylphenol novolak epoxy resin, biphenol F epoxy resin, and naphthalene epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin sheet used in the present invention, it is desirable that the soluble particles are substantially uniformly dispersed in the hardly-soluble resin. It is possible to form a roughened surface with unevenness of uniform roughness, and even if via holes and through holes are formed in the resin sheet, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can.
Alternatively, a resin sheet containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin sheet are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin sheet, the amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight based on the resin sheet. If the amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed.
When the soluble particles are dissolved using an acid or an oxidizing agent, they dissolve to the deep part of the resin sheet, failing to maintain the insulation between the conductor circuits via the interlayer resin insulation layer made of the resin sheet, and causing a short circuit. It may be.

The resin sheet desirably contains a curing agent and other components in addition to the soluble particles and the hardly-soluble resin. Examples of the curing agent include imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and those obtained by microencapsulating these curing agents, triphenylphosphine, and tetraphenylphosphonate. Organic phosphine-based compounds such as ammonium tetraphenylborate.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin sheet. 0.0
If the content is less than 5% by weight, the resin sheet is insufficiently cured, so that the degree of penetration of acid or oxidizing agent into the resin sheet becomes large, and the insulating property of the resin sheet may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

Examples of the other components include fillers such as inorganic compounds and resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the multilayer printed wiring board can be improved by matching thermal expansion coefficients, improving heat resistance and chemical resistance, and the like.

Further, the resin sheet may contain a solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone and cyclohexanone, ethyl acetate, butyl acetate, aromatic hydrocarbons such as cellosolve acetate, toluene and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers are dissolved and carbonized when a temperature of 350 ° C. or more is applied.

[First Modification] Next, a multilayer printed wiring board according to a modification of the first embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, the case where the BGA is provided has been described. The first modified example is almost the same as the first embodiment, but is configured as a PGA system in which connection is made via conductive connection pins 96 as shown in FIG.
In the first embodiment described above, the via hole is formed by laser, but in the first modification, the via hole is formed by photoetching.

A method for manufacturing a multilayer printed wiring board according to the first modification will be described with reference to FIG. (4) As in the first embodiment, (1)-(3) a 50 μm thick thermosetting epoxy resin 5
0 is applied (see FIG. 16A).

(5) Next, the photomask film 49 on which the black circle 49a corresponding to the via hole formation position is drawn is placed on the interlayer resin insulation layer 50 and exposed (FIG. 16).
(B)).

(6) Spray development with a DMTG solution and heat treatment are performed to obtain a via hole opening 4 having a diameter of 85 μm.
8 is provided (FIG. 16C).
reference).

(7) The surface of the interlayer resin insulating layer 50 is roughened with permanganic acid or chromic acid to form a roughened surface 50α (see FIG. 16D). Subsequent steps are the same as those in the above-described first embodiment, and a description thereof will not be repeated.

[Second Embodiment] Next, the configuration of a multilayer printed wiring board according to a second embodiment for housing the semiconductor element (IC chip) 20 of the above-described first to fourth manufacturing methods will be described. In the multilayer printed wiring board 10 of the first embodiment described above with reference to FIG. 15, an IC chip is embedded in a core substrate. On the other hand, in the second embodiment, as shown in FIG.
Is attached. The multilayer printed wiring board 10 includes:
The heat sink 30D, the core substrate 31 accommodating the IC chip 20, and the interlayer resin insulation layer 5 on the IC chip 20
0 and an interlayer resin insulation layer 150. Via holes 60 and conductive circuits 58 are formed in interlayer resin insulation layer 50, and via holes 160 are formed in interlayer resin insulation layer 150.
And a conductor circuit 158 are formed.

On the interlayer resin insulating layer 150, a solder resist layer 70 is provided. The conductor circuit 158 below the opening 71 of the solder resist layer 70 is provided with a solder bump 76 for connecting to an external board (not shown) such as a daughter board or a mother board.

The heat sink 30D is made of a ceramic such as aluminum nitride, alumina or mullite, or a metal such as an aluminum alloy, copper, or adjacent bronze. Here, it is preferable to use an aluminum alloy having a high thermal conductivity or a copper foil subjected to a roughening treatment on both surfaces. In the present embodiment, the heat sink 30D is attached to the back surface of the IC chip 20 embedded in the core substrate 31, so that the IC chip 2
0 is released to prevent the core substrate 31 and the interlayer resin insulating layers 50 and 150 formed on the core substrate from warping, and to form via holes 60 and 160 on the interlayer resin insulating layer.
Disconnection of the conductor circuits 58 and 158 is prevented. Thereby, the reliability of the wiring is improved.

Note that the IC chip 20 is
OD is attached by a conductive adhesive 29.
The conductive adhesive 29 contains a metal powder such as copper, silver, gold, and aluminum in a resin and has high thermal conductivity, so that heat generated in the IC chip 20 is efficiently released to the heat sink 30D side. be able to. Here, a conductive adhesive is used for attaching the IC chip 20, but various adhesives can be used as long as the adhesive has high thermal conductivity.

In the multilayer printed wiring board 10 of this embodiment,
The IC chip 20 is built in the core substrate 31, and the transition layer 38 is provided on the pad 22 of the IC chip 20. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using a lead component or a sealing resin. Further, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer 50 is also flattened and the film thickness becomes uniform. Further, the transition layer allows the upper via hole 6 to be formed.
Even when 0 is formed, the stability of the shape can be maintained.

Further, by providing a copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented, and it can be immersed in an acid, an oxidizing agent, an etching solution, or the like in a later step. Discoloration and dissolution of the pad 22 do not occur even after various annealing processes. This improves the connectivity and reliability between the pads of the IC chip and the via holes. Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, a via hole having a diameter of 60 μm can be reliably connected.

Subsequently, the second method described with reference to FIG.
Regarding the method for manufacturing a multilayer printed wiring board according to the example,
This will be described with reference to FIGS.

(1) A plate-like heat sink 30D made of ceramic such as aluminum nitride, alumina, mullite, or an aluminum alloy, adjacent bronze, etc. (FIG. 18A)
Then, a conductive adhesive 29 is applied (FIG. 18B). As the conductive adhesive, a paste containing copper particles having an average particle diameter of 2 to 5 μm and having a thickness of 10 to 20 μm was used.

(2) The first method described above with reference to FIG.
To the fourth manufacturing method (FIG. 18)
(C)).

(3) Next, the heat sink 30D to which the IC chip 20 is attached is placed on a stainless (SUS) press plate 100A. Then, a prepreg laminate 31α having a thickness of 0.5 mm formed by laminating an uncured prepreg obtained by impregnating a core material such as a glass cloth with a resin such as a BT (bismaleimide triazine) resin or an epoxy resin is used as a heat sink 3.
0D (FIG. 19A). Prepreg laminate 3
In 1α, a through hole 32 is provided in advance at the position of the IC chip 20. Here, the prepreg in which the core material is impregnated with the resin is used, but a resin substrate having no core material may be used. Further, instead of the prepreg, various thermosetting resins or a sheet obtained by impregnating a core material with a thermosetting resin and a thermoplastic resin can be used.

(4) Stainless steel (SUS) press plate 10
At 0A and 100B, the above-described laminate is pressed from above and below. At this time, the epoxy resin 3
1β exudes and fills the space between the through hole 32 and the IC chip 20 and covers the upper surface of the IC chip 20. Thereby, the IC chip 20 and the prepreg laminate 31α
Is completely flattened. (FIG. 19B). For this reason, when forming a build-up layer in a process described below,
Via holes and wiring can be properly formed, and the reliability of wiring of a multilayer printed wiring board can be improved.

(5) Thereafter, the core substrate 31 accommodating the IC chip 20 is formed by heating and curing the epoxy resin of the prepreg (FIG. 19C).

(6) A substrate having a thickness of 50 μm
m of a thermosetting epoxy resin sheet at a temperature of 50-150.
Vacuum compression lamination at a pressure of 5 kg / cm ² while raising the temperature to 50 ° C.
(See FIG. 20A). The degree of vacuum during vacuum compression is 10 mmHg.

(7) Next, using a CO ₂ gas laser having a wavelength of 10.4 μm, a beam diameter of 5 mm, a top hat mode,
Under the conditions of a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot, a via hole opening 48 having a diameter of 60 μm is provided in the interlayer resin insulating layer 50 (see FIG. 20B).
The residual resin in the opening 48 is removed using chromic acid.
By providing the copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented,
This improves the connectivity and reliability between the pad 22 and a via hole 60 described later. Further, by providing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, the opening 4 for a via hole having a diameter of 60 μm is formed.
8 can be reliably connected. Here,
Although the resin residue was removed using chromic acid, it is also possible to perform desmear treatment using oxygen plasma.

(8) Next, the surface of the interlayer resin insulation layer 50 is roughened with permanganic acid to form a roughened surface 50α (FIG. 2).
0 (C)).

(9) An electroless plating film 52 is provided on the interlayer resin insulation layer 50 on which the roughened surface 50α is formed (FIG. 21).
(A)). Copper and nickel can be used as the electroless plating. As its thickness, from 0.3 μm
The range of 1.2 μm is good. If it is less than 0.3 μm, it may not be possible to form a metal film on the interlayer resin insulation layer. If the thickness exceeds 1.2 μm, the metal film remains due to the etching, and a short circuit between conductors is easily caused. A plating film was formed under the following plating solution and plating conditions. [Electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyryl 100 mg / l Polyethylene glycol (PEG) 0.10 g / l [Electroless Plating Condition] Dipped at a liquid temperature of 34 ° C. for 40 minutes.

Other than the above, using the same apparatus as in the above-described plasma processing, sputtering using a Ni—Cu alloy as a target was performed at a pressure of 0.6 Pa, a temperature of 80 ° C., and a power of 200
The process is performed under the condition of W for 5 minutes to form a Ni—Cu alloy 52 on the surface of the epoxy-based interlayer resin insulating layer 50. At this time, the thickness of the formed Ni—Cu alloy layer 52 is 0.2 μm.
m (see FIG. 21A).

(10) A commercially available photosensitive dry film is adhered to the substrate 30 that has been subjected to the above processing, a photomask film is placed, and after exposure at 100 mJ / cm ² ,
Develop with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 20 μm. Next, electrolytic plating is performed to form an electrolytic plating film 56 having a thickness of 15 μm.
1 (B)).

(11) Plating resist 54 is made of 5% NaO
After removing with H, the plating film layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and a thickness of 16 μm comprising the plating film layer 52 and the electrolytic plating film 56 is formed. Are formed, and roughened surfaces 58α and 60α are formed with an etching solution containing a cupric complex and an organic acid (see FIG. 21C). In this embodiment, FIG.
As described above with reference to (C), since the upper surface of the core substrate 31 is formed completely smooth, the via hole 60
Accordingly, the connection to the transition layer 38 can be appropriately established. For this reason, it is possible to improve the reliability of the multilayer printed wiring board.

(12) Then, the above steps (6) to (11) are repeated to form a further upper interlayer resin insulation layer 150 and a conductor circuit 158 (including via holes 160) (FIG. 22 ( A)).

(13) Next, the same solder resist composition as that of the first embodiment was applied to the substrate 30 at a thickness of 20 μm, and dried at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes. After that, a 5 mm-thick photomask on which a pattern of the solder resist resist opening is drawn is brought into close contact with the solder resist layer 70, exposed to ultraviolet light of 1000 mJ / cm ² , developed with a DMTG solution, and developed to a thickness of 200 μm.
An opening 71 having a diameter of m is formed (see FIG. 22B).

(14) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed is immersed in the same electroless nickel plating solution as in the first embodiment for 20 minutes, and the thickness of the opening 71 is reduced. A nickel plating layer 72 of 5 μm is formed.
Further, the substrate is immersed in the same electroless gold plating solution as in the first embodiment, and a thickness of 0.0
By forming the gold plating layer 74 of 3 μm, the conductive circuit 1
A solder pad 75 is formed on 58 (see FIG. 22C).

(16) Thereafter, the solder resist layer 70
A solder paste is printed in the opening 71 of the substrate and reflowed at 200 ° C. to form a solder bump.
Finally, the heat sink 30D is divided into individual pieces by dicing or the like to obtain the multilayer printed wiring board 10.
3).

[First Modification] Next, a multilayer printed wiring board according to a first modification of the second embodiment will be described with reference to FIG. In the second embodiment described above, the case where the BGA is provided has been described. The first modification is almost the same as the second embodiment, but as shown in FIG.
The connection is established via a PGA system. Further, in the above-described second embodiment, the via hole is formed by the laser, but in the first modification, the via hole is formed by photoetching.

A method for manufacturing a multilayer printed wiring board according to the first modification will be described with reference to FIG. (4) As in the second embodiment, (1)-(3) a 50 μm thick thermosetting epoxy resin 5
0 (see FIG. 24A).

(5) Next, the photomask film 49 on which the black circle 49a corresponding to the via hole formation position is drawn is placed on the interlayer resin insulation layer 50 and exposed (FIG. 24).
(B)).

(6) Spray development with a DMTG solution and heat treatment are carried out to obtain a via hole opening 4 having a diameter of 85 μm.
24 is provided (FIG. 24C).
reference).

(7) The surface of the interlayer resin insulating layer 50 is roughened with permanganic acid or chromic acid to form a roughened surface 50α (see FIG. 24D). Subsequent steps are the same as those in the above-described second embodiment, and thus description thereof will be omitted.

[Second Modification] Next, a method of manufacturing a multilayer printed wiring board according to a second modification of the second embodiment will be described. In the second embodiment and the first modification described above, the core substrate 30 is formed from the prepreg. On the other hand, in the second modification, a resin substrate obtained by curing the prepreg is fixed to the heat sink 30D by the prepreg.

A method for manufacturing a multilayer printed wiring board according to the second modification will be described with reference to FIG.

(1) The IC chip 20 is attached to the copper foil 30 having both surfaces roughened via the conductive adhesive 29, and is mounted on a stainless (SUS) press plate 100A. Then, an uncured prepreg (0.2 mm) 31α in which a core material such as glass cloth is impregnated with a resin such as BT (bismaleimide triazine) resin or epoxy is placed on the heat sink 30D. Further, a resin substrate (0.4 mm) 31γ obtained by laminating and curing the prepreg is placed on the prepreg 31α (FIG. 26A). Prepreg 31α, resin substrate 3
In 1γ, a through hole 32 is provided at the position of the IC chip 20 in advance.

(4) Stainless steel (SUS) press plate 10
At 0A and 100B, the above-described laminate is pressed from above and below. At this time, the epoxy resin 3
1β exudes and fills the space between the through hole 32 and the IC chip 20 and covers the upper surface of the IC chip 20. Thereby, the upper surfaces of the IC chip 20 and the resin substrate 31γ become completely flat. (FIG. 26 (B)). For this reason, when forming the build-up layer in a step described later, the via hole and the wiring can be appropriately formed, and the reliability of the wiring of the multilayer printed wiring board can be improved.

(5) Thereafter, the core substrate 31 accommodating the IC chip 20 is formed by heating and curing the epoxy resin of the prepreg (FIG. 26C). Subsequent steps are the same as in the second embodiment, and a description thereof will not be repeated.

[Third Embodiment] The structure of a multilayer printed wiring board according to a third embodiment will be described with reference to FIG. First and second described above
In the embodiment, one IC chip is accommodated. On the other hand, as shown in FIG. 32, the multilayer printed wiring board 10 according to the third embodiment includes an IC chip (CPU) 2
0A and an IC chip (cache memory) 20B. Then, as in the first embodiment, an interlayer resin insulation layer 50 and an interlayer resin insulation layer 150 are formed on the core substrate 30, and a via hole 60 and a conductor circuit 58 are formed in the interlayer resin insulation layer 50. In the resin insulating layer 150,
Via holes 160 and conductive circuits 158 are formed.

The IC chips 20A and 20B are covered with a passivation film 24.
A die pad 22 that constitutes an input / output terminal is disposed in the opening. A transition layer 38 is formed on the die pad 22 made of aluminum. The transition layer 38 includes a first thin film layer 33, a second thin film layer 36,
It has a three-layer structure of the thick film 37.

A solder resist layer 70 is provided on interlayer resin insulation layer 150. The conductor circuit 158 below the opening 71 of the solder resist layer 70 is provided with a solder bump 76 for connecting to an external board (not shown) such as a daughter board or a mother board.

In the multilayer printed wiring board 10 of this embodiment,
IC chips 20A and 20B are preliminarily incorporated in the core substrate 30, and a transition layer 38 is provided on the die pad 22 of the IC chips 20A and 20B. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using a lead component or a sealing resin. Further, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer 50 is also flattened and the film thickness becomes uniform. Furthermore, the transition layer can maintain the shape stability even when the upper via hole 60 is formed.

Further, by providing a copper transition layer 38 on the die pad 22, resin residue on the die pad 22 can be prevented. Also, in a later step, the resin may be immersed in an acid, an oxidizing agent, an etching solution, or the like. Discoloration and dissolution of the die pad 22 do not occur even after various annealing processes. This improves the connectivity and reliability between the die pad of the IC chip and the via hole. Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the die pad 22 having a diameter of about 40 μm, a via hole having a diameter of 60 μm can be reliably connected.

In this embodiment, the CPU IC chip 20A
And the cache memory IC chip 20B are individually embedded in the printed wiring board. It is cheaper to produce the IC chips separately, and since each IC chip is located in the vicinity, there is no occurrence of transmission delay or malfunction. Further, even when the design of the printed wiring board is changed, the design of the IC chip itself is not required to be changed, and the degree of freedom of formation can be increased.

The adhesive layer 34 is filled in the recess 32 of the printed wiring board of this embodiment. IC of the recess 32
The chips 20A and 20B can be joined, and the adhesive 34 suppresses the behavior of the IC chips 20A and 20B even after a heat history during a heat cycle or a via hole formation, and the smoothness is maintained. Therefore, peeling or disconnection at a connection portion with a via hole, or interlayer insulating layers 50 and 150
Does not cause cracks. In addition, the reliability can be improved.

Next, a method of manufacturing the multilayer printed wiring board described above with reference to FIG. 32 will be described with reference to FIGS. Here, in the above-described first and second embodiments, the transition layer 38 is formed on the IC chip and then housed in the core substrate. On the other hand, in the third embodiment, the transition layer 38 is formed after the IC chip is accommodated in the core substrate.

(1) First, an insulating resin substrate (core substrate) 30 in which a prepreg obtained by impregnating a resin such as epoxy into a core material such as glass cloth is used as a starting material (FIG. 27).
(A)). Next, a recess 32 for accommodating an IC chip is formed on one surface of the core substrate 30 by counterboring.
(B)). Here, the concave portion is formed by counterboring, but a core substrate having an accommodating portion can be formed by laminating an insulating resin substrate having an opening and a resin insulating substrate having no opening.

(2) Thereafter, an adhesive material 34 is applied to the recess 32 using a printing machine. At this time, besides coating,
Potting may be performed. Next, the IC chip 20
A and 20B are placed on the adhesive material 34 (FIG. 27C).
reference).

(3) Then, the IC chips 20A and 20B
Is pressed or hit to completely accommodate the inside of the concave portion 32 (see FIG. 27D). Thereby, the core substrate 3
0 can be smoothed.

(4) Thereafter, the IC chips 20A and 20B
The conductive first thin film layer 33 is formed on the entire surface of the core substrate 30 in which is accommodated (FIG. 27E). As the metal, nickel, zinc, chromium, cobalt, titanium, gold, tin, copper and the like are preferable. In particular, using nickel, chromium, and titanium
Suitable for film formation and electrical characteristics. As the thickness,
It is preferred that the thickness be formed between 0.001 and 2.0 μm. In the case of chromium, a thickness of 0.1 μm is desirable.

The first thin film layer 33 covers the die pad 22 so that the adhesion between the transition layer and the IC chip at the interface between the die pad 22 can be enhanced. Also,
By coating the die pad 22 with these metals, it is possible to prevent moisture from entering the interface, prevent the die pad from dissolving and corroding, and improve reliability. In addition, the first thin film layer 33 allows connection with an IC chip by a lead-free mounting method. Here, it is desirable to use chromium or titanium in order to prevent moisture from entering the interface.

(5) A second thin film layer 36 is formed on the first thin film layer 33 by sputtering, vapor deposition, or electroless plating (FIG. 28A). Nickel as the metal,
Copper, gold, silver and the like. It is preferable to use copper because the electrical characteristics, economy, and the conductor layer, which is a build-up formed later, are mainly copper.

The reason for providing the second thin film layer is that the first thin film layer cannot take a lead for electrolytic plating for forming a thick layer described later. Second thin film layer 3
Reference numeral 6 is used as a thick lead. The thickness is preferably in the range of 0.01 to 5 μm. 0.01 μm
If it is less than 5 μm, it may not serve as a lead, and if it exceeds 5 μm, the lower first thin film layer may be shaved more to form a gap at the time of etching, making it easier for moisture to enter,
This is because the reliability decreases. The optimal thickness is 0.1-
3 μm.

(6) Thereafter, a resist is applied, exposed,
Develop and provide a plating resist 35 so as to provide an opening above the die pad of the IC chip, apply electrolytic plating,
An electrolytic plating film (thick film) 37 is provided (FIG. 28).
(B)). Thick film is made of nickel, copper, gold, silver, zinc,
It can be formed of iron.

After the plating resist 35 is removed, the electroless second thin film layer 36 and the first thin film layer 3 under the plating resist 35 are removed.
The transition layer 38 is formed on the die pad 22 of the IC chip by removing 3 by etching.
(C)). Here, the transition layer is formed by a plating resist. However, after an electrolytic plating film is uniformly formed on the electroless second thin film layer 36, an etching resist is formed, and exposure and development are performed to obtain portions other than the transition layer. It is also possible to form a transition layer on the die pad of the IC chip by exposing the metal of the above to the etching. The thickness of the electrolytic plating film is preferably in the range of 1 to 20 μm. If the thickness is larger than that, an undercut occurs at the time of etching, and a gap may be generated at the interface between the formed transition layer and the via hole.

(7) Next, a roughened surface 38α is formed by spraying an etching solution onto the substrate by spraying and etching the surface of the transition layer 38 (FIG. 28).
(D)). The roughened surface can be formed by using electroless plating or oxidation-reduction treatment. Transition layer 38
Has a three-layer structure of a first thin film layer 33, a second thin film layer 36, and a thick film 37.

(8) A substrate having a thickness of 50 μm
m of a thermosetting epoxy resin sheet at a temperature of 50-150.
Vacuum compression lamination at a pressure of 5 kg / cm ² while raising the temperature to 0 ° C., and an interlayer resin insulation layer 5 mainly composed of a thermosetting resin.
0 is provided (see FIG. 29A). The degree of vacuum during vacuum compression is 10 mmHg.

(9) Next, using a CO ₂ gas laser having a wavelength of 10.4 μm, a beam diameter of 5 mm, a top hat mode,
Under the conditions of a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot, a via hole opening 48 having a diameter of 80 μm is provided in the interlayer resin insulating layer 50 (see FIG. 29B).
The residual resin in the opening 48 is removed using chromic acid.
By providing the transition layer 38 made of copper on the die pad 22, resin residue on the die pad 22 can be prevented, thereby improving the connectivity and reliability between the die pad 22 and via holes 60 described later. In addition, 40μ
By interposing the transition layer 38 having a diameter of 60 μm or more on the die pad 22 having a diameter of about m, the via hole opening 48 having a diameter of 60 μm can be reliably connected. Here, the resin residue is removed using permanganic acid, but it is also possible to perform desmear treatment using oxygen plasma. Here, the opening 48 is formed by a laser.
Is formed, but it is also possible to form an opening by exposure and development processing.

(10) A roughened surface 50α is formed on the interlayer resin insulating layer 50 using an acid or an oxidizing agent (FIG. 29).
(C)). The rough surface may be formed with an average roughness of 1 to 5 μm.

(11) An electroless plating film 52 is provided on the interlayer resin insulating layer 50 on which the roughened surface 50α is formed (FIG. 30).
(A)). Copper and nickel can be used as the electroless plating. As its thickness, from 0.3 μm
The range of 1.2 μm is good. If it is less than 0.3 μm, it may not be possible to form a metal film on the interlayer resin insulation layer. If the thickness exceeds 1.2 μm, the metal film remains due to the etching, and a short circuit between conductors is easily caused. A plating film was formed under the following plating solution and plating conditions. [Electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyryl 100 mg / l Polyethylene glycol (PEG) 0.10 g / l [Electroless Plating Condition] Dipped at a liquid temperature of 34 ° C. for 40 minutes.

(12) A commercially available photosensitive dry film is adhered to the substrate 30 having been subjected to the above processing, a chrome glass mask is placed thereon, and the substrate is exposed at 40 mJ / cm ² .
Develop with 8% sodium carbonate to provide a plating resist 54 having a thickness of 25 μm. Next, apply electrolytic plating,
An electrolytic plating film 56 having a thickness of 18 μm is formed.
(B)).

(13) The plating resist 54 is made of 5% NaO
After removing with H, the plating film layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and a thickness of 16 μm comprising the plating film layer 52 and the electrolytic plating film 56 is formed. Are formed, and the roughened surfaces 58α and 60α are formed using an etching solution containing a cupric complex and an organic acid (see FIG. 30C). The roughened surface can be formed by using electroless plating or oxidation-reduction treatment.

(14) Next, the above steps (9) to (13) are repeated to form a further upper interlayer resin insulating layer 150 and a conductor circuit 158 (including via holes 160) (FIG. 31 ( A)).

(15) Next, the same solder resist composition as that of the first embodiment was applied to the substrate 30 at a thickness of 30 μm, and dried at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes. After that, a 5 mm-thick photomask on which the pattern of the opening of the solder resist resist is drawn is brought into close contact with the solder resist layer 70, exposed to ultraviolet rays of 1000 mJ / cm ² , developed with a DMTG solution, and developed with a DMTG solution.
An opening 71 of 60 μm is formed (see FIG. 31B).

(16) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 has been formed is immersed in the same electroless nickel plating solution as in the first embodiment, and the opening 71 has a thickness of 5 μm. A nickel plating layer 72 is formed. further,
The substrate is immersed in the same electroless gold plating solution as in the first embodiment to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72. Is formed (see FIG. 31C).

(18) Thereafter, the solder resist layer 70
A solder paste is printed in the opening 71 of the substrate and reflowed at 200 ° C. to form a solder bump.
Thereafter, the printed wiring board 10 is obtained by dividing the substrate by dicing or the like (see FIG. 32). [First Modification] Next, a printed wiring board according to a first modification of the third embodiment will be described with reference to FIGS. FIG. 34 shows a printed wiring board according to a first modification. The printed wiring board of the first modification is the same as the printed wiring board of the third embodiment described above with reference to FIG. However, in the third embodiment described above, the I
After accommodating the C chip, the transition layer 38 was formed. On the other hand, in the first modified example, a transition layer 38 is formed on an IC chip as in the first and second embodiments and then housed in a core substrate.

Subsequently, the semiconductor device (IC chip) 20
A method of manufacturing a multilayer printed wiring board according to a first modification shown in FIG. 34, in which A and 20B are housed in through holes of a core substrate, will be described with reference to FIG. Here, a transition layer 38 is provided on the IC chips 20A and 20B in the same manner as in the first to fourth manufacturing methods described above.

(1) First, an insulating resin substrate (core substrate) 30 in which a prepreg in which a core material such as glass cloth is impregnated with a resin such as epoxy is laminated is used as a starting material (FIG. 33).
(A)). Next, a recess 32 for accommodating an IC chip is formed on one surface of the core substrate 30 by counterboring.
(B)). Here, the concave portion is formed by counterboring, but a core substrate having an accommodating portion can be formed by laminating an insulating resin substrate having an opening and a resin insulating substrate having no opening.

(2) Thereafter, an adhesive material 34 is applied to the recess 32 using a printing machine. At this time, besides coating,
Potting may be performed. Next, the IC chip 20
A and 20B are placed on the adhesive material 34 (FIG. 33C).
reference).

(3) Then, the IC chips 20A and 20B
Is pressed or hit to completely house the recess 32 (see FIG. 33D). Thereby, the core substrate 3
0 can be smoothed. The subsequent steps are described in FIGS.
Since this is the same as the third embodiment described above with reference to FIG. 31, the description will be omitted.

[0168]

According to the present invention, by providing the transition layer on the die pad, resin residue on the pad can be prevented, and the connectivity and reliability between the die pad and the via hole are improved. In addition, a multi-layer printed wiring board including a semiconductor element is manufactured for multi-cavity production. Then, it is cut into individual pieces to obtain individual multilayer printed wiring boards. For this reason, a highly reliable multilayer printed wiring board can be efficiently manufactured. Furthermore, compared to the conventional IC chip mounting method, the wiring length from the IC chip to the substrate to the external substrate can be reduced, and the effect of reducing the loop inductance can be obtained.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C show a first example of the first embodiment; FIGS.
FIG. 9 is a manufacturing process diagram of the semiconductor element according to the manufacturing method of FIG.

FIGS. 2A, 2B, and 2C show a first embodiment of the first embodiment.
FIG. 9 is a manufacturing process diagram of the semiconductor element according to the manufacturing method of FIG.

FIGS. 3A and 3B are manufacturing process diagrams of the semiconductor device according to the first manufacturing method of the first embodiment.

FIG. 4A is a plan view of a silicon wafer according to the first manufacturing method of the first embodiment, and FIG. 4B is a plan view of a singulated semiconductor element.

FIGS. 5A, 5B, 5C, and 5D are manufacturing process diagrams of a semiconductor device according to a second manufacturing method of the first embodiment. FIGS.

FIGS. 6A, 6B, and 6C show a second embodiment of the first embodiment.
FIG. 9 is a manufacturing process diagram of the semiconductor element according to the manufacturing method of FIG.

FIGS. 7A and 7B are manufacturing process diagrams of a semiconductor device according to a second manufacturing method of the first embodiment.

FIGS. 8A, 8B, 8C, and 8D are manufacturing process diagrams of a semiconductor device according to a third manufacturing method of the first embodiment.

FIGS. 9A, 9B, 9C, and 9D are manufacturing process diagrams of a semiconductor device according to a fourth manufacturing method of the first embodiment.

FIGS. 10A, 10B, and 10C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 11A, 11B, and 11C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 12A, 12B, and 12C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 13A, 13B, and 13C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 14A, 14B, and 14C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 15 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 16 (A), (B), (C), and (D) are manufacturing process diagrams of a multilayer printed wiring board according to a first modification of the first embodiment of the present invention.

FIG. 17 is a sectional view of a multilayer printed wiring board according to a first modification of the first embodiment of the present invention.

FIGS. 18 (A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment of the present invention.

FIGS. 19 (A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment of the present invention.

FIGS. 20A, 20B, and 20C are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment of the present invention.

FIGS. 21 (A), (B), and (C) are manufacturing process diagrams of a multilayer printed wiring board according to a second embodiment of the present invention.

FIGS. 22 (A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment of the present invention.

FIG. 23 is a sectional view of a multilayer printed wiring board according to a second embodiment of the present invention.

FIGS. 24A, 24B, 24C, and 24D are manufacturing process diagrams of a multilayer printed wiring board according to a first modification of the second embodiment; FIGS.

FIG. 25 is a sectional view of a multilayer printed wiring board according to a first modification of the second embodiment.

FIGS. 26A, 26B and 26C are manufacturing process diagrams of a multilayer printed wiring board according to a second modification of the second embodiment of the present invention.

FIG. 27 (A), (B), (C), (D), (E)
FIG. 9 is a manufacturing process diagram of the multilayer printed wiring board according to the third embodiment of the present invention.

FIGS. 28 (A), (B), (C), and (D) are manufacturing process diagrams of the multilayer printed wiring board according to the third embodiment of the present invention.

FIGS. 29 (A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the third embodiment of the present invention.

FIGS. 30A, 30B, and 30C are manufacturing process diagrams of a multilayer printed wiring board according to a third embodiment of the present invention.

FIGS. 31 (A), (B), and (C) are manufacturing process diagrams of a multilayer printed wiring board according to a third embodiment of the present invention.

FIG. 32 is a sectional view of a multilayer printed wiring board according to a third embodiment.

FIGS. 33 (A), (B), (C), and (D) are manufacturing process diagrams of a multilayer printed wiring board according to a first modification of the third embodiment of the present invention.

FIG. 34 is a sectional view of a multilayer printed wiring board according to a first modification of the third embodiment.

[Explanation of symbols]

 Reference Signs List 20 IC chip (semiconductor element) 20A IC chip (CPU) 20B IC chip (cache memory) 22 Die pad 24 Passivation film 30 Core substrate 30D Heat sink 31 Core substrate 32 Through hole 36 Resin layer 38 Transition layer 50 Interlayer resin insulation layer 58 Conductor circuit Reference Signs List 60 via hole 70 solder resist layer 76 solder bump 90 daughter board 96 conductive connection pin 97 conductive adhesive 120 IC chip 150 interlayer resin insulating layer 158 conductive circuit 160 via hole

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H01L 23/12 NP 7/20 25/04 Z F term (Reference) 5E322 AA11 AB06 AB09 EA11 FA04 FA06 5E346 AA02 AA12 AA15 AA32 AA43 AA51 BB16 BB20 CC08 CC09 CC32 CC37 DD02 DD03 DD22 DD33 EE09 EE31 EE33 EE35 FF03 FF04 FF07 FF10 FF12 FF45 GG15 GG17 GG26 GG27 GG28 HH02H11

Claims (6)

[Claims] 1. A method for manufacturing a multilayer printed wiring board incorporating a semiconductor element, comprising at least the following steps (a) to (e): (a) forming a plurality of through holes formed in a core substrate; A step of accommodating a plurality of semiconductor elements; (b) a step of laminating a core substrate accommodating the semiconductor elements and a resin plate with a sheet impregnating an uncured resin into a core material interposed therebetween; and (c) the core substrate. And (d) forming a build-up layer on the upper surface of the core substrate. (E) cutting the core substrate to obtain individual multilayer printed wiring boards. 2. A method for manufacturing a multilayer printed wiring board incorporating a semiconductor element, comprising at least the following steps (a) to (f): (a) forming a transition layer on a die pad of the semiconductor element (B) accommodating a plurality of the semiconductor elements in a plurality of through-holes formed in the core substrate; (c) forming a core substrate accommodating the semiconductor element and a resin plate using an uncured resin as a core material. (D) pressurizing the core substrate and the resin plate; (e) forming a build-up layer on the upper surface of the core substrate; (f) removing the core substrate. A step of obtaining individual multilayer printed wiring boards by cutting. 3. A method of manufacturing a multilayer printed wiring board incorporating a semiconductor element, comprising at least the following steps (a) to (e): (a) a plurality of semiconductors mounted on a heat sink made of metal or ceramic; (B) placing a sheet having a through hole corresponding to the semiconductor element and impregnating the core material with an uncured resin on the heat sink; (c) pressing the sheet under pressure Forming a core substrate; (d) forming a build-up layer on the upper surface of the core substrate; (e) cutting the core substrate to obtain individual multilayer printed wiring boards. 4. A method for manufacturing a multilayer printed wiring board incorporating a semiconductor element, comprising at least the following steps (a) to (f): (a) forming a transition layer on a die pad of the semiconductor element (B) mounting a plurality of the semiconductor elements on a heat sink made of metal or ceramic; (c) a sheet having through holes corresponding to the semiconductor elements and impregnating a core material with an uncured resin; (D) pressing the sheet to form a core substrate; (e) forming a build-up layer on the upper surface of the core substrate; (f) cutting the core substrate. To obtain individual multilayer printed wiring boards. 5. A method for manufacturing a multilayer printed wiring board incorporating a semiconductor element, comprising at least the following steps (a) to (d): (a) forming a plurality of through holes formed in a core substrate; (B) forming a transition layer on a die pad of the semiconductor element; (c) forming a build-up layer on an upper surface of the core substrate; and (d) forming the core substrate. A step of obtaining individual multilayer printed wiring boards by cutting. 6. The production of a multilayer printed wiring board incorporating a semiconductor element according to claim 1, wherein said individual multilayer printed wiring board includes a plurality of semiconductor elements. Method.