JP4863546B2 - Capacitor-embedded printed wiring board and manufacturing method of capacitor-embedded printed wiring board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  For printed wiring boards on which electronic components such as IC chips are placed, especially with built-in capacitorsBuilt-in capacitorIt also relates to printed wiring boards.
[0002]
[Prior art]
Currently, in a printed wiring board for a package substrate, a chip capacitor is sometimes surface-mounted for the purpose of facilitating power supply to an IC chip.
[0003]
Since the reactance of the wiring from the chip capacitor to the IC chip depends on the frequency, a sufficient effect cannot be obtained even if the chip capacitor is surface-mounted as the driving frequency of the IC chip increases. For this reason, the present applicant has proposed, in Japanese Patent Application No. 11-248311, a technique of forming a recess in the core substrate and accommodating a chip capacitor in the recess. Moreover, as a technique for embedding a capacitor in a substrate, JP-A-6-326472, JP-A-7-263619, JP-A-10-256429, JP-A-11-45955, JP-A-11-126978, JP-A-11- No. 31868 etc.
[0004]
Japanese Patent Application Laid-Open No. 6-326472 discloses a technique of embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, it is possible to reduce power supply noise, eliminate the need for a space for mounting a chip capacitor, and reduce the size of the insulating substrate. Japanese Patent Application Laid-Open No. 7-263619 discloses a technique for embedding a capacitor in a substrate such as ceramic or alumina. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.
[0005]
[Problems to be solved by the invention]
However, the above-mentioned Japanese Patent Laid-Open Nos. 6-326472 and 7-263619 cannot reduce the distance from the IC chip to the capacitor so much, and in the higher frequency region of the IC chip, the inductance is required as it is currently required. Could not be reduced. In particular, in multilayer build-up wiring boards made of resin, disconnection occurs between the chip capacitor terminals and vias due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and interlayer resin insulation layer. Peeling occurs between the capacitor and the interlayer resin insulation layer, and cracks occur in the interlayer resin insulation layer, and high reliability cannot be achieved over a long period of time.
[0006]
On the other hand, in the invention of Japanese Patent Application No. 11-248311, when there is a displacement in the position of the capacitor, the connection between the capacitor terminal and the via cannot be made accurately, and the power supply from the capacitor to the IC chip may not be possible. was there.
[0007]
Moreover, the multilayer buildup wiring board used as a package substrate builds up each interlayer resin insulating layer through the following steps. First, an interlayer insulating resin is applied, exposed and developed by a roll coater or printing to form a via hole opening for interlayer conduction, and an interlayer resin insulating layer is formed through UV curing and main curing. Further, a catalyst such as palladium is attached to the roughened surface obtained by roughening the interlayer insulating layer with an acid or an oxidizing agent. Then, a thin electroless plating film is formed, a pattern is formed on the plating film with a dry film, and after thickening by electrolytic plating, the dry film is peeled off with alkali and etched to create a conductor circuit. . That is, it is necessary to repeat the above-described process every time one layer is formed. When the number of layers increases, the number of processes increases and the yield decreases.
[0008]
  The present invention has been made to solve the above-described problems, and its purpose is to incorporate a capacitor and improve connection reliability.Built-in capacitorPrinted wiring boards andBuilt-in capacitorIt is providing the manufacturing method of a printed wiring board.
[0009]
  In addition, the present invention can reduce the loop inductance and reduce the number of interlayer resin insulation layers.Built-in capacitorPrinted wiring board andBuilt-in capacitorIt is providing the manufacturing method of a printed wiring board.
[0010]
[Means for Solving the Problems]
  In order to solve the above-described problem, in Claim 1, a capacitor-embedded printed wiring board in which a resin insulating layer and a conductor circuit are laminated on a core substrate that houses a capacitor in a recess,
  A through hole is formed at the bottom of the concave portion of the core substrate,
  On the surface of the core substrate, a conductor circuit that closes the opening of the through hole is formed,
  Of the capacitor accommodated in the recess.Copper coatedA terminal and a conductor circuit that closes the through hole are disposed in the through hole.Composed of copperConnected through conductive bumps,
  The resin insulation layer and the conductor circuit are laminated on the through hole side of the core substrate,
  Solder bumps are formed on the surface of the through hole side,
  The technical feature is that the solder bump is connected to the conductor circuit.
[0011]
According to the first aspect, since the capacitor is arranged in the printed wiring board, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. Moreover, since the terminal of the capacitor and the conductor circuit are connected via the conductive bump in the through hole of the core substrate, high connection reliability can be achieved. Moreover, even if a reliability test such as heat cycle conditions is performed, peeling or cracking between the capacitor and the conductor circuit is not induced.
[0012]
Since the capacitor can be accommodated in the core substrate and the distance between the IC chip and the capacitor is shortened, the loop inductance of the printed wiring board can be reduced. Further, since the core substrate is formed by laminating a plurality of resin substrates on which conductor circuits are formed, the wiring density in the core substrate is increased, and the number of interlayer resin insulating layers can be reduced.
[0013]
It means a circuit formed by a build-up method in which an interlayer resin insulation layer is provided on a core substrate, and via holes or through holes are provided in the interlayer resin insulation layer to form a conductor circuit as a conductive layer. For them, either a semi-additive method or a full additive method can be used.
[0014]
It is desirable to fill the voids with resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if stress originating from the capacitor is generated, it can be relaxed by the filled resin. The resin also has an effect of reducing adhesion and migration between the capacitor and the core substrate.
[0015]
  Further, in claim 1Built-in capacitorThe printed wiring board is connected to a capacitor accommodated in a core substrate by providing a semiconductor element as an IC on the surface layer by flip chip mounting. At that time, it is transmitted in the order of semiconductor element-conductor circuit-conductive bump-capacitor. Conductive bumps improve electrical connectivity and board containment. In this case, the accommodation position of the capacitor is preferably directly under the semiconductor element that is an IC.
[0016]
Furthermore, electrical connection may be made from the lower surface of the capacitor. In this case, connection may be made with conductive bumps in the same manner as the upper surface of the capacitor, or it may be directly connected to the terminal portion of the capacitor with a conductor layer. A plurality of capacitors may be accommodated in one recess.
[0017]
The conductive bump suggests a plating film, solder paste, conductive paste, or insulating resin impregnated with metal particles. The plating film is formed by metal plating of nickel, copper, silver, gold, titanium, tin or the like. As the solder, alloys such as Sn / Pb, Sn / Sb, Sn / Ag, and Sn / Ag / Cu can be used. As the conductive paste, a conductive paste whose main component is conductive metal particles such as gold, silver, copper, and iron can be used. What has electroconductivity and adhesiveness, such as what impregnated the metal particle to resin, can be used.
[0018]
According to the second aspect of the present invention, since the conductive bump is made of the pressure contact paste, high connection reliability between the capacitor terminal and the conductor circuit can be achieved.
[0019]
The conductive bump is formed by metal plating of nickel, copper, silver, gold, titanium or the like. These may be formed of two or more layers. In addition, solder (Sn / Pb, Sn / Sb, Sn / Ag, Sn / Ag / Cu), conductive paste (gold, silver, copper or other metal particles as the main paste was made into a paste. Or conductive materials such as those obtained by impregnating metal particles in an insulating resin such as an epoxy resin or a phenol resin. That is, a material having both conductivity and adhesiveness can be used, and the capacitor can be accommodated and the capacitor can be electrically connected.
[0020]
  In claim 3,coreSince the substrate is made by impregnating the core material with resin, the core substrate can have high strength.
[0021]
According to the fourth aspect, since a plurality of capacitors are accommodated in the core substrate, the capacitors can be highly integrated.
[0022]
According to the fifth aspect, in addition to the capacitor accommodated in the substrate, the capacitor is disposed on the surface. Since the capacitor is accommodated in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance can be reduced, and the power can be supplied instantaneously. Since the capacitor is disposed, a large-capacity capacitor can be attached, and a large amount of power can be easily supplied to the IC chip.
[0023]
According to the sixth aspect of the present invention, since the capacitance of the surface capacitor is equal to or greater than the capacitance of the inner layer capacitor, there is no shortage of power supply in the high frequency region, and a desired IC chip operation is ensured.
[0024]
According to the seventh aspect, since the inductance of the capacitor on the surface is equal to or larger than the inductance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and a desired operation of the IC chip is secured.
[0025]
According to the eighth and ninth aspects, electrical connection is made to the electrode of the chip capacitor formed with the metal film by a via hole formed by plating. Here, the electrode of the chip capacitor is made of metallization and has irregularities on the surface, but the surface is smoothed by the metal film, and it is difficult to form a gap when connected to the conductive bump. Therefore, electrical connectivity is improved. Further, even if a reliability test is performed, peeling or cracking starting from the connected portion is not caused.
Moreover, even if a via hole is formed for electrical connection from the back side of the capacitor, when a through hole is formed in the resin coated on the electrode, no resin residue remains, and the via hole and the electrode Connection reliability can be improved. Furthermore, since via holes are formed by plating on the plated electrodes, the connectivity between the electrodes and via holes is high, and disconnection between the electrodes and via holes may occur even when a heat cycle test is performed. Absent.
[0026]
The metal film of the capacitor electrode is preferably provided with any one of copper, nickel, and a noble metal. This is because a layer of tin, zinc or the like in the built-in capacitor tends to induce migration at the connection portion with the via hole. Therefore, the occurrence of migration can also be prevented.
[0027]
Further, the surface of the chip capacitor may be roughened. Thereby, the adhesiveness between the ceramic chip capacitor and the resin interlayer resin insulation layer is high, and even when the heat cycle test is performed, the interlayer resin insulation layer does not peel off at the interface.
[0028]
According to the tenth aspect, the thermal expansion coefficient of the insulating adhesive is set smaller than that of the core substrate, that is, close to that of the capacitor made of ceramic. For this reason, in the heat cycle test, even if an internal stress occurs due to a difference in thermal expansion coefficient between the core substrate and the capacitor, cracks, peeling, and the like hardly occur in the core substrate, and high reliability can be achieved.
[0029]
According to the eleventh aspect, at least a part of the chip capacitor electrode coating layer is exposed and accommodated in the printed wiring board, and the electrode exposed from the coating layer is electrically connected. At this time, it is desirable that the metal exposed from the coating layer is mainly composed of Cu. This is because the connection resistance can be reduced.
[0030]
According to the twelfth aspect, since the chip capacitor in which the electrode is formed on the inner side of the outer edge is used, the external electrode can be made large even when conducting through the conductive bump, and the allowable range of alignment is widened.
[0031]
According to the thirteenth aspect, since a capacitor having electrodes formed in a matrix is used, a large chip capacitor can be easily accommodated in the core substrate. As a result, the capacitance can be increased, and the electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is hardly warped.
[0032]
In the fourteenth aspect, a plurality of chip capacitors may be connected to the capacitor. Thereby, the capacitance can be adjusted as appropriate, and the IC chip can be operated appropriately.
[0033]
In the fifteenth aspect, the conductive paste is applied to the electrode of the capacitor, and the electrode to which the conductive paste is applied is electrically connected by plating. Since the conductive paste is coated, the surface of the electrode becomes smooth, and when the interlayer resin insulation layer is provided on the electrode and the via hole opening is formed by the laser in the manufacturing process, there is no resin residue. Connection reliability when via holes are formed by plating can be improved.
[0034]
  The method of manufacturing a printed wiring board with a built-in capacitor according to claim 17 is characterized by including at least the following steps (a) to (g):
(A) forming a recess in the core substrate and a through hole in the bottom of the recess;
(B) forming a conductor circuit on the surface of the core substrate that closes the opening of the through hole;
(C) disposing a resin in the concave portion of the core substrate;
(D) CapacitorCopper coatedTerminalComposed of copperDisposing conductive bumps;
(E) The step of accommodating the capacitor in the recess of the core substrate and making a connection with a conductor circuit that closes the opening of the through hole via the conductive bump:
(F) A step of laminating a resin insulating layer and a conductor circuit on the through hole side of the core substrate:
(G) A step of forming solder bumps connected to the conductor circuit on the surface on the through hole side.
[0035]
  Claim 17Then, since the capacitor is arranged in the printed wiring board, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. Moreover, since the terminal of the capacitor and the conductor circuit are connected via the conductive bump in the through hole of the core substrate, high connection reliability can be achieved.
[0036]
  Claim 18Then, ultrasonic vibration is given in the process of making a connection with the conductor circuit that closes the opening of the through hole via the conductive bump. For this reason, even if the capacitor is placed after placing the resin in the recess of the core substrate, high connection reliability between the capacitor terminal and the conductor circuit can be achieved.
[0040]
In addition, it is desirable to fill the resin in the concave portion of the core substrate. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if stress originating from the capacitor is generated, it can be relaxed by the filled resin. The resin also has an effect of reducing adhesion and migration between the capacitor and the core substrate.
[0041]
The surface of the chip capacitor can be roughened. Thereby, the adhesiveness between the ceramic chip capacitor and the resin interlayer resin insulation layer is high, and even when the heat cycle test is performed, the interlayer resin insulation layer does not peel off at the interface.
[0042]
Further, it is preferable to form copper around the terminals of the capacitor by plating or the like. As a result, migration does not occur in the built-in capacitor. Further, peeling and cracking from the resin filling the capacitor are eliminated, and the accommodation property is improved. Therefore, there is no deterioration in electrical characteristics.
[0043]
DETAILED DESCRIPTION OF THE INVENTION
  Embodiments of the present invention will be described below with reference to the drawings.
  First, according to the first embodiment of the present invention.Built-in capacitorThe configuration of the printed wiring board will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state in which the IC chip 90 is mounted on the printed wiring board 10 shown in FIG.
[0044]
As shown in FIG. 7, the printed wiring board 10 includes a chip capacitor 20, a core substrate 30 that houses the chip capacitor 20, an interlayer resin insulating layer 40 that forms the buildup layers 80 </ b> A and 80 </ b> B, and an interlayer resin insulating layer 60. Become. The core substrate 30 is formed with a recess 30a for accommodating the chip capacitor 20 and through holes 30b for accommodating the conductive bumps 31 for connecting the first and second terminals 21 and 22 of the chip capacitor 20. Has been. A via hole 46 and a conductor circuit 48 are formed in the interlayer resin insulation layer 40, and a via hole 66 and a conductor circuit 68 are formed in the interlayer resin insulation layer 60.
[0045]
As shown in FIG. 8, bumps 76 for connecting to pads 92S1, 92S2, 92P1, and 92P2 of the IC chip 90 are formed in the via holes 66 of the upper buildup layer 80A. On the other hand, in the via hole 66 of the lower buildup layer 80B, bumps 76 for connecting to the pads 96S1, 96S2, 96P1, and 96P2 of the daughter board 94 are disposed. A through hole 36 is formed in the core substrate 30.
[0046]
As shown in FIG. 9A, the chip capacitor 20 includes a first terminal 21, a second terminal 22, and a dielectric 23 sandwiched between the first and second terminals. A plurality of first conductive films 24 connected to the first terminal 21 side and a plurality of second conductive films 25 connected to the second terminal 22 side are arranged to face each other. The first terminal 21 and the second terminal 22 are made of a metallized layer 26 formed by firing, and the metallized layer 26 is covered with a metal coating 29 such as copper plating. The metal coating 29 can improve electrical connectivity with the conductive bumps 31 and can prevent migration. In addition, as shown in FIG. 9B, the metallized layer 26 can be used without being covered with the metal coating 29.
[0047]
The signal pad 92S2 of the IC chip 90 shown in FIG. 8 is connected to the signal pad 96S2 of the daughter board 94 via the bump 76-conductor circuit 68-via hole 66-through hole 36-via hole 66-bump 76. It is connected. On the other hand, the signal pad 92S1 of the IC chip 90 is connected to the signal pad 96S1 of the daughter board 94 via the bump 76-via hole 66-through hole 36-via hole 66-bump 76.
[0048]
The power supply pad 92P1 of the IC chip 90 is connected to the first terminal 21 of the chip capacitor 20 via the bump 76, the via hole 66, the conductor circuit 48, and the via hole 46. On the other hand, the power supply pad 96P1 of the daughter board 94 is connected to the first terminal 21 of the chip capacitor 20 via the bump 76-via hole 66-through hole 36-conductor circuit 48-via hole 46.
[0049]
The power supply pad 92P2 of the IC chip 90 is connected to the second terminal 22 of the chip capacitor 20 via the bump 76-via hole 66-conductor circuit 48-via hole 46. On the other hand, the power supply pad 96P2 of the daughter board 94 is connected to the second terminal 22 of the chip capacitor 20 via the bump 76-via hole 66-through hole 36-conductor circuit 48-via hole 46.
[0050]
In the printed wiring board 10 of the present embodiment, the chip capacitor 20 is disposed immediately below the IC chip 90, so the distance between the IC chip and the capacitor is shortened, and power can be instantaneously supplied to the IC chip side. Become. That is, the loop length that determines the loop inductance can be shortened.
[0051]
Further, in the present embodiment, the first and second terminals 21 and 22 of the chip capacitor 20 housed in the recess 30a of the core substrate 30 and the via holes 46 formed in the interlayer resin insulating layer 40 are connected to the conductive bumps. 31 and the conductor circuit 34 are connected, so that high connection reliability can be achieved.
[0052]
Further, a through hole 36 is provided between the chip capacitor 20 and the chip capacitor 20 so that the signal line does not pass through the chip capacitor 20. For this reason, it is possible to prevent reflection due to impedance discontinuity due to the high dielectric material generated when the capacitor is passed and propagation delay due to passage through the high dielectric material.
[0053]
Further, an external board (daughter board) 94 connected to the back side of the printed wiring board and the first terminal 21 and the second terminal 22 of the capacitor 20 are via holes 46 provided in the interlayer resin insulating layer 40 on the IC chip side. And connected through a through hole 36 formed in the core substrate 30.
[0054]
In the present embodiment, as shown in FIG. 9A, a roughened layer 23a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. For this reason, the adhesion between the ceramic chip capacitor 20 and the resin interlayer resin insulation layer 40 is high, and the interlayer resin insulation layer 40 does not peel off at the interface even when the heat cycle test is performed. The roughened layer 23a can be formed by polishing the surface of the chip capacitor 20 after firing, or by performing a roughening treatment before firing. In this embodiment, the surface of the capacitor is roughened to improve the adhesion with the resin. Alternatively, a silane coupling treatment can be applied to the surface of the capacitor. Further, the capacitor may not have a roughened layer.
[0055]
In this embodiment, as shown in FIG. 7, a resin filler 32 is interposed between the side surface of the recess 30 a of the core substrate 30 and the chip capacitor 20. Here, the thermal expansion coefficient of the resin filler 32 is set to be smaller than that of the core substrate 30 and the interlayer resin insulating layer 40, that is, close to the chip capacitor 20 made of ceramic. For this reason, in the heat cycle test, even if an internal stress occurs due to the difference in thermal expansion coefficient between the core substrate and the interlayer resin insulation layer 40 and the chip capacitor 20, the core substrate 30 and the interlayer resin insulation layer 40 are cracked and peeled. Etc., and high reliability can be achieved. In addition, migration can be prevented.
[0056]
Next, a method for manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.
(1) A recess 30a is formed in the core substrate 30 by counterboring (FIG. 1A). Here, although the concave portion is formed by counterboring, a core substrate having a concave portion can be formed by stacking a prepreg having a through hole and a prepreg having no through hole. Or the core board | substrate which has a recessed part can be formed by injection molding. As the core substrate 30, a laminated plate formed by laminating a prepreg in which a core material such as glass cloth is impregnated with an epoxy resin can be used. In addition to epoxies, those generally used in printed wiring boards such as those containing reinforcing materials such as BT, phenolic resin or glass cloth can be used. It is also possible to use a resin substrate that does not have a core material such as glass cloth. However, a substrate such as ceramic or AIN cannot be used as the core substrate. This is because the substrate has poor external formability and cannot accommodate a capacitor, and even if it is filled with resin, voids are generated. Since the resin substrate has a melting point of 300 ° C. or lower, if a temperature exceeding 350 ° C. is applied, dissolution, softening or carbonization occurs.
[0057]
(2) A through hole 30b is formed in the bottom of the recess 30a by drilling or laser (FIG. 1B). In some cases, the opened portion may be subjected to desmear treatment or plasma treatment.
[0058]
(3) After a copper plating film is uniformly formed on the lower surface of the core substrate 30, etching is performed in a predetermined pattern to form a conductor circuit 34 that closes the opening of the through hole 30b (FIG. 1C). Alternatively, a copper foil may be attached and a pattern may be formed through a tenting method.
[0059]
(4) Conductive bumps 31 are formed on the first terminal 21 and the second terminal 22 of the chip capacitor 20 (FIG. 1D). The conductive bump 31 is formed by metal plating such as nickel, copper, silver, gold, titanium. Alternatively, the conductive bump 31 may be made of solder (Sn / Pb, Sn / Sb, Sn / Ag, Sn / Ag / Cu), a conductive paste, or a conductive and adhesive material such as a resin impregnated with metal particles. What has both can be used. In this case, a conductive bump formed of a copper plating film was used.
[0060]
(5) After a resin having a smaller coefficient of thermal expansion than the core substrate, for example, a filling resin 32 mainly composed of epoxy, is disposed in the recess 30a of the core substrate 30, the chip capacitor 20 is fitted into the recess 32a ( FIG. 1 (E)). By applying ultrasonic vibration in this state, the chip capacitor 20 is submerged in the recess 30a, and the conductive bumps 31 of the first terminal 21 and the second terminal 22 are brought into contact with the conductor circuit 34 to establish a connection. (FIG. 2 (A)). Here, the conductive bump 31 and the conductor circuit 34 can be brought into contact with each other by applying pressure to the chip capacitor 20 from above. Thereafter, the core substrate 30 that accommodates the chip capacitor 20 is formed by heating and curing. As the filling resin, a thermosetting resin, a thermoplastic resin, or a composite thereof can be used. In order to match the difference between the viscosity adjustment and the coefficient of thermal expansion with the core substrate, inorganic particles such as silica and alumina, metal particles, and resin particles may be blended.
[0061]
(6) A pressure of 5 kg / cm while heating a thermosetting resin sheet having a thickness of 50 μm to a temperature of 50 to 150 ° C.²Then, an interlayer resin insulation layer 40 is provided (see FIG. 2B). The degree of vacuum at the time of vacuum bonding is 10 mmHg.
[0062]
(7) Next, CO with a wavelength of 10.4 μm²A via hole opening 43 having a diameter of 80 μm is provided in the interlayer resin insulating layer 40 with a gas laser under the conditions of a beam diameter of 5 mm, a top hat mode, a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot ( (See FIG. 2C). Further, the resin residue in the opening 43 may be removed using chromic acid. Here, the resin residue is removed using chromic acid, but it is also possible to perform desmear treatment using oxygen plasma.
[0063]
(8) Subsequently, through holes 33 for through holes are drilled at 100 to 500 μm with a drill or laser in the core substrate 30 on which the interlayer resin insulating layer 40 is formed (FIG. 2D).
[0064]
(9) Next, a roughened surface (not shown) of the interlayer resin insulation layer 40 is provided by dipping in an oxidizing agent such as chromic acid or permanganate. The roughened surface is preferably formed in the range of 0.1 to 5 μm. As an example, a roughened surface of 2 to 3 μm is provided by dipping in a sodium permanganate solution 50 g / l at a temperature of 60 ° C. for 5 to 25 minutes. In addition to the above, a roughened surface can be formed on the surface of the interlayer resin insulation layer 40 by performing plasma processing using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. At this time, argon gas is used as the inert gas, and plasma treatment is performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C.
[0065]
(10) A metal layer 44 is provided on the interlayer resin insulating layer 40 on which the roughened surface is formed (see FIG. 4A). The metal layer 44 is formed by electroless plating. A metal layer 52 that is a plating film is provided in a range of 0.1 to 5 μm by previously applying a catalyst such as palladium to the surface layer of the interlayer resin insulation layer 40 and immersing it in an electroless plating solution for 5 to 60 minutes. As an example,
[Electroless plating aqueous solution]
NiSO_Four                  0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
It was immersed for 40 minutes at a liquid temperature of 34 ° C.
Other than the above, using the same apparatus as the plasma treatment described above, after replacing the argon gas inside, sputtering with Ni and Cu as targets was performed under conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, time 5 minutes. The Ni / Cu metal layer may be formed on the surface of the interlayer resin insulation layer 40. At this time, the thickness of the formed Ni / Cu metal layer is 0.2 μm.
[0066]
(11) A commercially available photosensitive dry film is pasted on the substrate 30 that has been subjected to the above-described treatment, and a photomask film is placed thereon, and 100 mJ / cm.²After the exposure, the development process is performed with 0.8% sodium carbonate to provide a plating resist 51 having a thickness of 25 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 45 having a thickness of 18 μm (see FIG. 3B). The additive in the electrolytic plating aqueous solution is Kaparaside HL manufactured by Atotech Japan.
[0067]
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive (manufactured by Atotech Japan, Kaparaside HL) 19.5 ml / l
[Electrolytic plating conditions]
Current density 1A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0068]
(12) After stripping and removing the plating resist 54 with 5% NaOH, the metal layer 44 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 44 and the electrolytic plating are removed. A conductor circuit 48 and a via hole 46 having a thickness of 16 μm formed of the film 45 are formed, and a roughened surface (not shown) is formed by an etching solution containing a cupric complex and an organic acid (FIG. 3C )reference).
[0069]
(13) Next, an interlayer resin insulating layer 60 is provided on the substrate 30 as in the step (6) (see FIG. 4A).
[0070]
(14) Next, a via hole opening 63 having a diameter of 80 μm is provided in the interlayer resin insulation layer 40 in the same manner as in the step (7), and a roughened surface (not shown) of the interlayer resin insulation layer 60 is provided. (See FIG. 4B).
[0071]
(15) After providing the metal layer 64 on the interlayer resin insulation layer 40, the plating resist 70 is provided (see FIG. 4C).
[0072]
(16) Electroplating is performed in the same manner as in step (12) to form an electrolytic plating film 65 having a thickness of 15 μm (see FIG. 5A).
[0073]
(17) After the plating resist 70 is peeled and removed, the metal layer 64 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 64 and the electrolytic plating film 65 are formed. A conductor circuit 68 and a via hole 66 having a thickness of 16 μm are formed, and a roughened surface (not shown) is formed by an etching solution containing a cupric complex and an organic acid (see FIG. 5B). Alternatively, the roughened layer may be formed by an electroless plating film or an oxidation-reduction process.
[0074]
(18) Next, the photosensitizing property obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 Take parts in a container, stirred and mixed to adjust the mixture composition, photopolymerization of this mixed compositionTogetherAdd 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as an initiator and 0.2 parts by weight of Michler ketone (manufactured by Kanto Chemical Co., Ltd.) as a photosensitizer, and adjust the viscosity to 2.0 Pa · s at 25 ° C. The obtained solder resist composition (organic resin insulating material) is obtained. Viscosity was measured using a B-type viscometer (Tokyo Keiki Co., Ltd., DVL-B type) at 60 rpm with rotor No. 4 and at 6 rpm with rotor No. 3. In addition, a commercially available solder resist can also be used as a solder resist.
[0075]
(19) Next, the solder resist composition is applied to the substrate 30 to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the solder resist resist opening is formed. A photomask having a thickness of 5 mm on which a pattern of 10 mm is drawn is brought into close contact with the solder resist layer 72 and 1000 mJ / cm²Then, an opening 72a having a diameter of 200 μm is formed (see FIG. 5C).
[0076]
(20) Next, the substrate on which the solder resist layer (organic resin insulating layer) 72 is formed is nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphate (2.8 × 10 6)^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 73 having a thickness of 5 μm is formed in the opening 72a by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1The solder pads 75 are formed by immersing in an electroless plating solution containing (mol / l) for 7.5 minutes at 80 ° C. to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 73. Form (see FIG. 6).
[0077]
(21) Thereafter, a solder bump 76 is formed by printing a solder paste in the opening 71 of the solder resist layer 70 and reflowing at 200 ° C. Thereby, the multilayer printed wiring board 10 having the chip capacitor 20 and having the solder bumps 76 can be obtained (see FIG. 7).
[0078]
Next, placement of the IC chip on the printed wiring board and attachment to the daughter board will be described with reference to FIG. The IC chip 90 is mounted so that the solder pads 92S1, 92S2, 92P1, and 92P2 of the IC chip 90 correspond to the solder bumps 76 of the completed printed wiring board 10, and the IC chip 90 is attached by performing reflow. Do. Similarly, the printed wiring board 10 is attached to the daughter board 94 by reflowing the pads 96S1, 96S2, 96P1, and 96P2 of the daughter board 94 to the solder bumps 76 of the printed wiring board 10.
[0079]
In the above-described embodiment, thermosetting resin sheets are used for the interlayer resin insulating layers 40 and 60. This thermosetting resin sheet resin contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.
[0080]
The thermosetting resin sheet used in the manufacturing method of the first embodiment is a resin in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are hardly soluble in an acid or oxidizing agent (hereinafter referred to as a hardly soluble resin). It is dispersed inside.
Note that the terms “sparingly soluble” and “soluble” used in the first embodiment are “soluble” for the sake of convenience when the solution has a relatively high dissolution rate when immersed in a solution of the same acid or oxidizing agent for the same time. A material having a relatively low dissolution rate is referred to as “slightly soluble” for convenience.
[0081]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0082]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0083]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the first embodiment, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0084]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.
[0085]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified various modified polybutadiene rubber, carboxyl group-containing (meth) acrylonitrile-butadiene rubber, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0086]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0087]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0088]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0089]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.
[0090]
The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via hole opening can be formed in the interlayer resin insulating layer by exposure and development.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0091]
Specific examples of the hardly soluble resin include, for example, epoxy resins, phenol resins, phenoxy resins, polyimide resins, polyphenylene resins, polyolefin resins, fluororesins and the like. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer occurs. It is difficult.
[0092]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0093]
In the resin film used in the first embodiment, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface with unevenness of uniform roughness can be formed, and even if a via hole or a through hole is formed in a resin film, the adhesion of the metal layer of the conductor circuit formed thereon can be secured. Because it can. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. As a result, since the portion other than the surface layer portion of the resin film is not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is reliably maintained.
[0094]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film is melted to the deep part of the resin film, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.
[0095]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0096]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0097]
  Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, and melaMiResin, olefin resin and the like. By including these fillers, it is possible to improve the performance of the multilayer printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0098]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers melt and carbonize when a temperature of 350 ° C. or higher is applied.
[0099]
  Continuing, according to the first modification of the first embodiment of the present invention.Built-in capacitorA method for manufacturing a printed wiring board will be described with reference to FIG.
  About the process mentioned above with reference to Drawing 1 (A)-Drawing 1 (C), since it is the same as that of a 1st embodiment, explanation is omitted.
[0100]
(1) In 1st Embodiment, the conductive bump 31 is provided in the through-hole 30b side of the core board | substrate 30 (FIG. 10 (A)). As the conductive bump 31, any one of an anisotropic conductive paste, an anisotropic conductive film, and an insulating paste can be used.
[0101]
The thing used for an anisotropic conductive paste and an anisotropic conductive film can use the thing which consists of resin and an anisotropic conductive particle. As the resin, it is desirable to use an epoxy resin with a proven track record for electronic applications, but various resins can be used. As the anisotropic conductive particles, resin spheres having a uniform particle diameter subjected to metal plating can be used. As plating applied to the anisotropic conductive particles, copper, nickel, and noble metal plating are used. Among these, it is desirable to form with gold. The reason is that the entire resin can be completely covered with plating, and inconvenience is unlikely to occur when the particles are brought into contact with each other to establish conduction.
[0102]
The insulating paste preferably has conductivity in the paste itself. It may be impregnated with resin or inorganic particles to match the thermal expansion coefficient of the paste itself.
[0103]
(2) Next, the filling resin 32 is applied to the back side of the chip capacitor 20 and positioned in the recess 30a of the core substrate 30 (FIG. 10B).
[0104]
(3) By applying pressure to the chip capacitor 20 from above and pressing the conductive bumps 31 with the first and second terminals 21 and 22, the first and second terminals 21 and 22 are made conductive. Connection with the conductor circuit 34 is established (FIG. 10C).
[0105]
(4) Resin 32a is filled between the chip capacitor 20 and the side wall of the recess 30a of the core substrate 30 (FIG. 10D). Subsequent steps are the same as those in the first embodiment described above with reference to FIGS.
[0106]
In the first modification of the first embodiment, any one of an anisotropic conductive paste, an anisotropic conductive film, and an insulating paste is used as the conductive bump 31. Therefore, the first and second of the chip capacitor 20 are used. High connection reliability between the terminals 21 and 22 and the conductor circuit 34 can be achieved. Further, since the conductive bumps 31 are formed using an anisotropic conductive paste, anisotropic conductive film, and insulating paste having flexibility, the difference in thermal expansion coefficient between the chip capacitor 20 and the core substrate 30 is absorbed. And high reliability can be obtained.
[0107]
In the present invention, since the core substrate 30 is formed of resin, the outer shape workability is high, and the chip capacitor 20 can be reliably accommodated. Furthermore, since the thermal expansion with the resin 32, 32a filled in the chip capacitor 20 can be matched, the reliability is also improved.
[0108]
Further, since the resin 32 is filled between the core substrate 30 and the chip capacitor 20, even if a stress caused by the capacitor or the like is generated, the stress is alleviated and no migration occurs. Therefore, there is no influence of peeling or dissolution on the connection part between the terminals 21 and 22 of the chip capacitor 20 and the via hole 46. Therefore, the desired performance can be maintained even if the reliability test is performed.
Also, migration can be prevented when the capacitor is covered with copper.
[0109]
  Continuing, according to a modification of the second embodiment of the present inventionBuilt-in capacitorThe printed wiring board will be described with reference to FIG. The modified printed wiring board is substantially the same as that of the first embodiment described above. However, in the first embodiment, only the chip capacitor 20 accommodated in the core substrate 30 is provided, but in the modified example, a large-capacity chip capacitor 86 is mounted on the surface.
[0110]
An IC chip consumes a large amount of power instantaneously and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in the modified example, a chip capacitor 20 for power supply and a chip capacitor 86 are provided on the printed wiring board. The effect of this chip capacitor will be described with reference to FIG.
[0111]
In FIG. 12, the vertical axis represents voltage supplied to the IC chip, and the horizontal axis represents time. Here, an alternate long and two short dashes line C indicates a voltage fluctuation of a printed wiring board that does not include a power supply capacitor. When the power supply capacitor is not provided, the voltage is greatly attenuated. A broken line A indicates voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. The voltage does not drop much as compared with the two-dot chain line C, but the loop length becomes long, so the rate-determining power supply cannot be sufficiently performed. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board incorporating the chip capacitor according to the first embodiment. Although the loop length can be shortened, the voltage fluctuates because a large-capacity chip capacitor cannot be accommodated in the core substrate 30. Here, the solid line E shows the voltage fluctuation of the modified printed wiring board in which the chip capacitor 20 in the core substrate described above with reference to FIG. 11 and the large-capacity chip capacitor 86 are mounted on the surface. By providing the chip capacitor 20 in the vicinity of the IC chip and the chip capacitor 86 having a large capacity (and relatively large inductance), voltage fluctuation is minimized.
[0112]
  Continuously, according to the third embodiment of the present invention.Built-in capacitorThe configuration of the printed wiring board will be described with reference to FIG.
  The configuration of the printed wiring board of the third embodiment is substantially the same as that of the first embodiment described above. However, the chip capacitor 20 accommodated in the core substrate 30 is different. FIG. 13 shows a plan view of the chip capacitor. FIG. 13A shows a chip capacitor before cutting for multi-piece taking, and a one-dot chain line in the drawing indicates a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are arranged on the side edge of the chip capacitor as shown in the plan view of FIG. FIG. 13C shows the chip capacitor before cutting for multi-piece fabrication according to the third embodiment, and the alternate long and short dash line in the drawing indicates the cutting line. In the printed wiring board of the third embodiment, the first electrode 21 and the second electrode 22 are disposed inside the side edge of the chip capacitor as shown in the plan view of FIG.
[0113]
In the printed wiring board of the third embodiment, since the chip capacitor 20 having electrodes formed inside the outer edge is used, a chip capacitor having a large capacity can be used.
[0114]
  Continuing from the first modification of the third embodimentBuilt-in capacitorThis will be described with reference to a printed wiring board.
  FIG. 14A shows a plan view of the chip capacitor 20 accommodated in the core substrate of the printed wiring board according to the first modification, and FIG. 14B shows a cross-sectional view. In the first embodiment described above, a plurality of small-capacity chip capacitors are accommodated in the core substrate. However, in the first modification, a large-capacity large-sized chip capacitor 20 is accommodated in the core substrate. Here, the chip capacitor 20 includes a first electrode 21, a second electrode 22, a dielectric 23, a first conductive film 24 connected to the first electrode 21, and a second electrode connected to the second electrode 22 side. The conductive film 25 and the connection electrodes 27 on the upper and lower surfaces of the chip capacitor not connected to the first conductive film 24 and the second conductive film 25 are formed. Through this electrode 27, the IC chip side and the daughter board side are connected in the same way through the through hole of the core substrate.
[0115]
Since the large-sized chip capacitor 20 is used in the printed wiring board of the first modified example, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0116]
  Referring to FIG. 15, according to the second modificationBuilt-in capacitorThe printed wiring board will be described. FIG. 15A shows a chip capacitor before cutting for multi-piece cutting. In the drawing, a one-dot chain line shows a normal cutting line, and FIG. 15B shows a plan view of the chip capacitor. . As shown in FIG. 15B, in this second modified example, a plurality of chip capacitors (three in the example in the figure) are connected and used in a large format.
[0117]
In the second modified example, since a large chip capacitor 20 is used, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0118]
In the third embodiment described above, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, it is also possible to use a plate-like capacitor in which a conductive film is provided on a ceramic plate.
[0119]
  Continuing, according to the fourth embodiment of the present invention.Built-in capacitorThe printed wiring board will be described with reference to FIG. The printed wiring board of the fourth embodiment is the same as that of the first to third embodiments except for the built-in chip capacitor 20.
  FIG. 16A shows the chip capacitor 20 of the fourth embodiment. In the first embodiment described above, as described above with reference to FIG. 9A, the metal coating made of copper plating is applied on the first terminal 21 and the second terminal 22 made of the metallized layer 26 of the chip capacitor 20. 29 was formed. In contrast, in the fourth embodiment, the conductive paste 27 is coated on the first terminal 21 and the second terminal 22 made of the metallized layer 26. Here, the metallized layer 26 is made of nickel, platinum, and silver, and the conductive paste is made of at least one kind of copper, nickel, and silver particles having a particle diameter of 0.1 to 1.0 μm (preferably 1 to 5 μm). It is included. Here, although formed from one layer, two or more layers of conductive pastes composed of different kinds of metal particles can be coated. The thickness of the conductive paste 27 is 1 to 30 μm (preferably 5 to 20 μm).
[0120]
In the fourth embodiment, since the conductive paste 27 is coated on the uneven metallized layer 26, the surfaces on the first terminal 21 and the second terminal 22 are smoothed. When an interlayer resin insulating layer is provided on the terminal 21 and the second terminal 22 and a via hole opening is formed by a laser, the resin residue is eliminated, and the connection reliability when the via hole is formed can be improved. . That is, it is possible to solve the problem of the resin remaining when the via hole opening is formed on the uneven metallized layer 26.
[0121]
FIG. 16B shows a chip capacitor 20 according to a first modification of the fourth embodiment. In the first modified example, a plating layer 28 including an electroless plating 28 a and an electrolytic plating film 28 b is formed on the conductive paste 27. In the first modified example, the surfaces on the first terminal 21 and the second terminal 22 are completely smooth, and the connection reliability when the via hole is formed can be improved.
[0122]
【The invention's effect】
As described above, according to the present invention, the capacitor can be accommodated in the core substrate, and the distance between the IC chip and the capacitor is shortened, so that the loop inductance of the printed wiring board can be reduced. Further, since the core substrate is formed by laminating a plurality of resin substrates on which conductor circuits are formed, the wiring density in the core substrate is increased, and the number of interlayer resin insulation layers can be reduced.
[0123]
In addition, since the resin is filled between the core substrate and the capacitor, even if a stress caused by the capacitor or the like is generated, the stress is alleviated and no migration occurs. Therefore, there is no influence of peeling or dissolution on the connection portion between the capacitor electrode and the via hole. Therefore, the desired performance can be maintained even if the reliability test is performed.
Also, migration can be prevented when the capacitor is covered with copper.
[Brief description of the drawings]
1 (A), (B), (C), (D), (E) are related to a first embodiment of the present invention.Built-in capacitorIt is a manufacturing process figure of a printed wiring board.
FIG. 2 (A), (B), (C), (D) relates to a first embodiment of the present invention.Built-in capacitorIt is a manufacturing process figure of a printed wiring board.
FIGS. 3A, 3B, and 3C are related to a first embodiment of the present invention.Built-in capacitorIt is a manufacturing process figure of a printed wiring board.
4A, 4B, and 4C are related to the first embodiment of the present invention.Built-in capacitorIt is a manufacturing process figure of a printed wiring board.
FIGS. 5A, 5B, and 5C are related to a first embodiment of the present invention.Built-in capacitorIt is a manufacturing process figure of a printed wiring board.
FIG. 6 is related to the first embodiment of the present invention.Built-in capacitorIt is a manufacturing process figure of a printed wiring board.
FIG. 7 is related to the first embodiment.Built-in capacitorIt is sectional drawing of a printed wiring board.
FIG. 8 is related to the first embodiment.Built-in capacitorIt is sectional drawing of a printed wiring board.
9A and 9B are cross-sectional views of a chip capacitor.
10A, 10B, 10C, and 10D are related to a first modification of the first embodiment. FIG.Built-in capacitorIt is a manufacturing process figure of a printed wiring board.
FIG. 11 relates to a second embodiment of the present invention.Built-in capacitorIt is sectional drawing which shows the state which mounted the IC chip on the printed wiring board.
FIG. 12 is a graph showing changes in supply voltage to IC chip and time.
13 (A), (B), (C), (D) are diagrams of the third embodiment.Built-in capacitorIt is a top view of the chip capacitor of a printed wiring board.
FIG. 14A is related to the third embodiment.Built-in capacitorIt is a top view of the chip capacitor of a printed wiring board, and (B) is a sectional view.
FIGS. 15A and 15B relate to a modification of the third embodiment.Built-in capacitorIt is a top view of the chip capacitor of a printed wiring board.
FIGS. 16A and 16B relate to a modification of the fourth embodiment.Built-in capacitorIt is sectional drawing of the chip capacitor of a printed wiring board.
[Explanation of symbols]
  10 Printed wiring board(Printed wiring board with built-in capacitor)
  20 chip capacitors
  21 1st terminal
  22 Second terminal
  30 core substrate
  30a recess
  30b through hole
  32 Conductive adhesive
  34 Conductor circuit
  36 Through hole
  40 connection layer
  42 Circuit pattern
  43 Non-through hole
  46 Bahia Hall
  60 Interlayer resin insulation layer
  66 Bahia Hall
  68 Conductor circuit
  90 IC chip
  94 Daughter Board

Claims (18)

A capacitor-embedded printed wiring board in which a resin insulating layer and a conductor circuit are laminated on a core substrate that houses a capacitor in a recess,
A through hole is formed at the bottom of the concave portion of the core substrate,
A conductor circuit is formed on the surface of the core substrate to close the opening of the through hole,
A capacitor- covered terminal of the capacitor accommodated in the recess and a conductor circuit that closes the through hole are connected via a conductive bump made of copper in the through hole,
The resin insulation layer and the conductor circuit are laminated on the through hole side of the core substrate,
Solder bumps are formed on the surface of the through hole side,
The printed wiring board with a built-in capacitor, wherein the solder bump is connected to the conductor circuit.   The printed wiring board with a built-in capacitor according to claim 1, wherein the conductive bump is made of a pressure contact paste.   The printed circuit board with a built-in capacitor according to claim 1, wherein the core substrate is formed by impregnating a core material with a resin.   5. The capacitor built-in printed wiring board according to claim 1, wherein the capacitor includes a plurality of capacitors.   The capacitor built-in printed wiring board according to claim 1, wherein a capacitor is mounted on a surface of the printed wiring board.   6. The printed wiring board with a built-in capacitor according to claim 5, wherein the capacitance of the chip capacitor on the surface is equal to or greater than the capacitance of the inner-layer chip capacitor.   6. The printed wiring board with a built-in capacitor according to claim 5, wherein the inductance of the chip capacitor on the surface is equal to or greater than the inductance of the chip capacitor on the inner layer.   8. A printed wiring board with a built-in capacitor according to claim 1, wherein a metal film is formed on the electrode of the capacitor, and an electrical connection is made by plating to the electrode on which the metal film is formed.   9. The printed wiring board with a built-in capacitor according to claim 8, wherein the metal film formed on the capacitor electrode is a plating film mainly composed of copper.   The capacitor-embedded printed wiring board according to claim 1 or 2, wherein a capacitor is bonded to the core substrate with an insulating adhesive, and the insulating adhesive has a smaller thermal expansion coefficient than the core substrate. .   11. The capacitor electrode according to claim 1, wherein at least a part of the electrode covering layer of the capacitor is exposed and the electrode exposed from the covering layer is electrically connected by plating. Printed wiring board with built-in capacitor.   12. The capacitor built-in printed wiring board according to claim 1, wherein a chip capacitor having an electrode formed inside an outer edge is used as the capacitor.   13. A printed wiring board with a built-in capacitor according to claim 1, wherein a chip capacitor having electrodes formed in a matrix is used as the capacitor.   The printed circuit board with a built-in capacitor according to claim 1, wherein a plurality of chip capacitors for connecting multiple capacitors are used as the capacitor.   The printed wiring board with a built-in capacitor according to any one of claims 1 to 14, wherein a conductive paste is applied to an electrode of the capacitor, and an electrical connection is made by plating to the electrode coated with the conductive paste.   16. The capacitor built-in printed wiring board according to claim 1, wherein a surface of the capacitor is roughened. A method for producing a printed wiring board with a built-in capacitor, comprising at least the following steps (a) to (g):
(A) forming a recess in the core substrate and a through hole in the bottom of the recess;
(B) forming a conductor circuit on the surface of the core substrate that closes the opening of the through hole;
(C) disposing a resin in the concave portion of the core substrate;
(D) a step of disposing a conductive bump made of copper on a copper-coated terminal of the capacitor;
(E) The step of accommodating the capacitor in the recess of the core substrate and making a connection with a conductor circuit that closes the opening of the through hole via the conductive bump:
(F) A step of laminating a resin insulating layer and a conductor circuit on the through hole side of the core substrate:
(G) A step of forming solder bumps connected to the conductor circuit on the surface on the through hole side.   18. The method of manufacturing a printed wiring board with a built-in capacitor according to claim 17, wherein ultrasonic vibration is applied in the step of establishing a connection with a conductor circuit that closes the opening of the through hole via the conductive bump.

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