JP4869486B2 - Printed wiring board and printed wiring board manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed circuit board on which an electronic component such as an IC chip is placed and a manufacturing method thereof, and more particularly to a printed wiring board having a built-in capacitor and a manufacturing method thereof.
[0002]
[Prior art]
Currently, in a printed wiring board for a package substrate, a chip capacitor is sometimes surface-mounted for the purpose of facilitating power supply to an IC chip.
[0003]
Since the reactance of the wiring from the chip capacitor to the IC chip depends on the frequency, a sufficient effect cannot be obtained even if the chip capacitor is surface-mounted as the driving frequency of the IC chip increases. For this reason, the present applicant has proposed, in Japanese Patent Application No. 11-248311, a technique of forming a recess in the core substrate and accommodating a chip capacitor in the recess. Moreover, as a technique for embedding a capacitor in a substrate, JP-A-6-326472, JP-A-7-263619, JP-A-10-256429, JP-A-11-45955, JP-A-11-126978, JP-A-11- No. 31868 etc.
[0004]
Japanese Patent Application Laid-Open No. 6-326472 discloses a technique of embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, it is possible to reduce power supply noise, eliminate the need for a space for mounting a chip capacitor, and reduce the size of the insulating substrate. Japanese Patent Application Laid-Open No. 7-263619 discloses a technique for embedding a capacitor in a substrate such as ceramic or alumina. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.
[0005]
[Problems to be solved by the invention]
However, the above-mentioned Japanese Patent Laid-Open Nos. 6-326472 and 7-263619 cannot reduce the distance from the IC chip to the capacitor so much, and in the higher frequency region of the IC chip, the inductance is required as it is currently required. Could not be reduced. In particular, in multilayer build-up wiring boards made of resin, disconnection occurs between the chip capacitor terminals and vias due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and interlayer resin insulation layer. Peeling occurs between the capacitor and the interlayer resin insulation layer, and cracks occur in the interlayer resin insulation layer, and high reliability cannot be achieved over a long period of time.
[0006]
On the other hand, in the invention of Japanese Patent Application No. 11-248311, when there is a displacement in the position of the capacitor, the connection between the capacitor terminal and the via cannot be made accurately, and the power supply from the capacitor to the IC chip may not be possible. was there.
[0007]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having a built-in capacitor and improved connection reliability, and a method for manufacturing the printed wiring board.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problem, in claim 1, a printed wiring board in which an interlayer resin insulating layer and a conductor circuit are alternately stacked on a core substrate that accommodates a capacitor, the core substrate accommodating the capacitor Is formed by laminating a first resin substrate having the conductor circuit formed on the surface thereof, a second resin substrate having an opening for accommodating a capacitor, and a third resin substrate with an adhesive plate interposed therebetween. A conductive paste is applied to the surface of the electrode made of the metallization of the capacitor, and a metal layer made of a copper plating film is provided on the conductive paste of the capacitor electrode. This resin substrate is made of copper plating and has a technical feature in that a via hole connected to the capacitor electrode is formed.
[0009]
The printed wiring board manufacturing method according to claim 17 has at least the following steps (a) to (f) as technical features:
(A) forming a conductive pad made of copper on the first resin substrate;
(B) A capacitor in which a conductive paste is applied on the metallized electrode via a conductive adhesive and a metal layer is provided on the conductive paste is connected to the conductor pad of the first resin substrate. Process;
(C) a third resin substrate having a conductor circuit formed on the surface thereof, a second resin substrate having an opening for accommodating the capacitor, and the first resin substrate, the first resin substrate Stacking a capacitor in the opening of the second resin substrate and interposing an adhesive plate so as to close the opening of the second resin substrate with a third resin substrate;
(D) a step of heating and pressurizing the first resin substrate, the second resin substrate, and the third resin substrate to form a core substrate;
(E) on the conductive paste, providing the metal layer composed of a copper plating film process;
(F) forming a via hole formed on the first resin substrate by copper plating and connected to the electrode of the capacitor via the conductor pad;
[0010]
In the printed wiring board according to claim 1 and the printed wiring board manufacturing method according to claim 19, the capacitor can be accommodated in the core substrate, and the distance between the IC chip and the capacitor is shortened. Loop inductance can be reduced. Further, since the resin substrate is laminated, sufficient strength can be obtained for the core substrate. Furthermore, since the core substrate is configured smoothly by disposing the first resin substrate and the third resin substrate on both surfaces of the core substrate, an interlayer resin insulating layer and a conductor circuit can be appropriately formed on the core substrate. It is possible to reduce the occurrence rate of defective printed wiring boards.
[0011]
It means a circuit formed by a build-up method in which an interlayer resin insulation layer is provided on a core substrate, and via holes or through holes are provided in the interlayer resin insulation layer to form a conductor circuit as a conductive layer. For them, either a semi-additive method or a full additive method can be used.
[0012]
It is desirable to fill the voids with resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if stress originating from the capacitor is generated, it can be relaxed by the filled resin. The resin also has an effect of reducing adhesion and migration between the capacitor and the core substrate.
[0013]
In addition, since the conductive paste is applied to the surface of the electrode made of metallization of the capacitor, the electrical connectivity of the electrode made of metallization and having high surface resistance can be improved. In addition, electrodes made of metallized have irregularities on the surface, and even if they are directly connected with a conductive adhesive, they cannot be adhered completely, but the conductive paste can eliminate irregularities and improve adhesion. The connection resistance can be lowered. In addition, since the electrode made of metallized is in contact with the surrounding resin layer via the conductive paste, the generation of stress due to the difference in thermal expansion between the electrode and the resin layer is suppressed, and the resin layer is not cracked or peeled off.
[0014]
Further , since the metal layer is provided on the conductive paste of the capacitor electrode, it is possible to prevent migration at the electrode and to further reduce the connection resistance. The electrode made of metallized has irregularities on the surface, and even if it is directly connected with a conductive adhesive, it cannot be completely adhered, but by applying a conductive paste and further providing a metal layer, the irregularities can be obtained. It can be completely eliminated, adhesion can be increased, and connection resistance can be reduced.
[0015]
According to a second aspect of the present invention , a roughening process is performed on the surface of the capacitor. As a result, the adhesion between the ceramic capacitor and the resin adhesive layer and the interlayer resin insulation layer is increased, and the adhesive layer and the interlayer resin insulation layer are peeled off at the interface even when the heat cycle test is performed. There is no.
[0016]
According to a third aspect of the present invention , the surface of the capacitor is subjected to wettability improvement processing such as silane coupling and resin coating. As a result, the adhesion between the ceramic capacitor and the resin adhesive layer and the interlayer resin insulation layer is increased, and the adhesive layer and the interlayer resin insulation layer are peeled off at the interface even when the heat cycle test is performed. There is no.
[0017]
According to the fourth aspect , since the adhesive plate is made by impregnating the core material with the thermosetting resin, the core substrate can have high strength.
[0018]
According to the fifth aspect of the present invention, since the first, second, and third resin substrates are made by impregnating the core material with resin, the core substrate can have high strength.
[0019]
According to the sixth aspect , since a plurality of capacitors are accommodated in the core substrate, the capacitors can be highly integrated.
[0020]
According to the seventh aspect , since the conductor circuit is formed on the second resin substrate, the wiring density of the substrate can be increased and the number of interlayer resin insulating layers can be reduced.
[0021]
According to the eighth aspect , in addition to the capacitor accommodated in the substrate, the capacitor is disposed on the surface. Since the capacitor is accommodated in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance can be reduced, and the power can be supplied instantaneously. Since the capacitor is disposed, a large-capacity capacitor can be attached, and a large amount of power can be easily supplied to the IC chip.
[0022]
According to the ninth aspect of the present invention , the capacitance of the capacitor on the surface is equal to or greater than the capacitance of the capacitor on the inner layer, so that there is no shortage of power supply in the high frequency region, and a desired IC chip operation is ensured.
[0023]
According to the tenth aspect of the present invention , since the inductance of the capacitor on the surface is equal to or larger than the inductance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and the desired operation of the IC chip is ensured.
[0024]
According to the eleventh aspect , the thermal expansion coefficient of the insulating adhesive is set to be smaller than that of the encasing layer, that is, close to a capacitor made of ceramic. For this reason, in the heat cycle test, even if an internal stress occurs due to a difference in thermal expansion coefficient between the core substrate and the capacitor, cracks, peeling, and the like hardly occur in the core substrate, and high reliability can be achieved.
[0025]
According to the fourteenth aspect , since the chip capacitor having the electrode formed on the inner side of the outer edge is used, the external electrode can be made large even if conduction is made through the via hole, and the allowable range of alignment is widened, so that connection failure is eliminated.
[0026]
According to the fifteenth aspect , since a capacitor having electrodes formed in a matrix is used, a large chip capacitor can be easily accommodated in the core substrate. As a result, the capacitance can be increased, and the electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is hardly warped.
[0027]
In the sixteenth aspect , a plurality of chip capacitors may be connected to the capacitor. Thereby, the capacitance can be adjusted as appropriate, and the IC chip can be operated appropriately.
[0028]
In the present invention, the resin film used as the interlayer resin insulation layer and the connection layer is a resin in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are hardly soluble in an acid or oxidizing agent (hereinafter referred to as a hardly soluble resin). ).
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively fast dissolution rate as “soluble” for convenience when immersed in a solution of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.
[0029]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0030]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0031]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0032]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.
[0033]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified various modified polybutadiene rubber, carboxyl group-containing (meth) acrylonitrile-butadiene rubber, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0034]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0035]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0036]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0037]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.
[0038]
The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via hole opening can be formed in the interlayer resin insulating layer by exposure and development.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0039]
Specific examples of the hardly soluble resin include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0040]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0041]
In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface with unevenness of uniform roughness can be formed, and even if a via hole or a through hole is formed in a resin film, the adhesion of the metal layer of the conductor circuit formed thereon can be secured. Because it can. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. As a result, since the portion other than the surface layer portion of the resin film is not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is reliably maintained.
[0042]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film is melted to the deep part of the resin film, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.
[0043]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0044]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0045]
Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compounds, for example, silica, alumina, dolomite and the like. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, Mera Mi down resin, olefin resin or the like can be mentioned It is done. By containing these fillers, it is possible to improve the performance of the printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0046]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more.
[0047]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state where the IC chip 90 is mounted on the printed wiring board 10 shown in FIG.
[0048]
As shown in FIG. 7, the printed wiring board 10 includes a core substrate 30 that houses a plurality of chip capacitors 20 and build-up wiring layers 80A and 80B. The build-up wiring layers 80A and 80B are composed of the resin layer 40 and the interlayer resin insulation layers 140 and 240. Conductor circuits 58 and via holes 60 are formed in the upper resin layer 40, and conductor circuits 158 and via holes 160 are formed in the upper and lower interlayer resin insulation layers 140, and upper and lower interlayer resins are formed. Conductive circuits 258 and via holes 260 are formed in the insulating layer 240. A solder resist layer 70 is formed on the interlayer resin insulation layer 240. The buildup wiring layer 80 </ b> A and the buildup wiring layer 80 </ b> B are connected via a through hole 56 formed in the core substrate 30.
[0049]
As shown in FIG. 13A, the chip capacitor 20 includes a first electrode 21, a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes. A plurality of first conductive films 24 connected to the electrode 21 side and second conductive films 25 connected to the second electrode 22 side are arranged to face each other. The surface of the first electrode 21 and the second electrode 22 is covered with a conductive paste 26.
[0050]
Here, the 1st electrode 21 and the 2nd electrode 22 consist of metallization of Ni, Pb, or Ag metal. The conductive paste 26 is made of a paste containing metal particles such as Cu, Ni, or Ag. Here, the particle diameter of the metal particles is desirably 0.1 to 10 μm, and particularly 1 to 5 μm is optimal. As the conductive paste, an organic conductive paste in which a thermosetting resin such as an epoxy resin or a polyphenylene sulfide (PPS) resin is added to metal particles is desirable. The thickness of the conductive paste 26 is desirably 1 to 30 μm. If the thickness is less than 1 μm, the unevenness of the electrode surface cannot be eliminated. On the other hand, if the thickness exceeds 30 μm, the effect is not particularly improved. Here, a thickness of 5 to 20 μm is most desirable. In addition, it is possible to use a paste in which particles having two or more types of different diameters are blended, and it is also possible to coat a metal paste having two or more types of different diameters.
[0051]
In the first embodiment, since the conductive paste 26 is applied to the surfaces of the electrodes 21 and 22 made of metallization of the capacitor 20, the electrical connectivity of the electrodes 21 and 22 made of metallization and having high surface resistance can be improved. it can. Further, the electrodes 21 and 22 made of metallized have irregularities on the surface, and even if they are directly connected with the adhesive material 36, they cannot be completely adhered, but the conductive paste 26 can eliminate the irregularities, The connection resistance can be lowered. Further, since the electrodes 21 and 22 made of metallized are in contact with the prepregs 38a and 38b and the core substrate 30 serving as the resin filler via the conductive paste 26, the electrodes 21 and 22 and the resin filler and the core substrate 30 are in contact with each other. Generation of stress due to a difference in thermal expansion is suppressed, and peeling of the resin filler and generation of cracks in the core substrate 30 are eliminated.
[0052]
As shown in FIG. 8, solder bumps 76U for connection to pads 92P1 and 92P2 of IC chip 90 are disposed on upper buildup wiring layer 80A. On the other hand, solder bumps 76D for connection to the pads 94P1 and 94P2 of the daughter board 95 are disposed on the lower buildup wiring layer 80B.
[0053]
The grounding pad 92P1 of the IC chip 90 is connected to the first electrode 21 of the chip capacitor 20 via the bump 76U-conductor circuit 258-via hole 260-conductor circuit 158-via hole 160-conductor circuit 58-via hole 60. ing. On the other hand, the grounding pad 94P1 of the daughter board 95 is connected to the first electrode 21 of the chip capacitor 20 via the bump 76D-via hole 260-conductor circuit 158-via hole 160-through hole 56-conductor circuit 58-via hole 60. Has been.
[0054]
The power supply pad 92P2 of the IC chip 90 is connected to the second electrode 22 of the chip capacitor 20 through the bump 76U-via hole 260-conductor circuit 158-via hole 160-conductor circuit 58-via hole 60. On the other hand, the power supply pad 94P2 of the daughter board 95 is connected to the second electrode 22 of the chip capacitor 20 via the bump 76D-via hole 260-conductor circuit 158-via hole 160-through hole 56-via hole 60. Although not shown, the signal pad of the IC chip is connected to the signal pad of the daughter board via the conductor circuit, the via hole, and the through hole of the printed wiring board.
[0055]
As shown in FIG. 7, the core substrate 30 of this embodiment includes a first resin substrate 30a of conductors pad portion 34 for connecting the chip capacitor 20 is formed on one surface, an adhesive resin layer on the first resin substrate 30a It consists of a second resin substrate 30b connected via an (adhesive plate) 38a and a third resin substrate 30c connected to the second resin substrate 30b via an adhesive resin layer (adhesive plate) 38b. In the second resin substrate 30b, an opening 30B that can accommodate the chip capacitor 20 is formed.
[0056]
Thereby, since the chip capacitor 20 can be accommodated in the core substrate 30, the distance between the IC chip 90 and the chip capacitor 20 is shortened, so that the loop inductance of the printed wiring board 10 can be reduced. Further, since the first resin substrate 30a, the second resin substrate 30b, and the third resin substrate 30c are stacked, sufficient strength can be obtained for the core substrate 30. Further, the first resin substrate 30a and the third resin substrate 30c are disposed on both surfaces of the core substrate 30 to make the core substrate 30 smooth, so that the resin layers 40, 140, 240 and the conductor are formed on the core substrate 30. The circuits 58, 158, and 258 can be appropriately formed, and the defective product occurrence rate of the printed wiring board can be reduced.
[0057]
Further, in the present embodiment, as shown in FIG. 1D, an insulating adhesive 34 is interposed between the first resin substrate 30a and the chip capacitor 20. Here, the thermal expansion coefficient of the adhesive 34 is set to be smaller than that of the core substrate 30, that is, close to the chip capacitor 20 made of ceramic. For this reason, in the heat cycle test, even if an internal stress is generated due to the difference in thermal expansion coefficient between the core substrate and the adhesive layer 40 and the chip capacitor 20, the core substrate is hardly cracked, peeled off, etc., and has high reliability. Can be achieved. In addition, migration can be prevented.
[0058]
Next, a method for manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.
[0059]
(1) A copper-clad laminate in which a copper foil 32 is laminated on one side of a first resin substrate 30a obtained by impregnating a BT (bismaleimide triazine) resin into a core material such as a glass cloth having a thickness of 0.1 mm and curing. Let it be a starting material (see FIG. 1A).
Then, the copper foil 32 side of the copper clad laminate by etching in a pattern to form the conductors pad portion 34 on one side of the first resin substrate 30a (see FIG. 1 (B)).
[0060]
Note that a ceramic substrate such as AlN could not be used as the core substrate. This is because the substrate has poor external formability and cannot accommodate a capacitor, and even if it is filled with resin, voids are generated.
[0061]
(2) Then, the guide member pad portion 34, the solder paste, the bonding material 36 such as conductive paste is applied using a printing machine (see FIG. 1 (C)). At this time, potting or the like may be performed in addition to the application. As the solder paste, any of Sn / Pb, Sn / Sb, Sn / Ag, and Sn / Ag / Cu can be used. Then, disposing a filler 33 between the conductors pads 34 (see FIG. 1 (D)). As a result, the gap between the chip capacitor 20 and the first resin substrate 30a can be filled as will be described later. Next, the chip capacitor 20 comprising a plurality of ceramic guide member pad portion 34 is placed, via the adhesive material 36, the guide body pad section 34 for connecting the chip capacitor 20 (see FIG. 2 (A)) . Although one or a plurality of chip capacitors 20 may be used, the use of a plurality of chip capacitors 20 enables high integration of the capacitors.
[0062]
(3) Next, a prepreg (adhesive resin layer) 38a, 38b in which a core material such as glass cloth is impregnated with an epoxy resin and a second resin substrate 30b in which a core material such as glass cloth is impregnated with BT resin and cured. A thickness 0.4 mm) and a third resin substrate 30c (thickness 0.1 mm) are prepared. In the prepreg 38a and the second resin substrate 30b, through holes 38A and 30B capable of accommodating the chip capacitor 20 are formed. First, the second resin substrate 30b is placed on the third resin substrate 30c via the prepreg 38b. Next, the first resin substrate 30a is inverted and placed on the second resin substrate 30b via the prepreg 38a. That is, the chip capacitor 20 connected to the first resin substrate 30a faces the prepreg 38a and is overlaid so that the chip capacitor 20 can be accommodated in the through hole formed in the second resin substrate 30b (see FIG. 2B). ). Thereby, the chip capacitor 20 can be accommodated in the core substrate 30, and a printed wiring board with reduced loop inductance can be provided.
[0063]
(4) Then, the first, second, and third resin substrates 30a, 30b, and 30c are integrated in a multilayer shape by press-pressing the stacked substrates using a hot press, and a plurality of chip capacitors 20 are integrated. Is formed (see FIG. 2C).
Here, first, an epoxy resin (insulating resin) is pushed out from the prepregs 38a and 38b by being pressurized, so that a gap between the opening 30B and the chip capacitor 20 is filled. Furthermore, the epoxy resin is cured by being heated simultaneously with the pressurization, and the prepregs 38a and 38b are interposed as adhesive resins, whereby the first resin substrate 30a, the second resin substrate 30b, and the third resin substrate 30c Is firmly bonded. In the present embodiment, the gap in the opening 30B is filled with the epoxy resin that comes out of the prepreg, but it is also possible to place a filler in the opening 30B instead.
Here, since both surfaces of the core substrate 30 are smooth, the first resin substrate 30a and the third resin substrate 30c, the smoothness of the core substrate 30 is not impaired, and the resin layer 40 and the conductor are formed on the core substrate 30 in a process described later. The circuit 58 can be formed appropriately, and the defective product occurrence rate of the printed wiring board can be reduced. In addition, sufficient strength can be obtained for the core substrate 30.
[0064]
(5) A thermosetting resin film, which will be described later, is vacuum-bonded and laminated at a pressure of 5 kg / cm ² while raising the temperature to a temperature of 50 to 150 ° C. on the substrate 30 that has undergone the above steps, thereby providing an interlayer resin insulation layer 40 (FIG. 2). (See (D)). The degree of vacuum at the time of vacuum bonding is 10 mmHg.
[0065]
(6) Next, via hole openings 42 reaching the conductor pad portions 34 are formed by laser in the interlayer resin insulating layer 40 and the first resin substrate 30a on the first resin substrate 30a side (see FIG. 3A).
[0066]
(7) And the through-hole 44 for through holes is formed in the core board | substrate 30 with a drill or a laser (refer FIG. 3 (B)). Thereafter, desmear treatment is performed using oxygen plasma. Or you may perform the desmear process by chemical | medical solutions, such as permanganic acid.
[0067]
(8) Next, plasma processing is performed using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd., and the roughened surface 46 is formed on the entire surface of the core substrate 30. At this time, argon gas is used as the inert gas, and plasma treatment is performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C. Thereafter, sputtering using Ni and Cu as targets is performed, and a Ni / Cu metal layer 48 is formed on the surface of the interlayer resin insulating layer 40 (see FIG. 3C). Although sputtering is used here, a metal layer such as copper or nickel may be formed by electroless plating. In some cases, the electroless plating film may be formed after the sputtering. You may roughen by an acid or an oxidizing agent. The roughened layer is preferably 0.1 to 5 μm.
[0068]
(9) Next, a photosensitive dry film is affixed to the surface of the Ni / Cu metal layer 48, a mask is placed, exposure and development are performed, and a resist 50 having a predetermined pattern is formed (FIG. 3D). reference). Then, the core substrate 30 is immersed in the electrolytic plating solution, a current is passed through the Ni / Cu metal layer 48, and electrolytic plating is performed on the resist 50 non-formation portion under the following conditions to form the electrolytic plating film 52 (FIG. 4 (A)).
[0069]
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive (manufactured by Atotech Japan, Kaparaside HL)
19.5 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
Time 120 minutes Temperature 22 ± 2 ° C
[0070]
(10) After stripping and removing the resist 50 with 5% NaOH, the Ni—Cu alloy layer 48 under the resist 50 is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the Ni—Cu alloy is removed. A through hole 56 having a thickness of 16 μm and a conductor circuit 58 (including a via hole 60) made of the layer 48 and the electrolytic plating film 52 are formed. After the substrate is washed with water and dried, the surface of the through hole 56 and the conductor circuit 58 (including the via hole 60) is etched by spraying an etching solution on both sides of the substrate to spray the through hole 56 and A roughened surface 62 is formed on the entire surface of the conductor circuit 58 (including the via hole 60) (see FIG. 4B). As an etching solution, a mixture of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride and 78 parts by weight of ion-exchanged water is used.
[0071]
(11) Fill the through hole 56 with a resin filler 64 containing an epoxy resin as a main component, and perform heat drying. (See FIG. 4C).
[0072]
(12) Thereafter, the thermosetting resin film used in the step (5) is vacuum-bonded and laminated at a pressure of 5 kg / cm ² while raising the temperature to 50 to 150 ° C. to provide an interlayer resin insulating layer 140 (FIG. 4). (See (D)). The degree of vacuum at the time of vacuum bonding is 10 mmHg.
[0073]
(13) Next, a via hole opening 142 is formed in the interlayer resin insulating layer 140 by laser (see FIG. 5A).
[0074]
(14) Thereafter, by repeating the steps (8) to (10), a conductor circuit 158 (via hole) having a thickness of 16 μm made of the Ni—Cu alloy layer 148 and the electrolytic plating film 152 is formed on the interlayer resin insulation layer 140. 160) and a roughened surface 162 are formed (see FIG. 5B).
[0075]
(15) Further, by repeating the steps (12) to (14), the interlayer resin insulating layer 240, the conductor circuit 258 (including the via hole 260), and the roughened surface 262 are formed in the upper layer (FIG. 5C). reference).
[0076]
(16) Next, a photosensitizing agent obtained by acrylating 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 A weight part is put into a container, and a mixed composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator and Michler's ketone as a photosensitizer for the mixed composition. (Kanto Chemical Co., Ltd.) 0.2 part by weight is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured using a B-type viscometer (manufactured by Tokyo Keiki Co., Ltd., DVL-B type) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3.
[0077]
(17) Next, the solder resist composition is applied to both surfaces of the substrate 30 to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the opening of the solder resist is performed. A photomask having a thickness of 5 mm on which the pattern of the portion is drawn is brought into close contact with the solder resist layer 70 and exposed to ultraviolet light of 1000 mJ / cm ² and developed with a DMTG solution to form an opening 71 (FIG. 6A). reference).
[0078]
(18) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed is made of nickel chloride (2.3 × 10 ⁻¹ mol / l), sodium hypophosphate (2.8 × 10 ^−1). mol / l) and sodium citrate (1.6 × 10 ⁻¹ mol / l) in a pH = 4.5 electroless nickel plating solution for 20 minutes, and nickel plating with a thickness of 5 μm is formed in the opening 71. Layer 72 is formed. Further, the substrate was made of potassium gold cyanide (7.6 × 10 ^-3 mol / l), ammonium chloride (1.9 × 10 ^-1 mol / l), sodium citrate (1.2 × 10 ^-1 mol). / L), and immersed in an electroless plating solution containing sodium hypophosphite (1.7 × 10 ⁻¹ mol / l) for 7.5 minutes at 80 ° C., a thickness of 0 on the nickel plating layer 72 A 0.03 μm gold plating layer 74 is formed (see FIG. 6B).
[0079]
(19) Thereafter, a solder paste is printed in the opening 71 of the solder resist layer 70 and reflowed at 200 ° C. to form solder bumps (solder bodies) 76U and 76D. Thereby, the printed wiring board 10 having the solder bumps 76U and 76D can be obtained (see FIG. 7).
[0080]
Next, placement of the IC chip 90 on the printed wiring board 10 completed in the above-described process and attachment to the daughter board 95 will be described with reference to FIG. The IC chip 90 is mounted so that the solder pads 92P1 and 92P2 of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10, and the IC chip 90 is attached by performing reflow. Similarly, the printed wiring board 10 is attached to the daughter board 95 by reflowing so that the pads 94P1 and 94P2 of the daughter board 95 correspond to the solder bumps 76D of the printed wiring board 10.
[0081]
Next, a printed wiring board according to a modification of the first embodiment of the present invention will be described with reference to FIG. The modified printed wiring board is substantially the same as that of the first embodiment described above. However, in the printed wiring board of this modified example, the conductive pin 84 is provided and formed so as to be connected to the daughter board via the conductive pin 84.
[0082]
FIG. 13B shows a cross section of the chip capacitor 20 according to the first modification. In the first embodiment, the surface of the capacitor is roughened to improve the adhesion with the resin. However, in the modified example, the surface wettability is improved by forming the polyimide film 23b instead. It is. Instead of the polyimide film, a silane coupling process can be applied to the surface of the capacitor.
[0083]
In the first modified example, a composite metal film 28 composed of an electroless copper plating film 28 a and an electrolytic copper plating film 28 b is formed on the conductive paste 26. The thickness of the composite metal film 28 is desirably 0.1 to 10 μm, and optimally 1 to 5 μm. Instead of the composite metal film, it is also possible to form a single-layer metal film.
[0084]
In the first modified example, since the metal layer 28 is provided on the conductive paste 26 of the electrodes 21 and 22 of the capacitor 20, the occurrence of migration at the electrodes 21 and 22 can be prevented, and the connection resistance is reduced. Further reduction can be achieved. The electrodes 21 and 22 made of metallized have irregularities on their surfaces, and even if they are directly connected with the adhesive material 36, they cannot be completely adhered, but a conductive paste 26 is applied and a metal layer 28 is further provided. Therefore, the unevenness can be completely eliminated, the adhesion can be improved, and the connection resistance can be lowered.
[0085]
In the first embodiment described above, only the chip capacitor 20 accommodated in the core substrate 30 is provided. However, in the first modified example, large-capacity chip capacitors 86 are mounted on the front surface and the back surface.
[0086]
An IC chip consumes a large amount of power instantaneously and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in the modified example, a chip capacitor 20 for power supply and a chip capacitor 86 are provided on the printed wiring board. The effect of this chip capacitor will be described with reference to FIG.
[0087]
In FIG. 12, the vertical axis represents voltage supplied to the IC chip, and the horizontal axis represents time. Here, an alternate long and two short dashes line C indicates a voltage fluctuation of a printed wiring board not provided with a power supply capacitor. When the power supply capacitor is not provided, the voltage is greatly attenuated. A broken line A indicates voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. The voltage does not drop much as compared with the two-dot chain line C, but the loop length becomes long, so the rate-determining power supply cannot be sufficiently performed. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board incorporating the chip capacitor described above with reference to FIG. Although the loop length can be shortened, the voltage fluctuates because a large-capacity chip capacitor cannot be accommodated in the core substrate 30. Here, the solid line E indicates the voltage fluctuation of the modified printed wiring board in which the chip capacitor 20 in the core substrate described above with reference to FIG. 9 and the large-capacity chip capacitor 86 are mounted on the surface. By providing the chip capacitor 20 in the vicinity of the IC chip and the chip capacitor 86 having a large capacity (and relatively large inductance), voltage fluctuation is minimized.
[0088]
Next, a printed wiring board according to a second embodiment of the present invention will be described with reference to FIG.
The configuration of the printed wiring board of the second embodiment is substantially the same as that of the first embodiment described above. However, in the printed wiring board 210 of the second embodiment, the conductor circuit 35 is formed on one side of the first resin substrate 30a and the third resin substrate 30c, and the second resin substrate 30b provided with the opening 30B for accommodating the chip capacitor 20 is provided. Conductor circuits 37 are formed on both sides. In the second embodiment, since the conductor circuit 35 is formed on one side of the first resin substrate 30a and the third resin substrate 30c and the conductor circuit 37 is formed on both sides of the second resin substrate 30b, the wiring density is increased. There is an advantage that the number of interlayer resin insulation layers to be built up can be reduced. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0089]
A manufacturing process of the printed wiring board according to the second embodiment of the present invention will be described with reference to FIGS.
[0090]
(1) A first resin substrate 30a is prepared by impregnating a core material such as a glass cloth having a thickness of 0.1 mm with a BT (bismaleimide triazine) resin and curing it. On the first resin substrate 30a, a conductive pad portion 34 is formed on one side, and a conductor circuit 35 is formed on the other side. Next, a plurality of chip capacitors 20 are placed on the conductive pad portion 34 via an adhesive material 36 such as solder or conductive paste, and the chip capacitor 20 is connected to the conductive pad portion 34 (see FIG. 10A). ).
[0091]
(2) Next, prepregs (adhesive resin layers) 38a and 38b in which a core material such as glass cloth is impregnated with an epoxy resin, and a second resin substrate 30b in which a core material such as glass cloth is impregnated with BT resin and cured. A thickness 0.4 mm) and a third resin substrate 30c (thickness 0.1 mm) are prepared. In the prepreg 38a and the second resin substrate 30b, through holes 38A and 30B capable of accommodating the chip capacitor 20 are formed. Moreover, the conductor circuit 37 is formed on both surfaces of the second resin substrate 30b, and the conductor circuit 35 is formed on one surface of the third resin substrate 30c. First, the second resin substrate 30b is placed on the surface of the third resin substrate 30c where the conductor circuit 35 is not formed via the prepreg 38b. The first resin substrate 30a is inverted and placed on the second resin substrate 30b via the prepreg 38a. That is, the chip capacitors 20 connected to the first resin substrate 30a are stacked so as to be accommodated in the openings 30B formed in the second resin substrate 30b (see FIG. 10B).
[0092]
(3) Then, the first, second, and third resin substrates 30a, 30b, and 30c are integrated in a multilayer shape by press-pressing the stacked substrates using a hot press, and a plurality of chip capacitors 20 are integrated. Is formed (see FIG. 10C). First, by applying pressure, an epoxy resin (insulating resin) is pushed out from the prepregs 38 a and 38 b to fill the gap between the opening 30 </ b> B and the chip capacitor 20. Furthermore, the epoxy resin is cured by being heated simultaneously with the pressurization, and the prepregs 38a and 38b are interposed as adhesive resins, whereby the first resin substrate 30a, the second resin substrate 30b, and the third resin substrate 30c Is firmly bonded.
[0093]
(4) A thermosetting resin film is vacuum-bonded and laminated at a pressure of 5 kg / cm ² while raising the temperature to a temperature of 50 to 150 ° C. on the substrate that has undergone the above-described steps, thereby providing an interlayer resin insulation layer 40 (FIG. 10D). reference). The degree of vacuum at the time of vacuum bonding is 10 mmHg.
[0094]
(5) Next, via hole openings 42 connected to the conductor pad portions 34 and the conductor circuits 35 and 37 are formed by laser on the upper and lower surfaces of the substrate 30 (see FIG. 10E).
Subsequent steps are the same as (7) to (19) of the first embodiment described above, and thus description thereof is omitted.
[0095]
The configuration of the printed wiring board according to the third embodiment of the present invention will be described with reference to FIG.
The configuration of the printed wiring board of the third embodiment is substantially the same as that of the first embodiment described above. However, the chip capacitor 20 accommodated in the core substrate 30 is different. FIG. 14 is a plan view of the chip capacitor. FIG. 14A shows a chip capacitor before cutting for multi-piece cutting, and a one-dot chain line in the drawing indicates a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are disposed on the side edge of the chip capacitor as shown in the plan view of FIG. FIG. 14C shows the chip capacitor before cutting for multi-piece fabrication according to the third embodiment, and the alternate long and short dash line in the drawing indicates the cutting line. In the printed wiring board of the third embodiment, the first electrode 21 and the second electrode 22 are disposed inside the side edge of the chip capacitor as shown in the plan view of FIG. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0096]
In the printed wiring board of the third embodiment, since the chip capacitor 20 having electrodes formed inside the outer edge is used, a chip capacitor having a large capacity can be used.
[0097]
Next, a printed wiring board according to a first modification of the third embodiment will be described with reference to FIG.
FIG. 15 is a plan view of the chip capacitor 20 accommodated in the core substrate of the printed wiring board according to the first modification. In the first embodiment described above, a plurality of small-capacity chip capacitors are accommodated in the core substrate. However, in the first modification, a large-capacity large-sized chip capacitor 20 is accommodated in the core substrate. Here, the chip capacitor 20 includes a first electrode 21, a second electrode 22, a dielectric 23, a first conductive film 24 connected to the first electrode 21, and a second electrode connected to the second electrode 22 side. The conductive film 25 and the connection electrodes 27 on the upper and lower surfaces of the chip capacitor not connected to the first conductive film 24 and the second conductive film 25 are formed. The IC chip side and the daughter board side are connected via this electrode 27.
[0098]
Since the large-sized chip capacitor 20 is used in the printed wiring board of the first modified example, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0099]
A printed wiring board according to a second modification will be described with reference to FIG. FIG. 16A shows a chip capacitor before cutting for multi-piece production. In the drawing, a one-dot chain line shows a normal cutting line, and FIG. 16B shows a plan view of the chip capacitor. . As shown in FIG. 16B, in this second modified example, a plurality of chip capacitors (three in the example in the figure) are connected and used in a large format.
[0100]
In the second modified example, since a large chip capacitor 20 is used, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0101]
In the third embodiment described above, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, it is also possible to use a plate-like capacitor in which a conductive film is provided on a ceramic plate.
[0102]
【Effect of the invention】
According to the manufacturing method of the present invention, the capacitor can be accommodated in the core substrate, and the distance between the IC chip and the capacitor is shortened, so that the loop inductance of the printed wiring board can be reduced. Further, since the resin substrate is laminated, sufficient strength can be obtained for the core substrate. Furthermore, since the core substrate is configured smoothly by disposing the first resin substrate and the third resin substrate on both surfaces of the core substrate, an interlayer resin insulating layer and a conductor circuit can be appropriately formed on the core substrate. It is possible to reduce the occurrence rate of defective printed wiring boards.
In addition, since the conductive paste is applied to the surface of the electrode made of metallization of the capacitor, the electrical connectivity of the electrode made of metallization and having high surface resistance can be improved. In addition, electrodes made of metallized have irregularities on the surface, and even if they are directly connected with a conductive adhesive, they cannot be adhered completely, but the conductive paste can eliminate irregularities and improve adhesion. The connection resistance can be lowered. In addition, since the electrode made of metallized is in contact with the surrounding resin layer via the conductive paste, the generation of stress due to the difference in thermal expansion between the electrode and the resin layer is suppressed, and the resin layer is not cracked or peeled off.
Also, migration can be prevented when the capacitor is covered with copper.
[Brief description of the drawings]
1A, 1B, 1C and 1D are manufacturing process diagrams of a printed wiring board according to a first embodiment of the present invention.
FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. FIGS.
FIGS. 3A, 3B, 3C and 3D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. FIGS.
4A, 4B, 4C, and 4D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
5A, 5B, and 5C are manufacturing process diagrams of a printed wiring board according to the first embodiment of the present invention.
6A and 6B are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view of the printed wiring board according to the first embodiment of the present invention.
8 is a cross-sectional view showing a state where an IC chip is mounted on the printed wiring board in FIG. 7 and attached to the daughter board.
FIG. 9 is a cross-sectional view showing a state where an IC chip is mounted on a printed wiring board according to a modification of the first embodiment of the present invention.
10 (A), (B), (C), (D), and (E) are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
FIG. 11 is a cross-sectional view of a printed wiring board according to a second embodiment of the present invention.
FIG. 12 is a graph showing changes in supply voltage to IC chip and time.
13A is a cross-sectional view of the chip capacitor of the first embodiment, and FIG. 13B is a cross-sectional view of the chip capacitor of the first modified example of the first embodiment.
14A, 14B, 14C, and 14D are plan views of a chip capacitor of a printed wiring board according to a third embodiment.
FIG. 15 is a plan view of a chip capacitor of the printed wiring board according to the third embodiment.
FIG. 16 is a plan view of a chip capacitor of a printed wiring board according to a modification of the third embodiment.
[Explanation of symbols]
20 Chip Capacitor 21 First Electrode 22 Second Electrode 23 Dielectric 23a Roughened Surface 23b Polyimide Film 26 Conductive Paste 28a Electroless Copper Plating Film 28b Electrolytic Copper Plating Film 28 Composite Metal Film 30 Core Substrate 30a First Resin Substrate 30b First 2 resin substrate 30c 3rd resin substrate 30B Opening 34 Conductor pad part 35 Conductor circuit 36 Adhesive material 37 Conductor circuit 38a, 38b Adhesive resin layer (adhesion plate)
40 Interlayer resin insulation layer 56 Through hole 58 Conductor circuit 60 Via hole 70 Solder resist layer 71 Opening 72 Nickel plating layer 74 Gold plating layer 76U, 76D Solder bump 80A, 80B Build-up wiring layer 90 IC chip 92P1, 92P2 Solder pad ( IC chip side)
94P1, 94P2 Solder pad (Daughter board side)
95 Daughter board 96 Conductive connection pin 140 Interlayer resin insulation layer 158 Conductor circuit 160 Via hole 240 Interlayer resin insulation layer 258 Conductor circuit 260 Via hole

Claims (17)

A printed wiring board formed by alternately laminating an interlayer resin insulation layer and a conductor circuit on a core substrate containing a capacitor,
A core substrate that accommodates the capacitor includes a first resin substrate having the conductor circuit formed on the surface thereof, a second resin substrate having an opening that accommodates the capacitor, and a third resin substrate. Interposing and laminating,
On the surface of the electrode made of metallization of the capacitor, a conductive paste is applied,
On the conductive paste of the capacitor electrode, a metal layer made of a copper plating film is provided,
The printed wiring board, wherein the first resin substrate is formed by copper plating and has a via hole connected to the capacitor electrode.   The printed wiring board according to claim 1, wherein a surface of the capacitor is roughened.   The printed wiring board according to claim 1, wherein a surface wettability improving process is performed on a surface of the capacitor.   The printed wiring board according to any one of claims 1 to 3, wherein the adhesive plate is formed by impregnating a core material with a thermosetting resin.   The printed wiring board according to any one of claims 1 to 4, wherein the first, second, and third resin substrates are formed by impregnating a core material with a resin.   The printed wiring board according to claim 1, wherein the capacitor includes a plurality of capacitors.   The printed wiring board manufacturing method according to claim 1, wherein a conductor circuit is formed on the second resin substrate.   The printed wiring board according to claim 1, wherein a capacitor is mounted on a surface of the printed wiring board.   9. The printed wiring board according to claim 8, wherein the capacitance of the capacitor on the surface is equal to or greater than the capacitance of the inner layer capacitor.   The printed wiring board according to claim 9, wherein an inductance of the capacitor on the surface is equal to or greater than an inductance of the capacitor on the inner layer.   The first resin substrate and the capacitor are joined with an insulating adhesive, and the insulating adhesive has a smaller coefficient of thermal expansion than the first resin substrate. Printed wiring board. The opening in which the capacitor is accommodated is filled with resin,
The printed wiring board according to claim 1, wherein a through-hole penetrating the core substrate through the resin filled in the opening is formed.   The printed wiring board according to claim 12, wherein the resin filled in the opening contains an inorganic filler.   The printed wiring board according to claim 1, wherein a chip capacitor in which an electrode is formed inside an outer edge is used as the capacitor.   The printed wiring board according to claim 1, wherein a chip capacitor in which electrodes are formed in a matrix is used as the capacitor.   The printed wiring board according to any one of claims 1 to 15, wherein a plurality of chip capacitors for connection are used as the capacitor. A method for producing a printed wiring board comprising at least the following steps (a) to (f):
(A) forming a conductive pad made of copper on the first resin substrate;
(B) A capacitor in which a conductive paste is applied on the metallized electrode via a conductive adhesive and a metal layer is provided on the conductive paste is connected to the conductor pad of the first resin substrate. Process;
(C) a third resin substrate having a conductor circuit formed on the surface thereof, a second resin substrate having an opening for accommodating the capacitor, and the first resin substrate, the first resin substrate Stacking a capacitor in the opening of the second resin substrate and interposing an adhesive plate so as to close the opening of the second resin substrate with a third resin substrate;
(D) a step of heating and pressurizing the first resin substrate, the second resin substrate, and the third resin substrate to form a core substrate;
(E) on the conductive paste, is constituted by a copper plating film, providing the metal layer connected to said conductor pad step;
(F) forming a via hole formed on the first resin substrate by copper plating and connected to the electrode of the capacitor via the conductor pad;

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