JP2001156457A - Manufacturing method of electronic circuit device - Google Patents

Abstract

(57) Abstract: Provided is a method of manufacturing an electronic circuit device having improved reliability of conductive connection between a pad of a semiconductor integrated circuit and a circuit board. SOLUTION: A bare chip 12 of a semiconductor integrated circuit is mounted on a base substrate 11a with a surface on which a terminal pad 12a is formed facing upward, and then insulated on an upper surface of the base substrate 11a so as to cover the terminal pad 12a of the bare chip 12. Layer 1
1b, the insulating layer 11b on the terminal pad 12a is removed to form a via hole 15, and the via hole 15 is filled with a conductor 16 electrically conductively connected to the terminal pad 12a, and then a wiring conductor is formed on the upper surface of the insulating layer 11b. 14 is formed. Further, the insulating layer 11c is formed on the wiring conductor 14. The electronic circuit device 10 is manufactured by a build-up method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit device having a multilayer structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of electronic devices, electronic circuit devices in which bare chips of semiconductor integrated circuits (ICs) are mounted at high density have been used. Further, circuit boards used in electronic circuit devices are multilayered to reduce the size of the circuit boards, and when multilayering circuit boards, the use of build-up boards is increasing.

On the other hand, when a bare chip of a semiconductor IC is mounted on a circuit board, flip-chip connection is performed in which signal pads of the bare chip are directly connected to connection lands on the circuit board and mounted.

In general, a bare chip of a semiconductor IC has pads constituting electrodes arranged along a peripheral edge of one surface thereof. When the bare chip is directly mounted on a circuit board, solder bumps are formed on the surface of the pad. Flip chip connection is performed in which the solder bumps are formed and the connection lands of the circuit board are electrically connected through an anisotropic conductive film or an anisotropic conductive resin.

[0005]

However, since the pitch between pads of a semiconductor IC bare chip is becoming narrower with the recent development of miniaturization technology, anisotropic conductive films and resins have been developed. The size of the mixed conductive particles is approaching the size of the pads of the semiconductor IC bare chip and the pitch between the pads, so that a short circuit between the pads often occurs. This is one factor that does not reduce the manufacturing cost.

An object of the present invention is to provide a method of manufacturing an electronic circuit device in which the reliability of conductive connection between a pad of a semiconductor integrated circuit and a circuit board is improved in view of the above problems.

[0007]

According to the present invention, there is provided an electronic circuit device comprising a multilayer circuit board and a chip-shaped electronic component having terminal pads on one main surface. A method of mounting the chip-shaped electronic component on a base substrate with the main surface on which the terminal pads are formed facing upward, and mounting the chip-shaped electronic component on the base substrate on the upper surface of the base substrate. Forming an insulating layer so as to cover the terminal pad from the side surface to the upper surface of the chip-shaped electronic component; removing a portion of the insulating layer on the terminal pad to form a via hole; In addition, the present invention proposes a method of manufacturing an electronic circuit device by performing a step of filling a conductor to be conductively connected to the terminal pad and a step of forming a wiring conductor on the upper surface of the insulating layer.

In the method of manufacturing an electronic circuit device, after the chip-shaped electronic component is mounted on the base substrate with the main surface on which the terminal pad is formed facing upward, the terminal pad of the chip-shaped electronic component is removed. An insulating layer is formed on the upper surface of the base substrate so as to cover, the insulating layer on the terminal pad is removed to form a via hole, and after the via hole is filled with a conductor conductively connected to the terminal pad, A wiring conductor is formed on the upper surface of the insulating layer, and an electronic circuit device is manufactured by a build-up method. Thus, an electronic circuit device in which the chip-shaped electronic component is embedded inside the multilayer circuit board is manufactured.

According to a second aspect of the present invention, in the method for manufacturing an electronic circuit device according to the first aspect, after a second insulating layer is further formed on the insulating layer on which the wiring conductor is formed, a predetermined position of the wiring conductor is formed. The upper second insulating layer is removed to form a via hole, and the via hole is filled with a conductor conductively connected to the wiring conductor to manufacture an electronic circuit device.

According to a third aspect of the present invention, in the method for manufacturing an electronic circuit device according to the first aspect, a photosensitive resin having electrical insulating properties is used as a material for forming the insulating layer, and the photosensitive resin is formed on the insulating layer. A method for manufacturing an electronic circuit device, comprising exposing and curing the photosensitive resin through a photomask covering a target portion and covering a position where the via hole is to be formed, and then removing the unexposed portion to form the via hole. Suggest.

In the method of manufacturing an electronic circuit device, since the insulating layer is formed using a photosensitive resin, an insulating layer having a desired thickness can be easily formed, and a via hole having a desired diameter can be formed at a desired position. It can be formed accurately.

According to a fourth aspect of the present invention, in the method of manufacturing an electronic circuit device according to the first aspect, the terminal pad uses a chip-shaped electronic component made of copper, and is electrically connected to the terminal pad in the via hole. In the step of filling the body, the oxide layer on the surface of the terminal pad exposed in the via hole is removed, the surface of the terminal pad is subjected to palladium treatment, and then a copper plating layer is chemically grown on the surface of the terminal pad. The present invention proposes a method of manufacturing an electronic circuit device that fills the via holes with a conductor.

In the method of manufacturing the electronic circuit device, the oxide layer of the terminal pad is removed and palladium treatment is applied to attach palladium on the surface of the terminal pad, thereby facilitating the growth of the chemical copper plating layer. ing.

According to a fifth aspect of the present invention, in the method of manufacturing an electronic circuit device according to the first aspect, the step of forming a wiring conductor on the surface of the insulating layer includes the step of forming the wiring conductor after roughening the surface of the insulating layer. A method of manufacturing an electronic circuit device to be formed is proposed.

In the method of manufacturing an electronic circuit device, a contact area between the surface of the insulating layer and the wiring conductor is increased by forming the wiring conductor after roughening the surface of the insulating layer,
The adhesive strength between them increases.

According to a sixth aspect of the present invention, in the method for manufacturing an electronic circuit device according to the first aspect, it is preferable that copper is used as a conductor filled in the via hole and a wiring conductor is formed on an upper surface of the insulating layer. Forming a copper plating layer chemically on the surface of the insulating layer and the conductor, coating the surface of the copper plating layer with a photosensitive resin, and applying a photomask covering a position where the wiring conductor is formed; After exposing and curing the photosensitive resin, and further exposing the copper plating layer by removing the non-exposed portion of the photosensitive resin, the copper plating layer is immersed in a copper pyrophosphate plating solution, and the copper plating layer is energized, and After electrically growing a copper plating layer on the exposed portion of the plating layer, the wiring conductor is formed by removing the photosensitive resin and removing the exposed portion of the chemically formed copper plating layer. . Thus, the wiring conductor can be easily formed.

According to a seventh aspect of the present invention, in the method for manufacturing an electronic circuit device according to the first aspect, in the step of forming the insulating layer, the resin is cured by spin-coating a resin having an electrical insulation property. The insulating layer is used.

According to an eighth aspect of the present invention, in the method for manufacturing an electronic circuit device according to the second aspect, a step of forming a land conductively connected to a conductor in a via hole on a surface of the second insulating layer; Mounting an electronic component on the surface of the insulating layer and conductively connecting a terminal electrode of the electronic component to the land.

According to the method of manufacturing an electronic circuit device, an electronic circuit device in which electronic components are mounted on a multilayer circuit board in which chip-shaped electronic components are embedded is formed.

In a ninth aspect of the present invention, there is provided a method for manufacturing an electronic circuit device according to the first aspect, wherein the chip-shaped electronic component is a bare chip of a semiconductor integrated circuit element.

According to the method of manufacturing an electronic circuit device, a multilayer circuit board in which a bare chip of a semiconductor integrated circuit element is embedded can be easily manufactured.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a side sectional view showing an electronic circuit device according to a first embodiment of the present invention. In the figure, 10
Denotes an electronic circuit device, in which a bare chip 12 of a semiconductor integrated circuit is embedded in a multilayer circuit board 11, and solder bumps 1 as external electrodes connected to terminal pads of the bare chip 12.
3 is provided on the upper surface of the multilayer circuit board 11. That is, the electronic circuit device 10 is one in which the package of the bare chip 12 is formed by a multilayer circuit board.

The multilayer circuit board 11 includes a plurality of insulating layers 11a.
11c, a wiring conductor 14 provided between the insulating layers, and a conductor 16 filled in the via hole 15. The lowermost insulating layer 11a shown in the figure serves as a base substrate, and its material is resin, metal, ceramics, or the like. The other insulating layers 11b and 11c are formed of resin.

The bare chip 12 has a rectangular plate shape.
It has a plurality of terminal pads 12a made of copper (Cu) arranged in a grid on one main surface (the upper surface in FIG. 1). Each of the plurality of terminal pads 12a is conductively connected to the solder bump 13 formed on the surface of the uppermost insulating layer 11c via the conductor 16 and the wiring conductor 14 in the via hole 15.

The electronic circuit device 10 having the above configuration is formed by the following manufacturing method. Hereinafter, a method of manufacturing the electronic circuit device 10 will be described with reference to FIGS.

First, an alumina substrate 2 having a thickness of 0.3 mm
1 is prepared as an insulating layer 11a to be a base substrate. The epoxy resin 22 is bonded to the upper surface of the insulating layer 11a with the back surface of the bare chip 12 facing upward, that is, with the surface on which the terminal pads 12a are formed as the upper surface (FIG. 2).

Here, the epoxy resin 22 is applied so as to have a thickness of 5 μm after being cured. Further, the difference between the linear expansion coefficient of the epoxy resin 22 and the linear expansion coefficient of the alumina substrate 21 or silicon (Si) is ± 20.
Adjusted to within%.

Next, an epoxy photosensitive resin (viscosity: 20 ps) having resistance to the plating solution used below 2
3 is a bare chip 12 disposed on an alumina substrate 21.
(FIG. 3). At this time, the spin coater is adjusted so that the bare chip 12 is applied with a thickness of 20 μm. As the resin of the insulating layer, polyimide or the like may be used as long as it has resistance to a plating solution.

Next, after the photosensitive resin 23 is dried, the photosensitive resin 23 is exposed and developed using a photomask (not shown) in which a pattern is arranged so as to cover only the Cu terminal pads 12a of the bare chip 12. And cure. Thus, an insulating layer 11b having an opening only at the upper portion of the Cu terminal pad 12a is formed (FIG. 4). The opening 23a becomes the via hole 15.

Next, after removing the oxide layer formed on the surface of the Cu terminal pad 12a with an acidic solution, palladium treatment is performed. Palladium selectively adheres to the surface of the Cu terminal pad 12a. Thereafter, a chemical Cu plating process is performed. Thereby, the Cu plating layer 24 grows on the Cu terminal pad 12a. Thus, the via hole 15
Is chemically filled until Cu is completely filled with the Cu plating layer 24 (FIG. 5). The Cu plating layer 24 filled in the via hole 15 becomes the conductor 16.

After the via holes 15 are filled with the Cu plating 24, the surface of the insulating layer 11b is appropriately roughened using a solution containing potassium permanganate as a main component. Thereby, the contact area between the surface of the insulating layer 11b and the wiring conductor 14 formed thereon is increased, the adhesive strength between them can be increased, and the reliability can be improved.

Next, the upper surface of the Cu filled in the insulating layer 11b and the via hole 15 is subjected to chemical Cu plating to form a Cu plating layer 25 having a thickness of 0.3 μm (FIG. 6).

Next, the surface of the chemical Cu plating layer 25 is coated with a photosensitive resin 26 to a thickness of 10 μm (FIG. 7).

Next, after drying the photosensitive resin 26, 1
The photosensitive resin 26 is exposed, developed, and cured using a photomask (not shown) on which the wiring pattern of the layer is arranged. Thus, the opening 26 corresponding to the wiring pattern
An insulating layer on which a is formed is formed (FIG. 8).

Thereafter, a current is applied to the chemical Cu plating layer 25 in a Cu pyrophosphate plating bath (current density: 60 A / m ² ),
An electrical Cu plating layer 27 is grown to a height of 10 μm in the wiring pattern opening 26a (FIG. 9).

Next, after the insulating layer formed of the photosensitive resin 26 is removed with a dedicated stripper (FIG. 10), 8% w
Using a t-HCl solution, only the exposed portion of the chemical Cu plating layer 25 is completely removed (FIG. 11). Thus, the first-layer wiring conductor 14 is formed.

Thereafter, the surface of the electric Cu plating layer 27 is
Blackening treatment with a solution mainly containing sodium chlorite,
The same photosensitive resin (viscosity: 20 ps) 23 is spin-coated so as to cover the Cu plating layer 27 (FIG. 12).
At this time, the spin coater is adjusted so as to be applied on the Cu plating layer 27 with a thickness of 20 μm.

Next, after the photosensitive resin 23 is dried, the photosensitive resin 23 is exposed and developed using a photomask (not shown) in which a pattern is arranged so as to cover only the position where the via hole 15 is formed. Let it cure. The photomask used at this time has a pattern of a via hole 15 for connecting the first layer wiring and the second layer wiring.

Thus, the opening 2 serving as the via hole 15 is formed.
An insulating layer 11c on which the insulating layer 3a is formed is formed.
3).

Next, C exposed at the bottom of the opening 23a
After removing the oxide layer formed on the surface of the u wiring conductor 14 with an acidic solution, palladium treatment is performed in the same manner as described above.
Palladium selectively adheres to the surface of the Cu wiring conductor 14. Thereafter, a chemical Cu plating process is performed. As a result, the Cu plating layer 28 grows on the Cu wiring conductor 14. Thus, chemical Cu plating is performed until the via hole 15 is completely filled with the Cu plating layer 28 (FIG. 14). The Cu plating layer 28 filled in the via hole 15 becomes the conductor 16.

After the via hole 15 is filled by Cu plating, the solder bump 13 is formed on the Cu plating layer 28 in the via hole 15 exposed on the surface of the outermost insulating layer 11c (FIG. 15). Thereby, the electronic circuit device 10 is completed.

The solder bumps 13 are formed by plating or solder balls. Further, a bonding pad may be formed instead of the solder bump 13.

By appropriately repeating the above steps, a multilayer circuit board having a desired number of layers can be formed. Further, other bare chips can be embedded in an arbitrary layer, and chip-like electronic components other than bare chips can be easily embedded.

According to the above-described manufacturing method, the bare chip 1
Via hole 1 in the insulating layer 11b on the second terminal pad 12a.
5 is formed and the conductor 16 is filled in the via hole 15 by Cu plating, so that the electrical connection between the terminal pad 12a and the conductor 16 can be improved.

Further, via holes 15 are formed by utilizing photosensitivity.
Since the via holes 15 having a small diameter can be easily formed, even if the pitch between the terminal pads 12a of the bare chip 12 becomes narrow, sufficient insulation between adjacent via holes can be maintained. Can be.

Further, the via holes 15 are formed by plating.
Since the inside is filled with the conductor 16, it can be easily formed.

Next, a second embodiment of the present invention will be described.

FIG. 16 is a side sectional view showing an electronic circuit device 30 according to the second embodiment. In the figure, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and description thereof is omitted. The difference between the second embodiment and the first embodiment is that, instead of the alumina substrate 21 serving as the base substrate, a base made of a metal 32 having a high thermal conductivity and another made of a resin is used. That is, the substrate 31 is used. The bare chip 12 is mounted on the upper surface of the metal 32. As a result, heat generated from the bare chip 12 can be efficiently radiated to the outside.

Next, a third embodiment of the present invention will be described.

FIG. 17 is a side sectional view showing an electronic circuit device 40 according to the third embodiment. In the figure, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and description thereof is omitted. The difference between the third embodiment and the first embodiment is that the number of layers is increased and four insulating layers 4 are provided.
A multilayer circuit board 41 having 1a to 41d is provided. A component mounting land 42 and a wiring conductor 43 are formed on the upper surface of the multilayer circuit board 41, and an electronic component 44 is mounted thereon. Is formed. In this case, the manufacturing method is the same as that of the first embodiment.

The above-described embodiment is a specific example of the present invention, and the present invention is not limited to only these.

[0053]

As described above, according to the method for manufacturing an electronic circuit device according to the first to ninth aspects of the present invention, a chip-shaped electronic component is embedded in a multilayer circuit board, and Since a via hole is formed on the terminal pad of the component, a conductor is filled and the terminal pad and the conductor are connected, and then a wiring conductor connected to the conductor is formed. The electrical connection between the pad and the conductor and the wiring conductor can be improved, and even if the pitch between the terminal pads becomes narrow, the terminal pads are hardly short-circuited.

According to the third aspect, in addition to the above-described effects, the via hole is formed by utilizing photosensitivity, so that a via hole having a small diameter can be formed, and the terminal of the chip-shaped electronic component can be formed. Even if the pitch between pads is narrower,
It is possible to sufficiently maintain insulation between adjacent via holes.

According to the fourth aspect, in addition to the above effects, the conductor in the via hole conductively connected to the terminal pad can be easily formed.

According to the fifth aspect, in addition to the above effects, the wiring conductor is formed after the surface of the insulating layer is roughened, so that the contact area between the surface of the insulating layer and the wiring conductor is increased. Thus, the adhesive strength between them can be increased, and the reliability can be improved.

According to the sixth aspect, in addition to the above effects, a wiring conductor can be easily formed on the insulating layer.

According to the seventh aspect, in addition to the above effects, an insulating layer having a flat surface and no irregularities can be easily formed.

According to the eighth aspect, in addition to the above effects, the size of the electronic circuit device provided with the chip-shaped electronic components can be reduced.

According to the ninth aspect, in addition to the above effects, the electronic circuit device having the bare chip of the semiconductor integrated circuit can be reduced in size, and the multilayer circuit board in which the bare chip of the semiconductor integrated circuit is embedded. It is also possible to make the package itself a bare chip.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing an electronic circuit device according to a first embodiment of the present invention.

FIG. 2 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 4 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 5 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 6 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 7 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 8 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 9 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 10 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 11 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 12 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 13 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 14 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 15 is a process chart illustrating a manufacturing method according to the first embodiment of the present invention.

FIG. 16 is a side sectional view showing an electronic circuit device according to a second embodiment of the present invention.

FIG. 17 is a side sectional view showing an electronic circuit device according to a third embodiment of the present invention.

[Explanation of symbols]

10, 30, 40: electronic circuit device, 11: multilayer circuit board, 11a, 11b, 11c: insulating layer, 12: semiconductor integrated circuit bare chip, 12a: terminal pad, 13: solder bump, 14: wiring conductor, 15: via hole , 16: Conductor, 21: Alumina substrate, 22: Epoxy resin, 23
... photosensitive resin, 23a ... opening, 24 ... Cu plating layer,
25: Cu plating layer, 26: photosensitive resin, 27: Cu plating layer, 28: Cu plating layer, 31: base substrate, 32
... thermal conductive metal, 41 ... multilayer circuit board, 41a-41d
... an insulating layer, 42 ... land, 43 ... wiring conductor, 44 ... electronic components, 45 ... solder bumps.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hiroya Shigemoto 6-16-20 Ueno, Taito-ku, Tokyo Taiyo Denki Co., Ltd. F-term (reference) 5E336 AA11 BB03 CC32 CC58 GG11 5E346 AA43 CC08 CC32 CC40 DD23 DD24 DD44 EE35 EE38 FF07 FF13 FF14 FF37 FF45 GG17 GG18 GG22 GG28 HH07 HH31 5F061 AA02 BA03 CA10 CB02 CB13

Claims (9)

[Claims] 1. A method for manufacturing an electronic circuit device comprising: a multilayer circuit board; and a chip-shaped electronic component having terminal pads on one main surface, wherein the main surface on which the terminal pads are formed faces upward. Mounting the chip-shaped electronic component on a base substrate by using an insulating layer on the upper surface of the base substrate so as to cover the terminal pad from the side surface to the upper surface of the chip-shaped electronic component mounted on the base substrate. Forming a via hole by removing a portion of the insulating layer on the terminal pad; filling a conductive material in the via hole to be conductively connected to the terminal pad; And a step of forming a wiring conductor on the upper surface to manufacture an electronic circuit device. A step of forming a second insulating layer on the insulating layer on which the wiring conductor is formed; a step of removing a second insulating layer above a predetermined position of the wiring conductor to form a via hole; Filling the via hole with a conductor conductively connected to the wiring conductor. 2. The method according to claim 1, further comprising: 3. A photosensitive resin having electrical insulation properties is used as a material for forming the insulating layer, and the photosensitive resin is coated on a portion where the insulating layer is to be formed, and a photomask covering a position where the via hole is to be formed is provided. 2. The method according to claim 1, wherein the via hole is formed by exposing and curing the photosensitive resin, and then removing an unexposed portion. 4. A step of using a chip-shaped electronic component in which said terminal pad is made of copper and filling said via hole with a conductor electrically conductively connected to said terminal pad, comprising: Removing the oxide layer, subjecting the surface of the terminal pad to palladium treatment, and then filling the via hole with a conductor by chemically growing a copper plating layer on the surface of the terminal pad. Item 2. A method for manufacturing an electronic circuit device according to Item 1. 5. The method for manufacturing an electronic circuit device according to claim 1, wherein in the step of forming a wiring conductor on the surface of the insulating layer, the wiring conductor is formed after roughening the surface of the insulating layer. . 6. A step of using copper as a conductor filled in the via hole and forming a wiring conductor on an upper surface of the insulating layer, chemically forming a copper plating layer on the surface of the insulating layer and the conductor. Forming, covering the surface of the copper plating layer with a photosensitive resin, exposing and curing the photosensitive resin through a photomask covering a position where the wiring conductor is formed, and further exposing the photosensitive resin in an unexposed portion. Is removed to expose the copper plating layer, the copper plating layer is immersed in a copper pyrophosphate plating solution, and the copper plating layer is energized to electrically grow the copper plating layer on the exposed portion of the copper plating layer. 2. The method according to claim 1, wherein the wiring conductor is formed by removing the photosensitive resin and removing an exposed portion of the chemically formed copper plating layer. 7. The electronic circuit device according to claim 1, wherein in the step of forming the insulating layer, a resin having an electrical insulation property is spin-coated, and then the resin is cured to form the insulating layer. Manufacturing method. 8. A step of forming a land conductively connected to a conductor in a via hole on a surface of the second insulating layer; mounting an electronic component on a surface of the second insulating layer; 3. The method for manufacturing an electronic circuit device according to claim 2, further comprising: a step of conductively connecting to the land. 9. The method of manufacturing an electronic circuit device according to claim 1, wherein said chip-shaped electronic component is a bare chip of a semiconductor integrated circuit device.