JP2000114549A - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To give a semiconductor element for electric power a high breakdown strength. SOLUTION: Plate rings 11 of which width in the element radial direction is smaller than that of plate rings 84 are provided for each groove 83 on a plurality (two shown in the figure) of guard ring layers 81a formed adjacent to the outermost part 63a of a p-type anode layer. The width in the element radial direction in the plate rings 11 is equal to or smaller than the width in the element radial direction of the guard ring layer 81a positioned right below the plate rings 11. On the other hand, the width in the element radial direction of the plate rings 84 provided on the side of the element end of the plate rings 11 is larger than the sum of the width in the element radial direction in the guard ring layer 81 positioned right below the plate rings 84 and that in the electric field concentration region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-voltage type power semiconductor device, and more particularly to a semiconductor device such as a static induction thyristor and a diode.

[0002]

2. Description of the Related Art FIG. 6 is a schematic sectional view of a generally known planar type power semiconductor device (a diode in FIG. 6). In FIG. 6, reference numeral 60 denotes a semiconductor element (pellet shape), and reference numeral 61 denotes a base layer made of a relatively low-concentration N-type semiconductor which is a semiconductor substrate (hereinafter, referred to as an N ⁻ -type base layer). On one main surface side (hereinafter, referred to as a lower surface side) of the N ⁻ -type base layer 61, a cathode region (hereinafter, referred to as N ⁺ ) made of a relatively high-concentration N-type semiconductor is provided.
(Referred to as a mold cathode layer) 62 is formed.

An anode region (hereinafter, referred to as a P-type anode layer) 63 made of a P-type semiconductor is formed on a part of the other main surface side (hereinafter, referred to as an upper surface side) of the N ⁻ -type base layer 61. Is done. A cathode electrode 64 is provided on the lower surface of the N ⁺ -type cathode layer 62, and an anode electrode 65 is provided at the center of the upper surface of the anode layer 63. Symbol 66
Shows a silicon oxide film (or silicon nitride film) provided so as to cover the end of the upper surface of the P-type anode layer 63 and the upper surface of the N ⁻ -type base layer 61.

In the semiconductor device 60 shown in FIG. 6, a junction surface between the N ⁻ type base layer 61 and the P type anode layer 63, that is, a junction between a P type semiconductor and an N type semiconductor (hereinafter, referred to as a junction).
(PN junction) surface is curved, and the curved PN junction surface
The electric field intensity in the vicinity (hereinafter referred to as a curved joint surface) becomes relatively high. Therefore, the breakdown voltage of the semiconductor element 60 is determined by the electric field strength at the curved junction surface, and the breakdown voltage at the curved junction surface is, for example, a P-type semiconductor 71 and an N-type semiconductor 72 of the semiconductor element as shown in FIG. Is lower than the withstand voltage value in the PN junction (planar junction; planar junction) with "Solid State Electronic"
s "in Volume 9 (1966). M. Sze and G.S. Gib
reported by Bons. As a means for reducing the electric field strength near the curved junction surface, a depletion layer generated in the semiconductor element when a reverse bias voltage is applied,
Means for expanding in the element radial direction (mainly in the element end direction) inside the substrate are known.

FIG. 8A is a schematic view of a generally known high voltage type power semiconductor device (pellet; for example, 4500 V class or higher), and FIG.
2 is a partial cross-sectional view (the outer peripheral portion 80b of the semiconductor element 80). Note that the same components as those shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. 8A and 8B
In the figure, reference numeral 80 indicates a semiconductor element. Reference numeral 63a denotes an N ⁻ -type base layer 61 in a central portion (active region; active region of the device) 80a of the semiconductor device 80.
3 shows a portion of the P-type anode layer 63 provided on the upper surface side of the P-type anode layer 63 closest to the element end (hereinafter, referred to as the P-type anode layer outermost).

A field limiting ring (hereinafter referred to as a guard ring layer) made of a P-type semiconductor is provided on the upper surface side of the N ⁻ -type base layer 61 in the outer peripheral portion (termination region; element withstand voltage relaxation region) 80 b of the semiconductor device 80. 8 (in FIG. 8, eight) are provided at predetermined intervals. A depletion layer generated at the outer peripheral portion 80b of the semiconductor element 80 due to each of the guard ring layers 81 described above.
(A dotted line in FIG. 8B is an example of a region where a depletion layer is generated) is expanded in the element end direction, and the voltage applied to the outer peripheral portion 80b can be dispersed to each of the guard ring layers 81. Can be alleviated. The semiconductor element 80 shown in FIGS. 8A and 8B has a structure in which the distance between the guard ring layers 81 is gradually increased toward the end of the element (hereinafter, referred to as a successive amplification type).

Reference numeral 82 denotes a stopper layer made of an N-type semiconductor having a relatively high concentration (hereinafter referred to as an N ⁺ -type stopper layer). Outer peripheral portion 8 of the semiconductor element 80
The silicon oxide film 66 is provided on the upper surface of the upper surface side of the silicon oxide film 0b. In the silicon oxide film 66, the groove 83a and the N
^A notch 83 is formed in a portion where the ⁺ type stopper layer 82 is located.
b are respectively formed by etching or the like.

Each of the groove portions 83a has a field plate ring (hereinafter, referred to as a plate ring) 84, which is a kind of electrode, and the notch portion 83b has an equipotential ring (Eq.
ui Potential Rings) 85 are provided, and an anode electrode 65 is provided on the upper surface of the central portion 80a. The semiconductor elements 8 are formed by the respective plate rings 84.
Since the depletion layer 82 at 0 becomes easier to spread in the element end direction and the voltage is equally distributed to each of the plate rings 84, the electric field concentration at the PN junction can be reduced.

Further, in order to improve the reliability of the semiconductor element 80, a semi-insulating silicon nitride film 86 having low hygroscopicity and excellent blocking properties against alkali metals such as sodium is used as a passivation film. Reference numeral 31 denotes an upper surface side of an outer peripheral portion 80b of the semiconductor element 80, which is an end portion of the anode electrode 65 (hereinafter, referred to as an outermost portion of the anode electrode) 65a, a silicon oxide film 66, a plate ring 84, and a part of the equipotential ring 85. It is provided so as to cover.

By using the silicon nitride film 31 and the plate ring 84 together, the depletion layer in the semiconductor element 80 can be further expanded in the element end direction, and a voltage is applied to each of the plate rings 84. Since the sharing can be performed, the electric field concentration at the PN junction is further reduced, and the effect of the plate ring 84 can be more remarkably exhibited.

The silicon nitride film has conductivity by changing the bonding ratio between silicon and nitrogen at the time of film formation and slightly increasing the ratio of silicon. The guard ring layer 81, the plate ring 84, and the equipotential ring 85 each have a concentric ring shape centered on the center of the semiconductor element 80. Further, each of the above-mentioned plate rings 84 is connected to each of the plate rings 84 and the silicon substrate (N ⁻ type base layer 6).
1) is provided so as to sandwich the silicon oxide film 66 therebetween, and is formed to protrude (protrude) toward the element end side from the guard ring layer 81 corresponding to each plate ring 84. . Similarly to the plate ring 84, the outermost anode electrode 65a and the silicon substrate (N ⁻
It is provided so as to sandwich the silicon oxide film 66 between itself and the mold base layer 61), and is formed so as to protrude (protrude) toward the element end side from the outermost 63a of the P-type anode layer.

FIG. 9A is a schematic explanatory view for explaining the effect of each plate ring 84, and FIG. 9B
Shows a case where a silicon nitride film as a semi-insulating film is used. The arrows in FIGS. 9A and 9B show an example of the direction of movement of ionic impurities and electrons. 8A,
Components similar to those shown in B are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 9A, when a positive voltage is applied to the cathode electrode 64 and a negative voltage is applied to the plate ring 84, Na ^+, which is a positive charge in the silicon oxide film 66 near the plate ring 84, is attracted to the plate ring 84. At the same time, electrons in the N ⁻ -type base layer 61 near the silicon oxide film 66 whose Na ⁺ concentration has decreased are freely moved. That is, by isolating ionic impurities from the interface between the silicon substrate (N ⁻ type base layer 61) and the oxide film (silicon oxide film 66), a high-concentration region (see FIG. 9 is prevented from being formed, and the depletion layer is expanded at the time of reverse bias, so that the electric field concentration is effectively reduced.

On the other hand, in FIG. 9B, each plate ring 84 is connected by a silicon nitride film 86, and since the silicon nitride film 86 has the same effect as the plate ring 84, the silicon oxide film 66 near the plate ring 84 is formed. The Na ⁺ in the region is attracted to the plate ring 84 and the silicon nitride film 86, so that the enhanced layer 91 over a wide range is eliminated, the electric field concentration is reduced, and the reduction in breakdown voltage in the semiconductor element can be further suppressed.

In an oxide film formed on a semiconductor element, there are interface fixed charges and interface states in addition to ionic impurities (hereinafter, ionic impurities, interface fixed charges and interface states are referred to as surface states). Surface charge existing near the interface between the oxide film and the silicon substrate is 1 × 10 ¹¹
It becomes a positive charge of cm ^-2 or more. Therefore, for example, FIG.
As in the semiconductor element 100 shown in the surface charge distribution diagram of FIG. 1, the enhanced layer 100c is formed in a portion of the silicon substrate 100a close to the oxide film 100b, and electric field concentration occurs on the upper surface side of the silicon substrate 100a. It is known that the degree of expansion in the depletion layer 100d is affected and the breakdown voltage of the semiconductor element 10a is reduced. Reference numeral 100e in FIG. 10 indicates a diffusion layer made of a P-type semiconductor.

As described above, a generally known semiconductor device has Si / SiO ₂ / S in the axial direction of the device.
i ₃ N ₄ three-layer structure, or Si / SiO ₂ / Si ₃ N ₄ /
It consists of a four-layer structure of SiO ₂ , attracts a part of positive charges (ionic impurities) in the vicinity of the interface between the oxide film and the silicon substrate to a plate ring, etc., and reduces the electric field concentration generated on the upper surface side of the silicon substrate. The reduction in breakdown voltage of the semiconductor element is reduced.

FIGS. 11A (when a plate ring is not used), B (when a silicon oxide film is formed thinner than in FIG. 11A using a plate ring), and C (when a plate ring is used and compared with FIG. 11A). (The silicon oxide film is formed thicker) is a simulation diagram (schematic diagram) for explaining the electric field concentration point at the time of breakdown in the vicinity of the guard ring layer formed on the outer peripheral portion of the semiconductor element having various structures. is there. Note that thin lines in FIGS. 11A to 11C indicate isoelectric lines, and dotted lines indicate main electric field concentrated portions. Reference numerals 111 in FIGS. 11A to 11C denote a silicon substrate, and reference numeral 112 denotes a guard ring layer.

In the semiconductor device having the structure shown in FIG. 11A, an electric field concentration 114a occurs at an upper end of the guard ring layer 112 and a part of the silicon oxide film 113a.
It was confirmed that the breakdown voltage of the semiconductor element deteriorated. On the other hand, in the semiconductor device having the structure shown in FIG.
Compared with the semiconductor device shown in FIG.
Electric field concentration at the upper surface side end of reference numeral 2 (reference numeral 1 in FIG. 11A)
14a) is relaxed, but an electric field concentration 114b occurs at the end of the plate ring 115b, and the silicon oxide film 11
Since 3b is thin, it has been confirmed that the electric field concentration 114b also affects the inside of the silicon substrate 111, and that the breakdown voltage of the semiconductor element deteriorates to a considerable extent.

In the semiconductor device having the structure shown in FIG. 11C, since the silicon oxide film 113c is formed thicker than the semiconductor device shown in FIG. 11B, the electric field concentration 114c in the guard ring layer 112 is reduced. It occurs on the lower surface side of the guard ring layer 112 (lower surface side than the electric field concentration 114a). The electric field concentration 114d generated at the end of the plate ring 115c is
It was confirmed that it was possible to prevent the influence on the semiconductor device and to suppress the deterioration of the breakdown voltage of the semiconductor element.

[0020]

As shown in FIG. 8B, a guard ring layer formed on a generally known successive amplification type semiconductor element is formed by a guard ring formed near the element end. Compared with the interval of the layer 81, the element central portion 8
The space between the guard ring layers 81 formed near 0a is small. For example, as shown in FIG. 8B, the interval between each plate ring 84 corresponding to each guard ring layer 81 formed in the vicinity of the element end (reference numerals c and d in FIG. 8B).
As compared with, the interval between the plate rings 84 (including the outermost 65 of the anode electrode) corresponding to the respective guard ring layers formed near the center of the element becomes narrower (symbols A and B in FIG. 8B). I have.

In the successive amplification type semiconductor element as described above, the width (length in the element end direction) of each plate ring provided on the semiconductor element is uniform, and the voltage (4500 V or more) until breakdown is reached. Is applied, the silicon nitride film and the silicon oxide film cause dielectric breakdown in a portion where the interval between the plate rings is narrow, and a problem occurs in that discharge occurs. Such a destruction phenomenon becomes remarkable as approaching the central part of the element (particularly, the symbol a in FIG. 8B).

Generally, the breakdown voltage of a silicon oxide film is 2 to 10 × 10 ⁶ V / cm, and the breakdown voltage of a silicon nitride film obtained by changing the composition ratio in the silicon oxide film is 1 × 10 ⁶ V / cm. It is about ⁶ V / cm. Therefore, when the distance between the plate rings provided in the semiconductor element is 10 μm, a destruction phenomenon occurs when a potential difference of 1000 V occurs. Further, when a pinhole, a structural defect or the like exists in the silicon oxide film or the silicon nitride film,
A lower potential difference (a potential difference of 1000 V or less) causes a destruction phenomenon.

In the above-described successive amplification type semiconductor device,
When the interval between the guard ring layers is simply changed, a difference occurs in the voltage shared between the guard ring layers, and the breakdown voltage of the semiconductor element is deteriorated. Changing the position of one or more guard ring layers in each guard ring layer;
For example, when the anode electrode provided on the P-type anode layer is shortened so as not to have the same effect as the plate ring
(When the outermost part of the anode electrode does not protrude toward the element end than the outermost part of the P-type anode layer), or on the guard ring layer closest to the inner peripheral part of the element, there is no plate ring effect. When only the electrode portion is formed, destruction occurs in a transient state.

That is, when a reverse bias starts to be applied to the PN junction of the semiconductor device (a process of rising from 0 V to 4500 V or more), before the electric field spreads over the entire guard ring layer of the semiconductor device, the central portion of the device is turned on. Since the electric field concentrates on the plurality of guard ring layers near the portion, sufficient electric field relaxation is not performed, and the semiconductor element may be damaged.

The present invention has been made based on the above-mentioned problem, and has an improved structure on the upper surface side in the outer peripheral portion of a semiconductor device of the successive amplification type, thereby alleviating electric field concentration and preventing a decrease in withstand voltage to achieve a high withstand voltage. It is an object of the present invention to provide a semiconductor device which has been developed.

[0026]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is directed to a first invention in which a disk-shaped semiconductor substrate made of a relatively low-concentration N-type semiconductor is provided on one main surface side. A cathode region of a relatively high-concentration N-type semiconductor is formed, a cathode electrode is provided on the surface of the cathode region, and a plurality of anode regions of a P-type semiconductor are respectively provided at a central portion on the other main surface side of the semiconductor substrate. While forming at intervals of
A plurality of field limiting rings made of a P-type semiconductor are formed on the outer peripheral portion on the other main surface side of the semiconductor substrate so that the intervals between the respective field limiting rings are sequentially amplified. An oxide film having a predetermined thickness is provided on the main surface of the oxide film, and grooves are respectively formed in portions of the oxide film where the anode regions and the field limiting rings are located. The anode electrode, the anode electrode, and the field limiting ring are located at portions where the respective anode regions and the respective field limiting rings are located on the film surface.
In a semiconductor device configured by providing field plate rings at predetermined intervals, a radial direction of a plurality of field plate rings among the field plate rings, which are located on a central portion side of the semiconductor substrate, is used. The width is shorter than the width in the element radial direction of the field plate ring located on the end side of the semiconductor substrate.

According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect of the invention, wherein the field plate ring and a part of the oxide film are covered on the other main surface side in the outer peripheral portion of the semiconductor element.
A semi-insulating passivation film is provided.

According to a third aspect of the present invention, in the first or second aspect, each of the field limiting rings is such that any one of the following three relational expressions is satisfied in an interval between the field limiting rings. Each is formed.

A + (n-1) b ₁ , a + (n-1) b ₂ + (n
-1) ² c ₂ or a + (n-1,) b 3 + (n-1) 2 c 3 +
(n-1) ³ d ₃ (a; spacing between the anode region closest to the outer periphery of the semiconductor substrate and the field limiting ring closest to the center of the semiconductor substrate; b ₁ , b ₂ , b ₃ , c ₂ , c ₃ , d ₃ ; amplification pitch coefficient in the interval between each field limiting ring, n; number of field limiting rings counted from the central part of the semiconductor substrate) The fourth invention is the second invention, wherein the passivation film is used. Is made of a silicon-rich silicon nitride film.

According to a fifth aspect, the first, second, or third aspect is provided.
The invention is characterized in that the thickness of the oxide film is gradually reduced as approaching the end of the element.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. First, the electric field distribution in the outer peripheral portion of the semiconductor element (reference numeral 121 in FIG. 12A) of the successive amplification type (15 guard ring layers; reference numeral 122) as shown in FIG. 12A was examined by simulation. Then, in the semiconductor element 121, the vicinity of the outermost 123 of the P-type anode layer (reference numeral e in FIG.
2 and the vicinity of the guard ring layer 122 closest to the end of the element (reference numeral in FIG. 12A).
In FIG. 12B,
C and D are shown in a partially enlarged view. Note that reference numerals 124b, 124c, and 124d indicated by dotted lines in FIGS.
Indicates an electric field concentration point.

From the results shown in FIGS. 12B, 12C, 12D, the guard ring layer 122a closest to the outermost 123 of the P-type anode layer (hereinafter referred to as the innermost guard ring layer) 122a
In FIG. 12, the electric field concentration 124b is generated on the lower surface side of the innermost guard ring layer 122a, but as the element edge portion is approached, the electric field concentration increases on the upper surface side (FIG. 12C, FIG.
It was confirmed that the movement to the symbols 124c and 124d) in D was made.

Therefore, in the guard ring layer formed on the outer peripheral portion of the successive amplification type semiconductor element, it is important to reduce the electric field concentration on the element end side as compared with the element center side of the guard ring layer. Was confirmed. Therefore, first, as shown in FIG. 1 (details will be described later),
A semiconductor device in which the structure of a plate ring provided near the center of the device was improved was studied.

FIG. 1 is a schematic diagram showing the configuration of a semiconductor device (reference numeral 10 in FIG. 1) according to the first embodiment of the present invention. The same components as those shown in FIG. 8B are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 1, reference numeral 11 denotes a plate ring whose width in the element radial direction is smaller than that of the plate ring 84. The plate ring 11 includes a plurality of plate rings 11 formed in the vicinity of the P-type anode layer outermost 63a. 1 (two in FIG. 1) are provided for the grooves 83a on the upper surface side of the guard ring layer 81a.

The width of the plate ring 11 in the element radial direction is equal to or smaller than the width of the guard ring layer 81a located immediately below the plate ring 11 in the element radial direction. On the other hand, a plate ring 84 provided on the element end side of the plate ring 11 is provided.
Is wider than the sum of the widths of the guard ring layer 81 located immediately below the plate ring 84 and the electric field concentration region in the element radial direction.

By arranging the semiconductor element as shown in FIG. 1, the electric field concentration in the outer peripheral portion of the semiconductor element is reduced, particularly the electric field concentration in the guard ring layer formed near the outermost periphery of the P-type anode layer. In addition to this, it is possible to prevent the silicon nitride film and the silicon oxide film formed on the semiconductor element from being broken.

Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. When the electric field concentration near the guard ring layer formed near the outermost portion of the P-type anode layer is relatively weak, as shown in FIG.
A silicon oxide film is simply provided on the upper surface side of a plurality (two in FIG. 2) of guard ring layers 81a formed near 3a. That is, the groove 83a is not formed in the portion of the silicon oxide film 66 where the guard ring layer 81a is located, and the semiconductor element 20 is formed without using the plate ring 84.

By configuring the semiconductor device as shown in FIG. 2, when the electric field concentration near the guard ring layer formed near the outermost portion of the P-type anode layer is relatively weak, the semiconductor device shown in FIG. As compared with the case, the reduction in the breakdown voltage of the semiconductor element can be easily suppressed.

Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 3, the outermost P-type anode layer 6
3, the outermost anode electrode 65a of the anode electrode 65 formed on the upper surface,
4. A semiconductor element 30 is formed by providing a passivation film 86 so as to cover a part of the equipotential ring 85.

By arranging the semiconductor element as shown in FIG. 3, the electric field concentration at the outer peripheral portion of the semiconductor element can be reduced, particularly the electric field concentration at the guard ring layer formed near the outermost periphery of the P-type anode layer. And the voltage applied to the anode electrode can be shared by each plate ring. In addition, destruction of the silicon nitride film and the silicon oxide film formed on the semiconductor element can be further prevented.

The semiconductor devices 10 and 2 shown in FIGS.
Each of the outer peripheral portion 80b of 0,30, based on the relation l _alpha below, each of the guard ring layer 81 sequentially to amplify expression, respectively (including a guard ring layer 81a) is formed. Incidentally, a in equation l _alpha, below, shows the distance between the P-type anode layer outermost and innermost guard ring layer. Further, b ₁ is amplified pitch coefficient at a distance of each of the guard ring layers, n represents the position of the desired guard ring layer counted from the central portion side of each of the guard ring layer which is formed on the outer peripheral portion of the semiconductor element (e.g., In the case of the innermost guard ring layer, n = 1) is indicated.

L _α = a + (n−1) b ₁ (1) Further, the semiconductor elements 10, 20 and 30 are, for example, 2
In the case where each of the guard ring layers 81 (including the guard ring layer 81a) is formed in a successive amplification manner based on the following relational expressions l _β and l _γ having the following terms, ~ It was confirmed that the effects shown in the third embodiment were obtained. FIG. 4 is a curve diagram showing the relational expressions l _α , l _β , and l _γ having the above first, second and third order terms. Note that b ₂ , b ₃ , c ₂ , c ₃ , and d ₃ in the relational expressions l _β and l _γ indicate the amplification pitch coefficients at the distance between the respective guard ring layers.

[0043] _{l β = a + (n-} 1) b 2 + (n-1) 2 c 2 ...... (2) l γ = a + (n-1) b 3 + (n-1) 2 c 3 + (N−1) ³ d ₃ ... (3) By providing a uniform thickness silicon oxide film on the upper surface side of the outer peripheral portion of the semiconductor device, each plate ring end provided on the outer peripheral portion of the semiconductor device is provided. It is possible to prevent the electric field concentration generated in the portion from affecting the inside of the substrate. However, as shown in FIG. 11C, the effect of reducing the electric field concentration (reference numeral 114c in FIG. 11C) generated inside the substrate (guard ring layer) is reduced. Then, FIG.
In consideration of the simulation result shown in D, a semiconductor device as shown in FIG. 5 (described in detail later) was studied.

FIG. 5 is a schematic sectional view of a semiconductor device (reference numeral 50 in FIG. 5) according to the fifth embodiment of the present invention. The same components as those shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 5, reference numeral 51 denotes an oxide film formed on the upper surface side of the outer peripheral portion 80b of the semiconductor element 50 so as to become thinner toward the element end. The oxide film 51 is first formed on the outer peripheral portion 80 b of the N ⁻ type base layer 61.
A thermal oxide film having a uniform thickness is formed on the upper surface of the device, and a CVD oxide film having a uniform thickness is formed on the upper surface of the thermal oxide film. (Steps inside)
It is formed by performing etching a plurality of times so as to reduce the thickness.

By configuring the semiconductor device as shown in FIG. 5, the concentration of the electric field generated inside the substrate can be reduced, and the concentration of the electric field generated at the end of the plate ring can be reduced. High breakdown voltage of the semiconductor element can be achieved.

[0046]

As described above, according to the present invention, the electric field in each of the guard ring layers formed on the outer peripheral portion of the semiconductor element is effectively reduced, and the electric field is evenly applied to each of the guard ring layers. Is shared. A short circuit due to dielectric breakdown of the silicon nitride film and the silicon oxide film can be prevented between the respective plate rings provided in the respective guard ring layers.

Further, by using a resistive passivation film on the outer periphery of the semiconductor element, ionic impurities in the oxide film can be more attracted to the plate ring, and enhanced generated in the semiconductor element can be obtained. The effect of suppressing the layers also acts on the plate rings to which no voltage is directly applied, and the shared voltage in each of the plate rings becomes weaker as approaching the element end, so that the depletion layer can be more effectively applied to the element. It becomes possible to expand in the end direction.

Further, the thickness of the oxide film provided on the upper surface side of the outer peripheral portion of the semiconductor element is gradually reduced as approaching the end of the element, so that the P-type anode layer at the outer peripheral portion of the semiconductor element is formed. Since the thickness of the oxide film near the outermost part is large, it is possible to prevent the relatively strong electric field concentration generated at the end of the plate ring near the outermost part of the P-type anode layer from affecting the inside of the substrate, and Relatively weak electric field concentration generated inside (on the lower surface side of each guard ring layer) can be suppressed.

Further, since the thickness of the oxide film near the element end in the outer peripheral part of the semiconductor element is small, it is possible to prevent the relatively weak electric field concentration generated at the end of the plate ring from affecting the inside of the substrate. Can be inside the substrate as well
The relatively strong electric field concentration generated on the upper surface side of each guard ring layer can be sufficiently reduced.

Therefore, it is possible to increase the breakdown voltage of the semiconductor element.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device according to a first embodiment of the present invention.

FIG. 2 shows a semiconductor device according to a second embodiment of the present invention.

FIG. 3 shows a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a curve diagram showing relational expressions l _α , l _β , and l _γ .

FIG. 5 shows a semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 shows a generally known planar type power semiconductor device.

FIG. 7 shows a P-type semiconductor and an N-type semiconductor which are planarly bonded.

FIG. 8 shows a generally known successive amplification type semiconductor element.

FIG. 9 is an explanatory diagram of the operation of the plate ring.

FIG. 10 is a surface charge distribution diagram of a semiconductor element.

FIG. 11 is an electric field concentration distribution diagram near a guard ring layer in various semiconductor elements.

FIG. 12 is an electric field concentration distribution diagram at an outer peripheral portion of a semiconductor element.

[Explanation of symbols]

10, 20, 30, 50 ... semiconductor device 11,84 ... plate ring 61 ... N ^- type base layer 62 ... N ⁺ -type cathode layer 63 ... P-type anode layer 63a ... P-type anode layer outermost 64 ... cathode electrode 65 ... Anode electrode 65a ... Anode electrode outermost 66,51 ... Silicon oxide film 80a ... Central portion 80b ... Outer peripheral portion 81,81a ... Guard ring layer 82 ... Stopper layer 83a ... Groove portion 83b ... Notch portion 85 ... Equipotential ring 86 ... Silicon Nitride film

Claims (5)

[Claims] A cathode region of a relatively high-concentration N-type semiconductor is formed on one principal surface side of a disc-shaped semiconductor substrate made of a relatively low-concentration N-type semiconductor, and a cathode electrode is formed on the surface of the cathode region. An anode region of a P-type semiconductor is formed in a central portion on the other main surface side of the semiconductor substrate, and a field limiting member made of a P-type semiconductor is formed on an outer peripheral portion on the other main surface side of the semiconductor substrate. A plurality of rings are formed so that the interval between the respective field limiting rings is sequentially amplified, and an oxide film having a predetermined thickness is provided on the outer peripheral surface on the other main surface side of the semiconductor substrate, and the oxide film is provided. Forming a groove in a portion where each of the field limiting rings is located; and forming each field on the surface of the oxide film including the anode region and each of the grooves. A semiconductor element configured by providing an anode electrode and a field plate ring at predetermined intervals so as to protrude toward an end of the semiconductor substrate with respect to a portion where a limiting ring is located; In each of the field plate rings, the width in the element radial direction of the plurality of field plate rings located on the center side of the semiconductor substrate is the width in the element radial direction of the field plate ring located on the end side of the semiconductor substrate. A semiconductor device characterized in that each of them is shortened as compared with. 2. A semi-insulating passivation film is provided on the other main surface side of the outer peripheral portion of the semiconductor device according to claim 1 so as to cover each of said field plate rings and a part of the oxide film. The semiconductor device according to claim 1, wherein: 3. The apparatus according to claim 1, wherein each of the field limiting rings is formed such that one of the following three relational expressions is satisfied in an interval between the field limiting rings. Or the semiconductor element according to 2. a + (n-1) b 1, a + (n-1) b 2 + (n-1) 2 c 2 or a + (n-1), b 3 + (n-1) 2 c 3 + (n-1 ) ³ d ₃ (a; distance between the outermost anode region and the field limiting ring closest to the center of the semiconductor substrate, b ₁ ,
b ₂ , b ₃ , c ₂ , c ₃ , d ₃ ; amplification pitch coefficient in the interval between each field limiting ring, n; position of the desired field limiting ring counted from the center of the semiconductor substrate) 4. The semiconductor device according to claim 2, wherein said passivation film is made of a silicon-rich silicon nitride film. 5. The semiconductor device according to claim 1, wherein the thickness of the oxide film is gradually reduced as approaching an end of the device.