JPH0465552B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a vertical insulated gate field effect transistor (hereinafter referred to as MOSFET), and more particularly to a vertical MOSFET with low power loss.

Prior Art As shown in FIGS. 1 and 2, a conventional vertical n-channel MOSFET is an n ^- type (first conductivity type) MOSFET provided with a portion 2a exposed on the surface of a silicon semiconductor substrate 1. High resistance drain region 2
and an n ⁺ type low-resistance drain region 3 provided below the high-resistance drain region 2, and is configured such that a drain current flows in the thickness direction of the substrate 1. 4 is a p-type (second conductivity type) base region, that is, a bulk region, and a high-resistance drain region 2
It is formed so as to annularly surround the surface exposed portion 2a of. Note that a channel region 4a is provided in an annular shape by this surface exposed portion. Reference numeral 5 denotes an n ⁺ type (first conductivity type) source region, which is formed so as to be surrounded by the base region 4 . As is clear from FIG. 2, this source region 5 is formed so as to annularly surround the exposed surface portion 2a of the high-resistance drain region 2, and has a portion exposed to the surface of the substrate 1. A gate insulating film 6 is made of SiO ₂ and is provided on the channel region 4a. 7 is a gate electrode provided on the gate insulating film 6, 8 is a source electrode provided on the source region 5, and 8a is a source connection electrode provided on the base region 4 integrally with the source electrode 8. , 9 is a drain electrode provided in the low resistance drain region 3, and 10 is a protective insulating film.

When a negative voltage is applied to the source electrode 8 and a positive voltage is applied to the gate electrode 7 and drain electrode 9 of this MOSFET, the channel region 4a is
It becomes a type inversion layer, and the source region 5 and channel region 4
A path through which majority carriers (electrons) flow is formed by the high-resistance drain region 2 and the low-resistance drain region 3, and a drain current flows.

However, in order to obtain a high-voltage vertical MOSFET, the impurity concentration of the high-resistance drain region 2 is designed to be lower than that of the base region 4, and the impurity concentration between the base region 4 and the high-resistance drain region 4 is designed to be lower than that of the base region 4. pn
The width W of the drain region 4 must be designed to be large so as to allow the depletion layer to spread at the junction.
Therefore, when a large drain current flows, the voltage drop in the high resistance drain region 2 becomes large (in a 1000V class element, the proportion of the total voltage drop is
70-90%), and the power loss increased.

In order to solve this kind of problem, the applicant has manufactured a vertical MOSFET having the structure shown in FIG. Next, this MOSFET will be explained. However, in Fig. 3, the items indicated by numerals 1 to 10 are
Since it is the same as that shown by the same reference numeral in the figure, the explanation thereof will be omitted. The MOSFET shown in FIG. 3 has a p-type (second conductivity type) carrier injection region 11 connected to a drain electrode 9. The MOSFET shown in FIG. This carrier injection region 11 is provided at a position corresponding to the surface exposed portion 2a of the high resistance drain region 2 and the lower part of the channel region 4a in order to inject fractional carriers (holes) into the path of the drain current. To illustrate the average impurity concentration of each region, the high resistance drain region 2 has an impurity concentration of 2×10 ¹⁴ /cm ³ , and the low resistance drain region 3 has an impurity concentration of 1×
10 ¹⁹ /cm ³ , base region 4 2×10 ¹⁷ /cm ³ , source region 1×10 ¹⁹ /cm ³ , carrier injection region 11 1
It has an average impurity concentration of ×10 ¹⁷ /cm ³ .

This MOSFET in Figure 3 is replaced with the MOSFET in Figure 1.
When a voltage is applied in the same manner as above, the channel region 4a becomes an n-type inversion layer, and a drain current flows. In this case, in the small current region, a voltage higher than the rising voltage (approximately 0.55 V) at the pn junction between the carrier injection region 11 and the drain regions 2 and 3 is not applied, so the current flows through the path shown by the dotted line 12. flows. On the other hand, when the drain current increases, the carrier injection region 11
There is a part where the voltage drop due to the current flowing near the boundary between the and drain regions 2 and 3 exceeds the forward rising voltage of the pn junction, and from this point, fractional carriers (holes) flow into the high resistance drain region 2 as indicated by the dotted line 13. Injected as shown. As a result, the high-resistance drain region 2 undergoes conductivity modulation, resulting in a state equivalent to a decrease in resistivity, limiting the increase in voltage drop between the source and drain, and reducing power loss in the large current region. Become. Note that holes injected from the carrier injection region 11 at the time of switch-on recombine with electrons flowing into the drain region 2 from the channel region 4a.

By the way, p-type carrier injection region 11 and n ^-
type drain region 2, p-type base region 4 and n ⁺
If the pnpn four-layer structure consisting of the type source region 5 operates as a thyristor, the function of a MOSFET cannot be obtained. Therefore, this MOSFET is configured not to operate as a thyristor. The conditions for not operating as a thyristor are that the carrier injection region 11, the high resistance drain region ₂ , and the base region are the emitter, the base, and the collector, respectively. 4. When the common base current amplification factor of an npn transistor with drain region 2 as emitter, base, and collector is α ₂ ,
α ₁ +α ₂ <1.

In order to satisfy this condition, specifically, the width W of the high-resistance drain region 2 is set to about 100 μm, and the hole diffusion length L in the drain region 2 is set to about 80 μm, so that L≦W. Further, the impurity concentration of the p-type carrier injection region 11 is set to 1×
α ₁ is made small by making it as low as 10 ¹⁷ /cm ³ . Also, the average impurity concentration of the source region 5 (1×
10 ¹⁹ /cm ³ ) and the average impurity concentration of base region 4 (2
×10 ¹⁷ /cm ³ ) is made smaller by a factor of ₁₀₀ or less.

However, there is a need for a vertical MOSFET that can more reliably prevent thyristor operation.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a vertical field effect transistor that can meet the above requirements.

Structure of the Invention To achieve the above object, the present invention will be described with reference to the reference numerals in the drawings showing the embodiments. The high-resistance drain region 2 has a portion exposed on the back surface of the semiconductor substrate and is disposed adjacent to the high-resistance drain region 2 .
a first conductivity type low-resistance drain region 3 having an impurity concentration higher than that of the first conductivity type, and a channel portion 4a provided adjacent to the high-resistance drain region 2 and exposed in an annular manner on the surface; A high-resistance base region 4 having a second conductivity type opposite to the first conductivity type, and a portion disposed adjacent to the high-resistance drain region 2 and the high-resistance base region 4 and exposed to the surface. a second conductivity type low resistance base region 4b formed outside the high resistance base region 4 and having a higher impurity concentration than the high resistance base region 4; and a portion exposed to the surface. and a first conductivity type source region 5 surrounded by the high resistance base region 4 and the low resistance base region 4b except for this exposed portion.
and is exposed on the back surface so as to be surrounded by the low-resistance drain region 3, is adjacent to the high-resistance drain region 2, and is formed so as to inject minority carriers into the high-resistance drain region 2. a second conductivity type carrier injection region 11; a gate insulating film 6 covering at least the channel portion 4a of the high-resistance base region 4;
A gate electrode 7 provided so as to face the channel portion 4a, a source electrode 8 provided in the source region 5, and a source region 5 and the low resistance base region 4b connected to the channel portion 4a. a base-source connection electrode 8a for connection at a position away from the base, and a drain electrode 9 provided at a portion exposed to the back surface of the low resistance drain region 3 and the carrier injection region 11; The carrier injection region 11 includes a surface exposed portion of the high resistance drain region 2 surrounded by the high resistance base region 4 and the channel portion 4a.
This relates to a vertical insulated gate field effect transistor characterized in that it is arranged so as to face the low resistance base region 4b but not to face the low resistance base region 4b.

Effects of the Invention In the above invention, by providing the low resistance base region 4b, the current amplification factor α ₂ of the transistor composed of the source region 5, the base regions 4, 4b, and the high resistance drain region 2 is reduced. , it is possible to reliably prevent thyristor operation that may occur due to the provision of the carrier injection region 11. Note that if the impurity concentration of the entire base region 4 in FIG. 3 is increased to lower the current amplification factor, it becomes impossible to form a good channel, but in the present invention, since the channel portion 4a is kept in a high resistance state, Such a problem does not occur. Further, in the present invention, although the carrier injection region 11 faces the exposed surface portion of the high-resistance drain region 2 and the channel portion 4a,
Since it is arranged so as not to face the low-resistance base region 4b, a transistor effect based on the carrier injection region 11, the high-resistance drain region 2, and the base regions 4, 4b is less likely to occur.

Embodiment Next, a vertical MOSFET according to an embodiment of the present invention will be described with reference to FIG. However, in FIG. 4, parts common to those in FIGS. 1 to 3 are designated by the same reference numerals and their explanations will be omitted. In this embodiment, the base region is composed of a high resistance base region 4 having an average impurity concentration of 1×10 ¹⁶ /cm ³ and a low resistance base region 4b having an average impurity concentration of 1×10 ¹⁸ /cm ³ . , a source connection electrode 8a is provided in the low resistance base region 4b. The rest of the parts are in the 3rd part.
It has the same configuration as the figure. With this configuration, α ₂ becomes small and thyristor operation is reliably prevented. Furthermore, it becomes possible to obtain a channel with a low gate voltage.

Modifications The present invention is not limited to the embodiments described above, but modifications are possible.

(A) When it is desired to significantly shorten the hole diffusion length L in the drain region 2, a lifetime killer such as Pt or Au may be doped into the drain region 2.

(B) Carrier injection layer 11 is connected to high resistance drain region 2
It may be formed deeper so that it protrudes into the inside. Conversely, it may be formed shallower than the low resistance drain region 3.

(C) Although the source connection electrode 8a is formed integrally with the source electrode 8, they may be formed separately and connected by an external circuit.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional vertical MOSFET.
Fig. 2 is a plan view showing a part of the surface of the FET substrate of Fig. 1, Fig. 3 is a sectional view showing another conventional MOSFET, and Fig. 4 is a sectional view showing a MOSFET according to an embodiment of the present invention. It is. 1... Semiconductor substrate, 2... High resistance drain region, 3
...Low resistance drain region, 4...Base region, 4a...
Channel region, 5... Source region, 6... Gate insulating film, 7... Gate electrode, 8... Source electrode, 8a... Source connection electrode, 9... Drain electrode, 11... Carrier injection region.

Claims (1)

[Scope of Claims] 1. A high resistance drain region 2 of a first conductivity type having a portion exposed on the front surface of the semiconductor substrate, and having a portion exposed on the back surface of the semiconductor substrate and adjacent to the high resistance drain region 2. a first conductivity type low resistance drain region 3 which is arranged and has a higher impurity concentration than the high resistance drain region 2;
and a high-resistance base that is provided adjacent to the high-resistance drain region 2, has a channel portion 4a exposed in an annular manner on the surface, and has a second conductivity type opposite to the first conductivity type. a region 4 that is disposed adjacent to the high-resistance drain region 2 and the high-resistance base region 4 and that is formed outside the high-resistance base region 4 and has a portion exposed to the surface; a second conductivity type low resistance base region 4b having an impurity concentration higher than that of the high resistance base region 4b, and a second conductivity type low resistance base region 4b having a portion exposed on the surface and excluding the exposed portion, the high resistance base region 4 and the low resistance base The first area surrounded by the area 4b
a conductive type source region 5; and a region exposed on the back surface so as to be surrounded by the low-resistance drain region 3, adjacent to the high-resistance drain region 2, and adjacent to the high-resistance drain region 2;
a second formed to inject minority carriers into
a carrier injection region 11 of a conductivity type; a gate insulating film 6 covering at least the channel portion 4a of the high-resistance base region 4; Gate electrode 7
and a source electrode 8 provided in the source region 5
and the source region 5 and the low resistance base region 4b.
a base-source connection electrode 8a for connecting the two at a position away from the channel portion 4a; and a drain electrode 9 provided on the portions of the low-resistance drain region 3 and the carrier injection region 11 exposed on the back surface. and, the carrier injection region 11 faces the exposed surface portion of the high resistance drain region 2 surrounded by the high resistance base region 4 and the channel portion 4a, but is opposite to the channel portion 4a. A vertical insulated gate field effect transistor, characterized in that it is arranged so as not to face 4b.