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ITMI930595A1 - Dispositivo a circuito integrato a semiconduttore con un convertitore riduttore di tensione interno - Google Patents

Dispositivo a circuito integrato a semiconduttore con un convertitore riduttore di tensione interno

Info

Publication number
ITMI930595A1
ITMI930595A1 IT93MI000595A ITMI930595A ITMI930595A1 IT MI930595 A1 ITMI930595 A1 IT MI930595A1 IT 93MI000595 A IT93MI000595 A IT 93MI000595A IT MI930595 A ITMI930595 A IT MI930595A IT MI930595 A1 ITMI930595 A1 IT MI930595A1
Authority
IT
Italy
Prior art keywords
semiconductor integrated
integrated circuit
external
circuit device
aging mode
Prior art date
Application number
IT93MI000595A
Other languages
English (en)
Inventor
Shigeru Mori
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI930595A0 publication Critical patent/ITMI930595A0/it
Publication of ITMI930595A1 publication Critical patent/ITMI930595A1/it
Application granted granted Critical
Publication of IT1272161B publication Critical patent/IT1272161B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/06—Acceleration testing

Landscapes

  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Un dispositivo a circuito integrato a semiconduttore include un circuito di controllo della modalità di invecchiamento o aging (1), che rivela i tempi di commutazione di una tensione di alimentazione esterna (Vcc esterna) con un'ampiezza predeterminata e genera un segnale (BE) di abilitazione della modalità aging, e un circuito di riduzione della tensione interna (2) che trasmette una tensione, che cambia in accordo con il cambio di una tensione di alimentazione esterna (Vcc esterna), su una linea di alimentazione interna (20) in risposta al segnale (BE) di abilitazione della modalità aging. Il dispositivo a circuito integrato a semiconduttore entra in una modalità aging solo quando la tensione di alimentazione esterna oscilla predeterminate volte con un'ampiezza non inferiore all'ampiezza predeterminata. Il dispositivo a circuito integrato a semiconduttore non entra necessariamente nella modalità aging per una prova aging e in modo semplicistico e sicuro entra nella modalità aging senza utilizzare una speciale relazione di temporizzazione dei segnali esterni di controllo.
ITMI930595A 1992-05-13 1993-03-26 Dispositivo a circuito integrato a semiconduttore con un convertitore riduttore di tensione interno IT1272161B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4120455A JPH05314769A (ja) 1992-05-13 1992-05-13 半導体集積回路装置

Publications (3)

Publication Number Publication Date
ITMI930595A0 ITMI930595A0 (it) 1993-03-26
ITMI930595A1 true ITMI930595A1 (it) 1994-09-26
IT1272161B IT1272161B (it) 1997-06-11

Family

ID=14786607

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI930595A IT1272161B (it) 1992-05-13 1993-03-26 Dispositivo a circuito integrato a semiconduttore con un convertitore riduttore di tensione interno

Country Status (5)

Country Link
US (1) US5451896A (it)
JP (1) JPH05314769A (it)
KR (1) KR960009400B1 (it)
DE (1) DE4244555C2 (it)
IT (1) IT1272161B (it)

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KR0165386B1 (ko) * 1995-04-24 1999-02-01 김광호 반도체장치의 내부 승압회로
US6329139B1 (en) 1995-04-25 2001-12-11 Discovery Partners International Automated sorting system for matrices with memory
US6416714B1 (en) 1995-04-25 2002-07-09 Discovery Partners International, Inc. Remotely programmable matrices with memories
US6331273B1 (en) 1995-04-25 2001-12-18 Discovery Partners International Remotely programmable matrices with memories
US5751629A (en) 1995-04-25 1998-05-12 Irori Remotely programmable matrices with memories
US6017496A (en) 1995-06-07 2000-01-25 Irori Matrices with memories and uses thereof
US5874214A (en) 1995-04-25 1999-02-23 Irori Remotely programmable matrices with memories
US5719524A (en) * 1995-10-11 1998-02-17 Telcom Semiconductor, Inc. Circuit having an input terminal for controlling two functions
KR0167261B1 (ko) * 1995-10-19 1999-04-15 문정환 전원공급 제어회로
JP2885187B2 (ja) * 1996-05-17 1999-04-19 日本電気株式会社 半導体記憶装置
US6198339B1 (en) * 1996-09-17 2001-03-06 International Business Machines Corporation CVF current reference with standby mode
KR100197998B1 (ko) * 1996-10-22 1999-06-15 김영환 반도체 장치의 저소비 전력 입력 버퍼
JP3963990B2 (ja) * 1997-01-07 2007-08-22 株式会社ルネサステクノロジ 内部電源電圧発生回路
JP3022815B2 (ja) * 1997-07-24 2000-03-21 日本電気アイシーマイコンシステム株式会社 中間電位生成回路
US6023176A (en) * 1998-03-27 2000-02-08 Cypress Semiconductor Corp. Input buffer
US6515934B2 (en) 1999-07-26 2003-02-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including internal potential generating circuit allowing tuning in short period of time and reduction of chip area
JP2001035199A (ja) * 1999-07-26 2001-02-09 Mitsubishi Electric Corp 半導体装置
JP2003022697A (ja) 2001-07-06 2003-01-24 Mitsubishi Electric Corp 半導体集積回路装置
JP3927788B2 (ja) * 2001-11-01 2007-06-13 株式会社ルネサステクノロジ 半導体装置
US7075284B2 (en) * 2002-07-08 2006-07-11 Kabushiki Kaisha Toshiba Time limit function utilization
EP1573889A1 (en) * 2002-12-10 2005-09-14 Koninklijke Philips Electronics N.V. Integrated half-bridge power circuit
JP4287678B2 (ja) 2003-03-14 2009-07-01 Ｏｋｉセミコンダクタ株式会社 内部電源回路
US20070069809A1 (en) * 2005-09-29 2007-03-29 Hynix Semiconductor Inc. Internal voltage generator
NL1032063C2 (nl) * 2006-06-27 2008-01-02 Maasland Nv Combinatie van een melkbeker en een flexibele melkslang, koppelstuk, alsmede werkwijze voor het bewaken van integriteit van flexibele melkslang.
KR100784908B1 (ko) 2006-08-11 2007-12-11 주식회사 하이닉스반도체 전압 조절 장치
US7793119B2 (en) * 2006-12-21 2010-09-07 Texas Instruments Incorporated Adaptive voltage scaling with age compensation
KR100863015B1 (ko) * 2007-05-11 2008-10-13 주식회사 하이닉스반도체 전압 안정화 회로 및 이를 이용한 반도체 메모리 장치
US8446187B1 (en) * 2007-11-16 2013-05-21 National Semiconductor Corporation Apparatus and method for power-on reset circuit with current comparison
US8736314B2 (en) * 2011-03-22 2014-05-27 Wisconsin Alumni Research Foundation Leakage power management using programmable power gating transistors and on-chip aging and temperature tracking circuit
US10371745B2 (en) * 2014-01-23 2019-08-06 Micron Technology, Inc. Overheat protection circuit and method in an accelerated aging test of an integrated circuit
WO2020078265A1 (en) * 2018-10-16 2020-04-23 Changxin Memory Technologies, Inc. Data channel aging circuit, memory and aging method
CN109087684B (zh) * 2018-10-16 2023-09-12 长鑫存储技术有限公司 数据通道老化电路、存储器及其老化方法

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JP2945508B2 (ja) * 1991-06-20 1999-09-06 三菱電機株式会社 半導体装置
KR930008886B1 (ko) * 1991-08-19 1993-09-16 삼성전자 주식회사 전기적으로 프로그램 할 수 있는 내부전원 발생회로

Also Published As

Publication number Publication date
JPH05314769A (ja) 1993-11-26
ITMI930595A0 (it) 1993-03-26
US5451896A (en) 1995-09-19
DE4244555C2 (de) 1997-05-28
KR940006342A (ko) 1994-03-23
IT1272161B (it) 1997-06-11
DE4244555A1 (de) 1993-11-18
KR960009400B1 (en) 1996-07-18

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970326