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HK1006884A1 - High integration dram controller - Google Patents

High integration dram controller

Info

Publication number
HK1006884A1
HK1006884A1 HK98105915A HK98105915A HK1006884A1 HK 1006884 A1 HK1006884 A1 HK 1006884A1 HK 98105915 A HK98105915 A HK 98105915A HK 98105915 A HK98105915 A HK 98105915A HK 1006884 A1 HK1006884 A1 HK 1006884A1
Authority
HK
Hong Kong
Prior art keywords
high integration
dram controller
integration dram
controller
integration
Prior art date
Application number
HK98105915A
Other languages
English (en)
Inventor
Eugene P Matter
Steven M Farrer
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1006884A1 publication Critical patent/HK1006884A1/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • G06F12/0653Configuration or reconfiguration with centralised address assignment
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Memory System (AREA)
  • Dram (AREA)
HK98105915A 1992-09-23 1998-06-22 High integration dram controller HK1006884A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/949,708 US5307320A (en) 1992-09-23 1992-09-23 High integration DRAM controller

Publications (1)

Publication Number Publication Date
HK1006884A1 true HK1006884A1 (en) 1999-03-19

Family

ID=25489456

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98105915A HK1006884A1 (en) 1992-09-23 1998-06-22 High integration dram controller

Country Status (4)

Country Link
US (1) US5307320A (xx)
JP (1) JP3590413B2 (xx)
GB (1) GB2271003B (xx)
HK (1) HK1006884A1 (xx)

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530944A (en) * 1991-02-27 1996-06-25 Vlsi Technology, Inc. Intelligent programmable dram interface timing controller
JPH06111010A (ja) * 1992-09-29 1994-04-22 Ricoh Co Ltd Dram及びコントローラ
TW390446U (en) * 1992-10-01 2000-05-11 Hudson Soft Co Ltd Information processing system
TW276312B (xx) * 1992-10-20 1996-05-21 Cirrlis Logic Inc
US5561814A (en) * 1993-12-22 1996-10-01 Intel Corporation Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges
US5721860A (en) * 1994-05-24 1998-02-24 Intel Corporation Memory controller for independently supporting synchronous and asynchronous DRAM memories
US5604880A (en) * 1994-08-11 1997-02-18 Intel Corporation Computer system with a memory identification scheme
AU703750B2 (en) * 1994-10-14 1999-04-01 Compaq Computer Corporation Easily programmable memory controller which can access different speed memory devices on different cycles
US5694585A (en) * 1994-11-10 1997-12-02 International Business Machines Corporation Programmable memory controller and data terminal equipment
US20030009616A1 (en) * 1994-11-30 2003-01-09 Brian K. Langendorf Method and apparatus for integrating and determining whether a memory subsystem is installed with standard page mode memory or an extended data out memory
DE4445801C2 (de) * 1994-12-21 2003-12-04 Siemens Ag Schaltungsanordnung zur Ansteuerung von dynamischen Speichern durch einen Mikroprozessor
US6525971B2 (en) 1995-06-30 2003-02-25 Micron Technology, Inc. Distributed write data drivers for burst access memories
US5610864A (en) 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US6725349B2 (en) * 1994-12-23 2004-04-20 Intel Corporation Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US6804760B2 (en) * 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
WO1996029652A1 (en) * 1995-03-22 1996-09-26 Ast Research, Inc. Rule-based dram controller
US5572686A (en) * 1995-06-05 1996-11-05 Apple Computer, Inc. Bus arbitration scheme with priority switching and timer
US5619471A (en) * 1995-06-06 1997-04-08 Apple Computer, Inc. Memory controller for both interleaved and non-interleaved memory
US5737572A (en) * 1995-06-06 1998-04-07 Apple Computer, Inc. Bank selection logic for memory controllers
US5867422A (en) * 1995-08-08 1999-02-02 University Of South Florida Computer memory chip with field programmable memory cell arrays (fpmcas), and method of configuring
US5873114A (en) * 1995-08-18 1999-02-16 Advanced Micro Devices, Inc. Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles
US5956744A (en) * 1995-09-08 1999-09-21 Texas Instruments Incorporated Memory configuration cache with multilevel hierarchy least recently used cache entry replacement
US5850632A (en) * 1995-09-08 1998-12-15 Texas Instruments Incorporated Memory access controller utilizing cache memory to store configuration information
US5898856A (en) * 1995-09-15 1999-04-27 Intel Corporation Method and apparatus for automatically detecting a selected cache type
US5701438A (en) * 1995-09-29 1997-12-23 Intel Corporation Logical relocation of memory based on memory device type
US6035369A (en) 1995-10-19 2000-03-07 Rambus Inc. Method and apparatus for providing a memory with write enable information
KR0170905B1 (ko) * 1995-11-06 1999-03-30 김주용 디램
US5590071A (en) * 1995-11-16 1996-12-31 International Business Machines Corporation Method and apparatus for emulating a high capacity DRAM
US5729504A (en) * 1995-12-14 1998-03-17 Micron Technology, Inc. Continuous burst edo memory device
US6567904B1 (en) 1995-12-29 2003-05-20 Intel Corporation Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices
US5715476A (en) * 1995-12-29 1998-02-03 Intel Corporation Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic
US7681005B1 (en) 1996-01-11 2010-03-16 Micron Technology, Inc. Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
US5802550A (en) * 1996-01-17 1998-09-01 Apple Computer, Inc. Processor having an adaptable mode of interfacing with a peripheral storage device
US5881264A (en) * 1996-01-31 1999-03-09 Kabushiki Kaisha Toshiba Memory controller and memory control system
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
KR100293359B1 (ko) * 1996-05-15 2001-09-17 박종섭 광역 d-램의 입출력 제어방법
US6401186B1 (en) 1996-07-03 2002-06-04 Micron Technology, Inc. Continuous burst memory which anticipates a next requested start address
US6981126B1 (en) 1996-07-03 2005-12-27 Micron Technology, Inc. Continuous interleave burst access
US5745913A (en) * 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US6092165A (en) * 1996-08-16 2000-07-18 Unisys Corporation Memory control unit using a programmable shift register for generating timed control signals
US6047361A (en) * 1996-08-21 2000-04-04 International Business Machines Corporation Memory control device, with a common synchronous interface coupled thereto, for accessing asynchronous memory devices and different synchronous devices
US5937423A (en) * 1996-12-26 1999-08-10 Intel Corporation Register interface for flash EEPROM memory arrays
US6279069B1 (en) * 1996-12-26 2001-08-21 Intel Corporation Interface for flash EEPROM memory arrays
US6154825A (en) * 1997-03-07 2000-11-28 Intel Corporation Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations
US6088761A (en) * 1997-03-31 2000-07-11 Sun Microsystems, Inc. Reduced pin system interface
JPH1115742A (ja) 1997-06-19 1999-01-22 Kofu Nippon Denki Kk メモリ・リフレッシュ制御回路
AU9798798A (en) 1997-10-10 1999-05-03 Rambus Incorporated Power control system for synchronous memory device
GB2381103B (en) 1997-12-17 2003-06-04 Fujitsu Ltd Memory access methods and devices for use with random access memories
US6154821A (en) * 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
US6275243B1 (en) * 1998-04-08 2001-08-14 Nvidia Corporation Method and apparatus for accelerating the transfer of graphical images
US6209074B1 (en) * 1998-04-28 2001-03-27 International Business Machines Corporation Address re-mapping for memory module using presence detect data
US6446184B2 (en) 1998-04-28 2002-09-03 International Business Machines Corporation Address re-mapping for memory module using presence detect data
JPH11328961A (ja) * 1998-05-21 1999-11-30 Fujitsu Ltd 電子回路装置及びインタフェース回路
US6601130B1 (en) * 1998-11-24 2003-07-29 Koninklijke Philips Electronics N.V. Memory interface unit with programmable strobes to select different memory devices
US6046957A (en) * 1999-08-26 2000-04-04 Winbond Electronics Corporation Semiconductor memory device with flexible configuration
US6668299B1 (en) 1999-09-08 2003-12-23 Mellanox Technologies Ltd. Software interface between a parallel bus and a packet network
DE19945004A1 (de) 1999-09-20 2001-03-22 Micronas Gmbh Speichersteuerung zum Durchführen von Schaltbefehlen
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US7010642B2 (en) * 2000-01-05 2006-03-07 Rambus Inc. System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
US6625685B1 (en) * 2000-09-20 2003-09-23 Broadcom Corporation Memory controller with programmable configuration
JP4071930B2 (ja) * 2000-11-22 2008-04-02 富士通株式会社 シンクロナスdram
TW594743B (en) * 2001-11-07 2004-06-21 Fujitsu Ltd Memory device and internal control method therefor
US7111143B2 (en) * 2003-12-30 2006-09-19 Infineon Technologies Ag Burst mode implementation in a memory device
US20050144372A1 (en) * 2003-12-31 2005-06-30 Robert Walker Memory device controlled with user-defined commands
JP4569921B2 (ja) * 2004-08-04 2010-10-27 パナソニック株式会社 省電力メモリアクセス制御装置
US7516264B2 (en) * 2005-02-09 2009-04-07 International Business Machines Corporation Programmable bank/timer address folding in memory devices
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7464225B2 (en) * 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US7562271B2 (en) * 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
TWI312113B (en) * 2006-05-23 2009-07-11 Novatek Microelectronics Corp Systems and methods capable of controlling multiple data access
US8266361B1 (en) * 2009-01-28 2012-09-11 Cypress Semiconductor Corporation Access methods and circuits for devices having multiple buffers
KR20100100395A (ko) * 2009-03-06 2010-09-15 삼성전자주식회사 복수의 프로세서를 포함하는 메모리 시스템
CN102270500A (zh) * 2011-03-29 2011-12-07 西安华芯半导体有限公司 可实现dram自复位的方法及可自复位的dram
US8982654B2 (en) 2013-07-05 2015-03-17 Qualcomm Incorporated DRAM sub-array level refresh
JP2015108972A (ja) * 2013-12-04 2015-06-11 富士通株式会社 演算装置、演算装置の決定方法及びプログラム
EP3306479A1 (en) * 2016-10-06 2018-04-11 Stichting IMEC Nederland Memory structure comprising scratchpad memory

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725945A (en) * 1984-09-18 1988-02-16 International Business Machines Corp. Distributed cache in dynamic rams
GB8725111D0 (en) * 1987-03-13 1987-12-02 Ibm Data processing system
US4937791A (en) * 1988-06-02 1990-06-26 The California Institute Of Technology High performance dynamic ram interface
GB2226666B (en) * 1988-12-30 1993-07-07 Intel Corp Request/response protocol
DE68923864T2 (de) * 1989-04-19 1996-05-02 Ibm Anordnung zur Speicher- und Peripherie-Bausteinauswahl.
US4967397A (en) * 1989-05-15 1990-10-30 Unisys Corporation Dynamic RAM controller
US5175835A (en) * 1990-01-10 1992-12-29 Unisys Corporation Multi-mode DRAM controller
EP0440445B1 (en) * 1990-01-31 1996-06-19 Hewlett-Packard Company System memory initialization with presence detect encoding
JPH04336347A (ja) * 1991-05-13 1992-11-24 Ricoh Co Ltd メモリ装置

Also Published As

Publication number Publication date
US5307320A (en) 1994-04-26
JP3590413B2 (ja) 2004-11-17
GB2271003B (en) 1996-02-14
GB2271003A (en) 1994-03-30
GB9313110D0 (en) 1993-08-11
JPH06208503A (ja) 1994-07-26

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20100625