GB2353399A

GB2353399A - Testing printed or integrated circuits

Info

Publication number: GB2353399A
Application number: GB9919626A
Authority: GB
Inventors: Nigel Stuart Priest; William Thomas Phillips; Emsley Douglas Dacres; Graham Brian Hollands
Original assignee: 3Com Corp
Current assignee: 3Com Corp
Priority date: 1999-08-20
Filing date: 1999-08-20
Publication date: 2001-02-21
Also published as: GB2353402A; GB9919626D0; GB2353401A; GB9927423D0; GB9927426D0

Abstract

A multi-layer printed or integrated circuit device having a multiplicity of layers 2 - 13 includes at least one signal layer 6 which embodies an electrical circuit and is disposed intermediate other layers of the device, and a multiplicity of exposed electrical terminal conductors 3 of which at least some extend through layers of the device to the signal layer. A sensing layer 8 which is conductive is disposed adjacent the signal layer, being electrically separated from the layer and any other conductive layer of the device. The sensing layer is capacitatively coupled to the signal layer and is electrically connected to a terminal 3a. The internal sensing layer takes the place of an external probe and facilitates testing of the device, particularly by a capacitative sensing method. The device and a semi conductor die 18 are mounted on a heat sink 17 and interconnected by bond wires 20.

Description

2353399 MULTI-LAYER ELECTRONIC CIRCUIT INCLUDING INTERMEDIATE CAPACITATIVE

SENSING LAYER AND IMPROVED METHODS OF TESTING.

Field of the Invention

This invention relates to electronic circuits and particularly to multilayer electronic device comprising at least one signal layer constituted by a printed or integrated circuit.

Typically the device includes insulating layers, power layers and a heat sink or heat spreader. The present invention primarily concerns an improved construction of such a multi-layer devices to render it more easily testable.

BackRround to the Invention Testing is customary and important adjunct to the manufacturing process for electronic is circuits. Different methods of testing have been devised and are in use at the present time.

One method, generally known as vector testing, requires the application of a large multiplicity of sets of binary signals (the vectors) to the input terminals of the circuit and the obtaining of the relevant sets of outputs. For circuits of any complexity, the vector testing mode is complex and often len thy, and has the general disadvanta c that the 9 It) 9 output vectors do not necessarily indicate directly the nature and location of a fault that causes them to depart from the vector values which would be produced if the circuit were operative in a fully correct manner.

Another known form of testing, described for example in United States patent US 5274336, is a capacitative method wherein a plurality of spring loaded conductive probes (known as a 'bed of nails') make selective ohmic contact directly with a devices input and output pins on one surface of the multi-layer device. A capacitative probe is constituted by an external plate, suspended over or otherwise separated from the circuit. The capacitance between a selected pin and the probe can be measured by stimulation from an AC source.

Such a technique is useful for in circuit testing because if a terminal pin is not properly soldered to its trace on the printed circuit board, there is an additional capacitor in series with the capacitance formed with the capacitative probe. The existence of this small 2 capacitance may readily be used to determine whether pins make proper connection (by means of adequate soldering) with the printed circuit, by for example discriminating 1.

between the actual measured capacitance and an expected or computed value.

One advantage of a capacitative sensing technique of this nature is that no knowledge of 1 1 the core functionality of the device is required. The technique depends only on the physical properties of the packaging. It is simpler and in general much more rapid than vector' testing. Nevertheless, there are practical difficulties which render such a W capacitative measuring technique potentially unsuitable. In particular, increasing miniaturization renders the technique less suitable, owing to the difficulty of determining the precise location of the fault. Furthermore, if the device includes a ground plane or for example a heat spreader which is not electrically isolated ftom other planes in the device, the obtaining of accurate results or occasionally any meaningful results from a C) capacitatively coupled test probe are difficult. Thus despite its convenience and rapidity, capacitatively coupled probe testing of multi-layer circuits appears to be unavailable for a variety of circuits owing to their construction.

Summary of the Invention

The present invention has as its main object a new construction for multilayer circuits so as to make them better adapted for vectorless test techniques in general and capacitatively coupled testing in particular.

The invention is based on the incorporation within a multi-layer device of a conductive sensing plane or plate which is not electrically utilised in the circuits of the device and is very preferably isolated conductively from the other plates or planes in the device. Such a sensing plane can be disposed adjacent any signal plane of the device and accordingly not 1 be blocked by a ground or power plane or a heat spreader. The plane can be connected or tracked internally within the device to an accessible connection, such as a solder ball, on an external face of the device in order to enable its connection to the circuit required for the application and sensing of a signal intended for measurement of capacitative values 3 between the sensing plane and the pins connected to the various layers of the multi-layer device.

Brief Description of the Drawing 5

The accompanying single figure, Figure 1, illustrates in simplified form, and not to scale, a cross-section through a multi-layer electronic circuit device embodying the present invention.

Detailed Description of Preferred Embodiment

The drawing illustrates, by way of example, a multi-layer electronic circuit which is particularly adapted in accordance with the invention for capacitative testing. The device 1 has an uppermost insulating layer 2 which is the support for a ball grid array 3) composed is of a multiplicity of solder balls which are connected by 'vertical' traces, extending through vias in the relevant layers, to underlying layers of the device. These traces should be without electrical contact to any conductive layer except with the respective layer to which they make predetermined connection Beneath the insulating layer 2 is a conductive 1 ground layer or plane 4. Beneath this layer is a further insulating layer 5. The next underlying layer 6 is a 'signaP layer constituted by a printed or integrated circuit The 1 Z_ functionality of this circuit is of no particular importance to the invention.

Underlying the signal layer 6 is a further insulating layer 7. A conductive la\er 8, hereinafter called 'sensing layer' is disposed below the insulating layer 7, the sensing layer 8 being thereby isolated conductively from the signal layer 6 but being capacitanvely coupled to it. Although there could be a respective sensing layer for each signal laver. in this example the sensing layer also serves for capacitative sensing of a second signal layer which underlies the insulating layer 8 and is separated from it by an insulating layer 9.

A yet further insulating layer 11 is disposed between the second signal layer 10 and a power layer 12 (which has a layout of the power rail WC for the various circuits).

4 Beneath the power layer is another insulating layer 1-33 which is in this example 1 substantially co-planer with a power ring 14. Layer 13) and ring 14 are disposed on a 1 cavity layer 15 made for example of copper. This layer is separated by an insulating layer 16 from a conductive heat spreader 17.

Also on the heat spreader in this example is a semiconductor die 18, which is secured to the heat spreader by an adhesive layer 19.

Conductive leads in the lead frame of the die are, in this example, connected, according to the requirements of the circuit device, to the power ring 14, the power layer 12 and the signal layers 6 and 10 by means of bond wires 20.

The foregoing is given by way of example only. It is not necessary that there be a multiplicity of signal layers. Moreover, the sense layer 8 need not be, as shown, in the Z.

middle of the layers making up the device but may, in general, be anywhere in the layers provided that, very preferably, it is adjacent, apart from separating insulation, to one or more of the signal layers. It follows that for complex devices having a multiplicity of signal layers there may be more than one sense layer such as the layer 8.

The layer 8 or each such layer is provided with external access by means of a wire or conductive trace which extends to at least one accessible terminal, herein constituted by one or more of the solder balls (3a) in the ball grid array (3)).

It will be apparent that the sense layer 8 may be used for capacitative testing of, for example, the terminal connections such as the connection of solder ball - 3b to signal layer 6, taking the place of the capacitative probe which is used in conjunction with the 'bed of nails' described in the aforementioned US patent. The usefulness of the known method is not thereby limited by the disposition of the ground plane or the heat spreader. However, the invention is not, obviously, limited to that method of testing.

Conventional features such as encapsulation have been omitted for the sake of brevity and simplicity.

In a modification, an amplifier which may be required for the performance of a capacitative test could be incorporated into the device (such as on die 18) to minimize the external components required for such a test.

6

Claims

1. A multi-layer electronic device comprising:

a multiplicity of layers (2 - 1 3 3) including at least one signal layer (6) which embodies an electrical circuit and is disposed intermediate other layers of the device., a multiplicity of exposed electrical terminal conductors (3) of which at least some extend throuCrh layers of said device to said signal layer- and In a sensing layer (8) which is conductive and is disposed adjacent said signal layer, being electrically separated from said layer and any other conductive layer of said device, wherein said sensing layer is capacitatively coupled to said signal layer and is electrically 1:1 1-5 connected to at least a respective one (3a) of said terminal conductors.

2. A device according to claim 1 wherein the terminal conductors (3) have substantially co-planar parts.

3. A device according to claim 2 wherein the terminal conductors comprise a solder ball array.

4. A device according to any foregoing claim wherein the layers include a ground plane (4). 25

5. A device according to any foregoing claim wherein the layers include a heat spreader (17).

6. A device according to any foregoing claim wherein there are at least two signal layers 30 (6, 10).

7 7. A device according to calim 6 wherein the sensing layer is disposed between said two signal layers.

8. A method of testing comprising measuring the capacitance between said respective one (3a) of said terminal conductors and a selected one of said terminal conductors (3).

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