JP4635901B2 - Module package - Google Patents

Description

The present invention measures the junction temperature of a semiconductor in a module such as an LSI (Large Scale Integration) or an IC (Integrated Circuit), or a module such as an MCM (Multi Chip Module) or SIP (System In Package) in which LSI or IC is embedded. those related to the module package with terminals for inspection to enable.

  In recent years, digital home appliances such as digital television have been improved in performance and functionality. In order to achieve high performance, digital signal processing has been speeded up, and circuit integration has been promoted in order to realize many functions. In order to increase the speed of digital signal processing, the operation clock of the system LSI is increased, the data bus is expanded, and a high-speed memory device such as DDR is employed. In order to achieve high integration of circuits, a system LSI or a memory device is sealed and stored in one package by using MCM or SIP technology. Generally, it is often stored in a BGA (Ball Grid Array) package.

  As the speed increases, the amount of heat generated by a semiconductor chip such as a system LSI or memory incorporated in the package increases. Further, with the progress of higher integration, the heat generation of each semiconductor chip stored in the package is added, and the heat generation amount per package tends to further increase.

  In order to keep the junction temperature of the semiconductor housed in the package within the guaranteed operating range, heat sinks and heat radiating fins are prepared in the package to increase the heat radiation effect.

  Along with this, the material cost of the package and the cost for the heat radiating fins are increasing, and the thickness is also increasing. In order to keep the junction temperature of the built-in semiconductor within the guaranteed operating range while suppressing the increase in cost and thickness, measure the built-in semiconductor junction temperature accurately and take the minimum heat dissipation measures in terms of cost and component thickness. Is desirable.

  Therefore, it is conceivable to control the semiconductor chip so that it does not exceed a certain temperature by incorporating a temperature measuring element. (For example, refer to Patent Document 1).

  However, general-purpose products such as memories generally do not include such a temperature measuring element. Therefore, the junction temperature of a semiconductor such as a built-in memory is measured by attaching a thermocouple to the package surface. Since a method of attaching a thermocouple to a measurement object and measuring the temperature is already common and there is a dedicated measuring device, a detailed description is omitted.

  An outline of a conventional measurement method using a module package and a thermocouple will be described with reference to FIG. FIG. 3 is a side view showing a configuration of a BGA package which is a conventional module package. A semiconductor chip 111, a substrate 101, a mold 107, and a plurality of solder balls 104 are included. The thermal resistance 102 and the measurement point 103 are conceptual objects and are not actually built in.

  The physical bonding between the semiconductor chip 111 incorporated in the mold 107 and the substrate 101 is performed by bonding the semiconductor chip 111 to the substrate with an adhesive sheet having a thickness of several μm (not shown) interposed therebetween. Electrically, the connection is made using a flip chip method or a wire bonding method. Since any method is general, the description is omitted. The solder ball 4 is a connection means with an external substrate (not shown). That is, an example of a BGA (Ball Grid Array) in which a plurality of solder balls 4 are arranged on the lower surface of the substrate 101 is shown here. The physical bonding between the BGA package and the external substrate is performed by soldering the lands corresponding to the solder balls 4 of the external substrate and the solder balls 4 by a reflow process.

  A method for measuring the junction temperature of the built-in semiconductor chip 111 in the conventional BGA package is as follows.

  In a state where the semiconductor chip 111 is operated under predetermined operating conditions, a thermocouple is attached to the measurement point 103 on the surface of the mold 107, and the surface temperature Tc of the package is measured. Next, the junction temperature Tj of the semiconductor chip 111 is calculated using the thermal resistance θjc102 of the BGA package and the power consumption Pa of the semiconductor chip 111 under a predetermined operating condition. The calculation formula is Tj = Tc + (Pa × θjc).

It is also conceivable to measure the temperature by a four-terminal resistance measurement method using a resistor connected and fixed to the temperature measurement object. (For example, refer to Patent Document 2).
JP-A-8-335522 JP-A-6-137960

  However, in the configuration of Patent Document 2 as described above, it is necessary to separately add a resistor component for temperature measurement, and the cost of the resistor is extra, and there is a problem that the cost increases. In addition, since the resistors are stacked on the object to be measured, there has been a problem that the thickness of the package increases by the thickness of the resistors.

  In the case of a module incorporating a multichip, the Tj of the semiconductor chip rises due to heat generated by other semiconductor chips. Further, Tc is affected by the heat generation of all the semiconductor chips. Therefore, in order to obtain Tj of each semiconductor chip, in addition to θjc of all the semiconductor chips, a thermal resistance between all the semiconductor chips is newly required, and the calculation formula becomes complicated. In general, since the thermal resistance is a parameter with a large error, the error in the calculation formula increases as the ratio of the thermal resistance increases. Therefore, in the conventional junction temperature measurement method using a thermocouple, the relational expression between Tc and each chip Tj is complicated, and there is a problem that an error between the calculated junction temperature and the actual junction temperature becomes large.

  In order to solve the above problems, a module package of the present invention includes a first substrate on which a first semiconductor is mounted, a sealing member stacked above the semiconductor and in the thickness direction of the first substrate, The first substrate is wired including the lower region of the first semiconductor, and both ends thereof are bifurcated and provided with a first copper wiring connected to first four terminals that can be contacted from the outside. One of the four terminals is a terminal for inspecting the junction temperature of the first semiconductor.

In the module package of the present invention, since the copper wiring on the substrate on which the semiconductor chip is mounted is used as a temperature measurement resistor, it is not necessary to add a temperature measurement resistor component, and the cost does not increase. Further, it is not necessary to stack the resistor parts on the semiconductor chip, and no additional thickness is generated. In addition, by providing four temperature test terminals branched and drawn out from the resistors arranged directly under the plurality of semiconductor chips sealed inside the module so that they can be measured from the outside, the junction of the plurality of semiconductor chips sealed inside the module Each temperature can be accurately checked.

  Accordingly, since the junction temperatures of a plurality of built-in semiconductors can be accurately measured, it is possible to take a minimum heat dissipation measure in terms of cost and component thickness. As a result, a high-performance, high-quality and inexpensive module can be realized.

(Embodiment 1)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view showing the configuration of the module package according to the first embodiment of the present invention. Further, FIG. 2 shows (a) a plan perspective view and (b) a side perspective view of the same configuration. In addition, in both figures, the same number shall be attached | subjected about the same component. Actually, (a) the plane perspective view should be shown because there are many wiring patterns from the solder balls 4 and the respective IC (semiconductor) chips, but are omitted for the sake of clarity.

  The module package shown in FIGS. 1 and 2 includes a first substrate 1, a second substrate 2, a third substrate 3, a plurality of solder balls 4, two composite sheets 8, an IC chip 11, an IC chip 12, and an IC 13. , Temperature inspection terminals 51, 52, 53, 54, 61, 62, 63, 64, copper wiring patterns 31, 33, 34, 36, 37, 41, 43, 44, 46, 47, copper wiring branches 32, 35, 42 and 45.

  The first substrate 1, the second substrate 2, and the third substrate 3 are three-layer multilayer printed boards that are stacked in the thickness direction of the substrate. They are laminated with the composite sheet 8 as an insulator sandwiched between the substrates. On the upper surface of the third substrate 3, an area of a printed board on which a general-purpose IC such as an IC 13 or a memory can be mounted is secured.

  The composite sheet 8 is considered to be an adhesive resin sheet containing an epoxy resin or the like. The upper and lower substrates are adhesively bonded. Further, electrical connection between the substrates can be achieved by leaving a through hole in the composite sheet and filling it with a conductor. As an example, the composite sheet is also described as a prepreg in JP-A-2005-26573.

  In addition, although the example which pinches | interposes the composite sheet 8 showed the lamination | stacking between board | substrates, it is not necessarily required. The substrate may be cut out to form a cavity, a semiconductor chip may be embedded, and the substrate may be stacked without sandwiching the composite sheet 8. Moreover, although the board | substrate to laminate | stack was shown the example of 3 sheets, it should just be 1 or more regardless of 3 sheets.

  The solder ball 4 includes temperature inspection terminals 61, 62, 63, and 64, which are connection means to an external substrate (not shown). That is, an example of a BGA (Ball Grid Array) in which a plurality of solder balls 4 are arranged on the lower surface of the first substrate 1 is shown here. The physical bonding between the module package and the external board is performed by soldering the lands corresponding to the solder balls 4 of the external board and the solder balls 4 by a reflow process. Of course, a connector terminal may be provided in place of the solder ball 4 to connect to an external substrate.

  The solder ball 4 is also an external interface of the module package. A circuit such as an IC chip 11 mounted on the first substrate 1, an IC chip 12 mounted on the second substrate 2, an IC 13 mounted on the third substrate 3, and a circuit prepared on an external substrate; Are electrically connected via the solder balls 4.

  The second substrate 2 that is the sealing member of the IC chip 11 and the third substrate 3 that is the sealing member of the IC chip 12 have a thickness of about several hundred μm, and are the sealing members of the IC chip 11 and the IC chip 12. A certain composite sheet 8 also has a thickness of about several hundred μm. Since the IC chip 11 and the IC chip 12 are sealed in the upper direction by the second substrate 2 and the third substrate 3 and in the lateral direction by the composite sheet 8, respectively, the height does not exceed the thickness of the composite sheet, and the composite sheet It is necessary to mount in a size that does not exceed the cavity part.

  Therefore, a bare die is used in which the semiconductor wafer is polished to be thinner than the thickness of the composite sheet and then diced to a size smaller than the cavity size of the composite sheet. In the physical bonding of the IC chip 11 and the IC chip 12 and the substrate, the bare die is bonded to the substrate with an adhesive sheet having a thickness of several μm not shown. Electrically, the connection is made using a flip chip method or a wire bonding method. Since any method is general, the description is omitted. Since the IC chip 13 is mounted on the area of the printed board secured on the upper surface of the third substrate 3, there is no restriction in the thickness direction. Therefore, general-purpose ICs stored in the package are physically and electrically connected in a normal reflow process. In addition, although the sealing member of IC chip 11 and IC chip 12 showed the example of the board | substrate and the composite sheet, it is not limited. For example, the case where it seals with a mold instead of a composite sheet and a board | substrate is also considered. In that case, the sealing member is a molding material.

  The IC chip 11 and the IC chip 12 are sealed inside the module package. Therefore, the IC chip 11 and the IC chip 12 cannot be connected to the thermocouple from the outside.

  The copper wiring patterns 31, 33, 34, 36, 37, 41, 43, 44, 46 and 47 are the solder balls 4 and the respective ICs on the first substrate 1, the second substrate 2 and the third substrate 3, respectively. (Semiconductor) It is the same copper wiring as the electric wiring pattern from the chip, and is generated in an etching process for forming the copper wiring on the insulating layer of the printed board. Therefore, the copper wiring patterns 31, 33, 34, 36, 37, 41, 43, 44, 46, and 47 have the same thickness as the electric wiring pattern. The copper wiring patterns 31, 33, 34, 36, 37, 41, 43, 44, 46, 47 generally have a thickness of about a few tens of μm.

  In general, a metal has a characteristic that an electric resistance characteristic changes according to a temperature change. In the case of copper as well, the resistance temperature coefficient of copper is known to be 4.3 × 10 −3 (Ω / ° C.). The equation for calculating the temperature change using the resistance value of copper and the temperature coefficient of resistance is T2 = (T1 + 1 / (4.3 × 10−3)) × (R2 / R1) −1 / (4.3 × 10-3). Here, T2 is the temperature after change, T1 is the temperature before change, R2 is the resistance value after change, and R1 is the resistance value before change.

  Therefore, the present invention makes it possible to measure the junction temperature of a built-in semiconductor chip using the resistance temperature coefficient and resistance value of copper. In the module package of the present invention, a copper wiring pattern is routed to a predetermined wiring length on a substrate portion below a built-in semiconductor chip, both ends of the copper wiring pattern are branched and stretched, and two pairs of copper wiring patterns are stretched. It is characterized by providing four terminals that are connected and can be contacted from the outside for measuring the resistance value.

  The copper wiring pattern 31 is routed around the upper surface region of the first substrate 1 directly below the semiconductor chip 11 so as to have a predetermined wiring length. The upper surface region of the first substrate 1 directly below the semiconductor chip 11 is in direct contact with the lower surface of the semiconductor chip 11 and has the same temperature as the semiconductor chip 11. Actually, an adhesive sheet having a thickness of several μm is often sandwiched, but can be ignored. This is because the adhesive sheet is very thin and has good thermal conductivity, so there is little influence. Therefore, the temperature of the semiconductor chip 11 can be measured by measuring the temperature of the copper wiring pattern 31. The temperature of the copper wiring pattern 31 is calculated from the resistance temperature coefficient and the resistance value of the copper wiring pattern 31 using the above calculation formula.

  In order to measure the junction temperature of the semiconductor chip 11 most accurately, it is desirable to dispose the copper wiring pattern 31 in the upper surface region of the first substrate 1 directly under the semiconductor chip 11. However, when it cannot be arranged in the upper surface region of the first substrate 1 directly below the semiconductor chip 11 due to mounting restrictions, it may be arranged not directly under the semiconductor chip 11, or as indicated by 41 in FIG. In addition, it may be arranged in a lower region other than the upper surface such as the lower surface region of the substrate directly under the semiconductor chip. In that case, since the semiconductor chip 11 and the copper wiring pattern 31 are not in direct contact with each other, a value at which the temperature is reduced by the amount of heat conducted to the substrate and dissipated is measured. In that case, it can correct | amend by calculating | requiring the temperature fall part from the heat conductive characteristic of a board | substrate, and adding further.

  The copper wiring pattern 31 is drawn in a wave shape as shown in FIG. 2 when the copper wiring pattern 31 is arranged directly below the semiconductor chip 11 in order to accurately measure the temperature of the semiconductor chip 11. This is because the wiring length of the copper wiring pattern 31 to be routed is increased in a limited area corresponding to. While the resistance value of the copper wiring pattern 31 increases in proportion to the wiring length, the resistance temperature coefficient is constant regardless of the wiring length. Therefore, as the resistance value of the copper wiring pattern 31 increases, the amount of change in the resistance value with respect to the temperature change Becomes larger. That is, in order to measure a change in resistance value in response to a small temperature change, it is advantageous to increase the resistance value by increasing the wiring length because a smaller temperature change can be observed. On the other hand, the semiconductor chip 11 is generally several mm in size, and the width of the copper wiring on the substrate and the insulation distance between the copper wiring are generally several tens to several hundreds of micrometers. Since the upper surface region of the first substrate 1 directly below the semiconductor chip 11 is limited, the wiring length that can be routed is also limited. Therefore, the copper wiring pattern 31 may be a straight line when the wiring length is the shortest. Conceivable.

  Both ends of the copper wiring pattern 31 have branch points 32 and 35, which are bifurcated. From the branch point 32, copper wiring patterns 33 and 34 are formed, and from the branch point 35, copper wiring patterns 36 and 37 are formed. The copper wiring pattern 33 is provided with a temperature inspection terminal 61, the copper wiring pattern 34 is provided with a temperature inspection terminal 62, the copper wiring pattern 36 is provided with a temperature inspection terminal 64, and the copper wiring pattern 37 is provided with a temperature inspection terminal 63. The temperature inspection terminals 61, 62, 63, and 64 are all part of the solder balls 4 that are external terminals of the module. Therefore, the resistance value of the copper wiring pattern 31 can be measured by using the temperature inspection terminals 61, 62, 63, 64 from the outside, and the junction temperature of the semiconductor chip 11 can be calculated and inspected.

  Here, the branching points 32 and 35 are provided at both ends of the copper wiring pattern 31, and the bifurcating branches are not affected by the resistance values of the copper wiring patterns 33, 34, 36, and 37, respectively. This is for measuring the resistance value. Since this method is also disclosed in Patent Document 2 as a four-terminal method using a resistor, detailed description thereof is omitted.

  The feature of the present invention is that the above copper wiring patterns 31, 33, 34, 36, and 37 are the same copper wiring as the electrical wiring pattern to be wired from the semiconductor chip 11. That is, the resistor for calculating the temperature is the same copper wiring as the electric wiring pattern from the semiconductor chip 11 and is branched into two branches in the four-terminal method.

  Therefore, it is not necessary to add a resistor component for temperature measurement, and it is not necessary to stack the resistor component on the semiconductor chip.

  Further, the junction temperature can be similarly measured in the semiconductor chip 12 which is the second semiconductor chip incorporated in the module. The semiconductor chip 12 is mounted on the second substrate 2. As shown in FIG. 2, the internal wiring is the same as in the case of the semiconductor chip 11, and therefore, the description will be made paying attention to the difference.

  In the case of the semiconductor chip 12, the semiconductor chip 12 is mounted on the second substrate 2 that is stacked and provided between the first substrate 1 and the third substrate 3 that serves as a sealing member. Therefore, the temperature inspection terminal is provided on the upper surface of the module having a short wiring distance. That is, the temperature inspection terminals 51, 52, 53, 54 are provided on the third substrate 3.

  Unlike the solder balls 4, the temperature inspection terminals 51, 52, 53 and 54 are not means for connecting to an external substrate. Therefore, as shown in FIG. 2, the diameter of the temperature inspection terminals 51, 52, 53, 54 is smaller than the diameter of the solder ball 4. Because the diameter of the solder ball is determined depending on the bonding method with the external substrate and the wiring density of the external substrate, there is a limit to reducing the temperature, but the temperature inspection terminals 51, 52, 53, 54 are external substrates. This is because it can be made smaller because it does not depend on Therefore, the required area of the temperature inspection terminals 51, 52, 53, 54 provided on the upper surface can be reduced as compared with the case where the solder balls 4 on the back surface are provided. As a result, the size of the module package can be reduced.

  Further, since the semiconductor chip 13 is arranged on the upper surface of the module, it is possible to measure the junction temperature by connecting a thermocouple as in the prior art.

  Therefore, even in a module incorporating three semiconductor chips 11, 12, and 13, the junction temperatures of all the semiconductor chips can be accurately measured and inspected. In the present embodiment, an example of three stones is shown, but any number of stones of two or more stones is possible as well.

  The junction temperature of the semiconductor chip 11 sealed in the module package can be measured and inspected accurately by measuring the resistance value using the temperature inspection terminals 61, 62, 63 and 64 and using the above-described calculation formula. The junction temperature of the semiconductor chip 12 sealed in the module package can be accurately measured and inspected using the above-described calculation formula by measuring the resistance value using the temperature inspection terminals 51, 52, 53, and 54. The junction temperature of the semiconductor chip 12 mounted on the upper surface of the module package can be measured and inspected by connecting the thermocouple and measuring Tc and using the above-described calculation formula.

  Therefore, in the temperature inspection method for a module package and a built-in semiconductor according to the present invention, the copper wiring on the substrate on which the semiconductor chip is mounted is used as a temperature measurement resistor, so that it is necessary to add a resistor component for temperature measurement. There is no increase in cost. Further, since it is not necessary to stack the resistor parts on the semiconductor chip, no additional thickness is generated.

  In addition, the four temperature test terminals branched and drawn out from the copper wiring arranged directly under the plurality of semiconductor chips sealed inside the module are arranged so that they can be measured from the outside so that they can be measured from the outside. The resistance value of the formed copper wiring can be accurately measured by the four probe method. Using the above-described calculation formula based on the measured resistance value, it is possible to accurately measure and inspect each junction temperature of a plurality of built-in semiconductor chips.

  Therefore, it is necessary to separately add a resistor component for temperature measurement, and it is possible to solve the problem that the cost of the resistor is extra and the cost increases. Further, since the resistor is stacked on the object to be measured, the problem that the thickness of the package increases by the thickness of the resistor can be solved. Further, in the conventional junction temperature measurement method, in the case of a module incorporating a multichip, the relational expression between Tc and each chip Tj becomes complicated, and the error between the calculated junction temperature and the actual junction temperature becomes large. can be solved.

  The module package according to the present invention has an effect of realizing a high-performance, high-quality and inexpensive module, and is useful as a package of LSI, IC, MCM, SIP, or the like.

The perspective view which shows the structure of the module package which concerns on 1st embodiment of this invention. The top view and side view which show the structure of the module package which concerns on 1st embodiment of this invention Side view showing the configuration of a conventional BGA package

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st board | substrate 2 2nd board | substrate 3 3rd board | substrate 4 Solder ball 8 Composite sheet 11 IC chip 12 IC chip 13 IC
51, 52, 53, 54, 61, 62, 63, 64 Temperature inspection terminal 31, 33, 34, 36, 37, 41, 43, 44, 46, 47 Copper wiring pattern 32, 35, 42, 45 Copper wiring branch

Claims (6)

A first substrate on which the first semiconductor is mounted; a sealing member stacked above the semiconductor and in a thickness direction of the first substrate; and a lower region of the first semiconductor on the first substrate. A first copper wiring having a predetermined wiring length connected to the first four terminals that are bifurcated at both ends and can be contacted from the outside. A module package characterized by being a temperature inspection terminal for a semiconductor chip. The lower region of the first semiconductor of the first copper interconnect module package of claim 1, wherein the wired wavy. Equipped with external terminals for external board connection,
The module package according to claim 1, wherein the first four terminals are included in the external terminals. The module package according to any one of claims 2 to 3, wherein the first four terminals are provided on an upper surface of the module package. Equipped with external terminals for external board connection,
A second substrate for mounting a second semiconductor is provided between the first substrate and the sealing member, and the second substrate is wired including the lower region of the second semiconductor, and both ends thereof are bifurcated. The second copper wiring connected to the second four terminals that are branched to the outside and are accessible from the outside, the first four terminals are included in the external terminals, and the second four terminals are included in the module package. Provided on the top surface,
Further, characterized in that the first 4 terminal is testing terminal of the temperature of the first semiconductor chip, the second 4 terminals are terminals for inspection of the temperature of the second semiconductor chip The module package according to claim 1. 6. The module package according to claim 5, wherein a diameter of the second four terminals is smaller than a diameter of the external terminals.

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