JPH05226524A - Electronic device mounting equipment - Google Patents

Abstract

(57) [Abstract] [Purpose] The test socket has a structure in which the inductance of its connection pin is reduced and the noise due to current changes is reduced. Try to be accurate. [Structure] The test socket (zero force socket) 100 is a socket body 10 in which an LSI is mounted.
1 and a socket connection pin 1 whose upper end is exposed on the LSI installation surface of the socket body and whose lower end is exposed on the lower surface of the socket body 1
10 and the connection pin 11 fixed inside the main body
0, the first and second wiring layers 130 and 140 electrically connected to the Vdd pin 112 and the GND pin 113, respectively.
And Vdd additional pins 121 and GN that are conductively connected to the two wiring layers and have their respective lower ends protruding from the lower end surface of the socket.
The configuration includes the D additional pin 122.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effectively applied to a mounting apparatus for electronic equipment, and is used for a so-called "zero force socket" in which an LSI having a large number of external lead terminals can be removably mounted. And useful mounting technology.

[0002]

2. Description of the Related Art In a large-scale integrated circuit (LSI) including a large number of functions such as a processor, the number of external connection pins (external lead terminals) has increased in proportion to the number of gates. An LSI whose number is about 500 has also been proposed. When inspecting such an LSI with a tester at the time of product completion, the completed LSI is temporarily mounted in a multi-pin compatible socket into which external lead terminals can be freely inserted and removed, The pin-corresponding sockets are mounted on a test wiring board (see FIG. 2), and then various product inspections are performed.

The multi-pin compatible socket used for this product inspection is provided with the same number of socket connecting pins as the external lead terminals of the LSI, but this number of pins increases as the number of external lead terminals of the LSI increases. When the number of pins increases, the contact pressure generated during the attachment / detachment with respect to the external lead terminal per pin is accumulated, and a considerable force is required for the insertion / removal of the LSI, which sometimes leads to a situation where the insertion / removal is impossible. Therefore, a so-called "zero force socket" having a contact pressure reducing mechanism for loosening the contact pressure with the external lead terminal of the LSI has been proposed on the socket side.
In this zero force socket, the width of the upper opening of the socket hole formed in the upper part of the socket connection pin can be freely adjusted, and the holding means for sandwiching the opening from the outside (Fig. 2 contact pressure reduction mechanism 19
0) is provided, and the holding means is operated in accordance with the attachment / detachment of the LSI.

[0004]

However, the zero force socket having such a structure has the socket connecting pin 1
The shape of 10 is complicated (for example, the cross section is Y as shown in FIG. 2).
It is known that the conductive portion becomes thicker and the inductance increases. This inductance causes generation of power supply noise, but since the magnitude of the noise is proportional to the magnitude of the inductance and the amount of change in the current (= L × di / dt), the noise is large in the zero force socket. Such an increase in noise exceeds a clock frequency of 100 MHz, and a high-performance LS of recent years such as a high-performance processor having a high applied voltage level.
The effect is markedly exhibited by I, and the LSI may malfunction due to the generation of noise depending on the signal level. Therefore, when an LSI (high-performance LSI) product is inspected using the zero force socket, even if the LSI to be inspected is a product within the standards (good product), the zero force
The use of the socket causes noise, malfunction of the LSI, and the product being judged to be a non-standard product, which lowers the reliability of the product test and eventually deteriorates the yield of the product.

The present invention has been made in view of the above circumstances, and noise of a test socket (mounting device) used when a product test of an LSI chip is performed is reduced due to a change in current in the socket. It is an object of the present invention to provide a mounting apparatus for an electronic device, which has a configuration and is capable of accurately performing product inspection even for a high-performance LSI. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the mounting apparatus for an electronic device of the present invention includes a socket main body part to which the electronic device is attached, and a socket connection in which at least one end is exposed to the electronic device connection part of the socket main body part and the other end is exposed to the lower surface of the main body part. Pins, one or more wiring layers fixed to the inside of the body portion and electrically connected to the socket connection pins, and electrically connected to the wiring layers and at least a part of which is exposed on the lower surface of the body portion. It is configured to have an additional pin.

[0007]

When the electronic device and the socket connecting pin are connected, the additional pin is connected to the socket connecting pin and further to the electronic device through the wiring layer, so that the apparent inductance of the connecting pin is small. As a result, noise generated when a power supply voltage is applied is reduced.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a perspective view showing an entire zero force socket 100 according to the present invention. The zero force socket 100 shown in the figure has a main body 101 made of a square-shaped insulator (for example, plastic) having an opening 100a in the center thereof, and a first body 101 having one end protruding from the surface 101a of the main body 101. Connection pin (socket connection pin) 1
,, second connection pins (additional pins) 120, 120, ... For reducing inductance, and the first connection pin 110 which is formed in parallel with the surface 101a of the main body portion 101 and will be described later. The first and second pins are conductively connected to the Vdd pin, the GND pin, and the second connection pin 120.
The wiring boards (conductive layers) 130 and 140 are used as main components (see FIGS. 2 and 3).

Of these, the first connection pin 110 is
LSI mounted on this zero force socket 100
The external connection pins (external lead terminals) on the side (not shown) are provided in a one-to-one correspondence, and will be described later with reference to FIG.
As shown in (4), the external lead terminals of the LSI are arranged at positions (outer periphery of the square-shaped main body 101) facing the positions. A socket hole 110a is provided inside the first connection pin 110 so that external lead terminals (151, 152, 153 in FIG. 2) are inserted when the LSI is mounted. Also, the second connection pin 120 is
It is provided to reduce the apparent inductance of the pins (power supply pins; 112 and 113 in FIG. 2) that are conductively connected to the power supply terminals (152 and 153 in FIG. 2) of the LSI among the first connection pins 110. The power supply pins 112 and 113 and the additional pin 120 are electrically connected to each other via the first wiring board 130 or the second wiring board 140.

FIG. 2 shows the first connection pin (socket connection pin) 11 of the zero force socket 100 shown in FIG.
0 and the second connection pin (additional pin) 120 and the first and second
3 is a cross-sectional view of essential parts showing a mutual connection state with wiring boards (conductive layers) 130 and 140 of FIG. 3, FIG. 3 shows socket connection pins 110 and additional pins 120, and first wiring board 130 and second wiring board 140. It is a perspective view which shows the positional relationship of.

As shown in these figures, the first connecting pin 110 formed inside the socket has an L
Socket hole for receiving SI external lead terminal 1
10a, and a known contact pressure reducing device 190 (the detailed configuration is omitted) for opening and closing the Y-shaped electrode portion of the socket hole 110a. Since the first connection pin 110 formed in this way has a complicated shape and the conductor portion is thick, the inductance increases, and when the LSI is mounted on the socket 100 and a product inspection is performed, Usually, noise is easily added to the inspection signal. Therefore, in the zero force socket 100 of the present embodiment, the second connection pin and the wiring board are provided as described later to reduce noise.

By the way, in the present embodiment, the first connecting pin 110 constituting the essential part of the zero force socket is the LS.
It is divided into three types according to the type of the I-side pin (external lead terminal). That is, the signal pin 111 to which the data signal line of the LSI is connected, the constant voltage power line (Vd
D) is connected to the Vdd pin 112 and the ground line is connected to the GND pin 113. Then, as shown in FIG. 2, the signal pin 111 has an LSI-side signal external lead terminal 151 in its socket hole, and the Vdd pin 112 has L.
The Vdd external lead terminal 152 on the SI side is the GND pin 1
The GND external lead terminals 153 on the LSI side are inserted in 13 and are electrically connected. In the zero force socket 100 of this embodiment, the Vdd pin 112 and the GND pin 113 among these three types of socket connection pins are used.
The inductance of is substantially reduced.

A second connecting pin (additional pin) 120 provided to reduce the inductance of the Vdd pin 112 and the GND pin 113 is a Vdd additional pin 121 connected to the wiring board 130 and a second wiring board. It is classified as a GND additional pin 122 connected to 140. Of the above-mentioned two types of pins, the Vdd pin 112 has a socket hole having an upper end side exposed on the surface of the main body 101 and a lower end side having the main body 1.
It is connected to the corresponding Vdd (not shown) terminal of the wiring board 200 by penetrating 01 and projecting to the test wiring board 200 side. On the other hand, the Vdd pin 112 is conductively connected to the first wiring board 130 and further connected to the Vdd additional pin 121 via the wiring board 130. Thus Vd
The Vdd additional pin 121 electrically connected to the d pin 112 is conductively connected to another Vdd terminal (not shown) of the test wiring board 200. Therefore, when the Vdd external lead terminal 152 of the LSI is connected to the Vdd pin 112, the external lead terminal 152 is actually the Vdd pin 112.
Not only the wiring board 20 via the Vdd additional pin 121
Since it is connected to the Vdd terminal of 0, the apparent inductance of the Vdd pin is reduced. Therefore, when a signal is output, the output circuit operates to reduce noise generated when a large transient current flows through the power supply line or the ground line.

Similarly to the Vdd pin 112, the GND pin 113 has its upper end side having a socket hole exposed on the surface of the main body 101 and its lower end penetrating the main body 101 and protruding toward the test wiring board 200. The wiring board 200
Is connected to the corresponding ground terminal GND (not shown).
On the other hand, the GND pin 113 is conductively connected to the second wiring board 140 and further connected to the GND additional pin 122 via the wiring board 140. In this way, GND pin 11
The GND additional pin 122 conducted to 3 is conductively connected to another ground terminal (not shown) of the test wiring board 200. Therefore, the GND external lead terminal 153 of the LSI
Is connected to the GND pin 113, the external lead terminal 153 is actually not only the GND pin 113 but also the GND.
Since it is connected to the ground terminal of the wiring board 200 via the additional pin 122, the apparent inductance of the GND pin is reduced. Therefore, when a signal is output, the output circuit operates to reduce noise generated when a large transient current flows through the power supply line or the ground line.

As described above, in the above embodiment, the first connecting pin 110 provided on the zero force socket is used.
Of these, the power pins 112 and 113 are conductively connected to the wiring layers 130 and 140 formed inside the main body, respectively.
Further, additional pins 121, 122 are added to the wiring layers 130, 140.
The conductive inductance of the zero force socket reduces the apparent inductance of the power supply pin of the zero force socket, thereby reducing the noise generated when a transient current flows through the power supply pin. Therefore, it becomes possible to accurately perform product inspection of a high-performance LSI such as a high-speed processor to which a high voltage is applied and a transient current instantaneously flows, by using the socket.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the present embodiment, as shown in FIG. 1, the additional pin 120 is implanted inside the socket connecting pin installation region that is implanted in a square shape, but the present invention is not limited to this, and for example, the socket connecting pin and the socket connecting pin. You may alternately plant in the empty area between.
In addition, in this embodiment, a cellophore socket having a socket connecting pin with reduced inductance is set to L.
Although the operation and effect have been described in the case of being applied to the SI product inspection, the noise is reduced and a remarkable effect can be obtained even when the LSI is used in the actual product.

In the above description, the case where the invention made by the present inventor is mainly used for the semiconductor technology which is the field of application which is the background of the invention has been described, but the present invention is not limited to this and other general Similar effects can be obtained even when the electronic device is used when it is mounted on the product body.

[0018]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. In a socket that electrically connects an electronic device and a wiring board on which the electronic device is mounted,
The inductance of the connecting pin is reduced.

[Brief description of drawings]

FIG. 1 is a perspective view showing an entire zero force socket 100 according to the present invention.

FIG. 2 is a diagram illustrating a first connection pin 110 and a second connection pin of the zero force socket 100, and first and second wiring boards 13.
It is a principal part sectional view which shows the mutual connection state with 0 and 140.

FIG. 3 is a perspective view three-dimensionally showing the positional relationship between socket connection pins 110, additional pins 120, first wiring board 130, and second wiring board 140.

[Explanation of symbols]

 100 zero force socket (socket) 101 socket body 110 socket connection pin (first connection pin) 112 Vdd pin (power supply pin) 113 GND pin (power supply pin) 120 additional pin (second connection pin) 121 Vdd additional pin (Additional pin) 122 GND Additional pin (additional pin) 130 First wiring board (first wiring layer) 140 Second wiring board (second wiring layer) 200 Wiring board

Claims (3)

[Claims] 1. A socket body to which an electronic device is mounted, a socket connection pin having at least one end exposed to an electronic device connection part of the socket body and another end exposed to a lower surface of the body part, and an inside of the body part. And at least one wiring layer fixedly connected to the socket connection pin and conductively connected to the socket connection pin, and an additional pin conductively connected to the wiring layer and at least a part of which is exposed on the lower surface of the main body. Electronic device mounting equipment. 2. The electronic device is a semiconductor integrated circuit,
The mounting device for electronic equipment according to claim 1, wherein the socket connection pin is provided corresponding to an external lead terminal of a semiconductor integrated circuit. 3. The socket connection pin is connected to an external lead terminal that is conductively connected to a power supply voltage terminal and a ground terminal inside the semiconductor integrated circuit, and the wiring layer is a power supply provided on a wiring board via an additional pin. The electronic device mounting apparatus according to claim 1, wherein the mounting device is electrically connected to the terminal.