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FR2750250B1 - Procede de protection d'une galette de circuits integres, et galette de circuits integres obtenue - Google Patents

Procede de protection d'une galette de circuits integres, et galette de circuits integres obtenue

Info

Publication number
FR2750250B1
FR2750250B1 FR9607680A FR9607680A FR2750250B1 FR 2750250 B1 FR2750250 B1 FR 2750250B1 FR 9607680 A FR9607680 A FR 9607680A FR 9607680 A FR9607680 A FR 9607680A FR 2750250 B1 FR2750250 B1 FR 2750250B1
Authority
FR
France
Prior art keywords
wafer
integrated circuits
protecting
circuits obtained
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9607680A
Other languages
English (en)
Other versions
FR2750250A1 (fr
Inventor
Sophie Siettler
Jean Noel Audoux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Solaic SA
Original Assignee
Solaic SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Solaic SA filed Critical Solaic SA
Priority to FR9607680A priority Critical patent/FR2750250B1/fr
Publication of FR2750250A1 publication Critical patent/FR2750250A1/fr
Application granted granted Critical
Publication of FR2750250B1 publication Critical patent/FR2750250B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
FR9607680A 1996-06-20 1996-06-20 Procede de protection d'une galette de circuits integres, et galette de circuits integres obtenue Expired - Fee Related FR2750250B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR9607680A FR2750250B1 (fr) 1996-06-20 1996-06-20 Procede de protection d'une galette de circuits integres, et galette de circuits integres obtenue

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9607680A FR2750250B1 (fr) 1996-06-20 1996-06-20 Procede de protection d'une galette de circuits integres, et galette de circuits integres obtenue

Publications (2)

Publication Number Publication Date
FR2750250A1 FR2750250A1 (fr) 1997-12-26
FR2750250B1 true FR2750250B1 (fr) 1998-08-21

Family

ID=9493252

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9607680A Expired - Fee Related FR2750250B1 (fr) 1996-06-20 1996-06-20 Procede de protection d'une galette de circuits integres, et galette de circuits integres obtenue

Country Status (1)

Country Link
FR (1) FR2750250B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2788375B1 (fr) 1999-01-11 2003-07-18 Gemplus Card Int Procede de protection de puce de circuit integre

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6461934A (en) * 1987-09-02 1989-03-08 Nippon Denso Co Semiconductor device and manufacture thereof
JP2597396B2 (ja) * 1988-12-21 1997-04-02 ローム株式会社 シリコーンゴム膜のパターン形成方法
WO1991000683A2 (fr) * 1989-07-07 1991-01-24 Irvine Sensors Corporation Production d'unites de circuits electroniques contenant des couches empilees de circuits integres a reacheminement des conducteurs
FR2671417B1 (fr) * 1991-01-04 1995-03-24 Solaic Sa Procede pour la fabrication d'une carte a memoire et carte a memoire ainsi obtenue .
JPH0567620A (ja) * 1991-09-06 1993-03-19 Tanaka Kikinzoku Kogyo Kk バンプ形成方法
JPH05283488A (ja) * 1992-03-30 1993-10-29 Nec Corp 半導体装置

Also Published As

Publication number Publication date
FR2750250A1 (fr) 1997-12-26

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Legal Events

Date Code Title Description
ST Notification of lapse