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FR2388410A1 - Procede de realisation de transistors a effet de champ de type mos, et transistors realises selon un tel procede - Google Patents

Procede de realisation de transistors a effet de champ de type mos, et transistors realises selon un tel procede

Info

Publication number
FR2388410A1
FR2388410A1 FR7711912A FR7711912A FR2388410A1 FR 2388410 A1 FR2388410 A1 FR 2388410A1 FR 7711912 A FR7711912 A FR 7711912A FR 7711912 A FR7711912 A FR 7711912A FR 2388410 A1 FR2388410 A1 FR 2388410A1
Authority
FR
France
Prior art keywords
transistors
type field
realized according
effect transistors
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7711912A
Other languages
English (en)
Other versions
FR2388410B1 (fr
Inventor
Marcel Roche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR7711912A priority Critical patent/FR2388410A1/fr
Priority to US05/897,169 priority patent/US4160683A/en
Priority to GB15315/78A priority patent/GB1594537A/en
Priority to IT48972/78A priority patent/IT1102177B/it
Priority to DE19782817342 priority patent/DE2817342A1/de
Publication of FR2388410A1 publication Critical patent/FR2388410A1/fr
Application granted granted Critical
Publication of FR2388410B1 publication Critical patent/FR2388410B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention se rapporte aux procédés de fabrication des transistors à effet de champ du type MOS à grille isolée. Le positionnement précis de la grille par rapport aux régions de source et de drain conditionnant les performances en haute fréquence, le procédé prévoit de créer préalablement ces régions 43 et 44 par diffusion à partir de portions de silice dopée telles que 70 et d'utiliser ensuite ces portions comme masque pour réaliser la grille 45, et sa connexion extérieure 72. Les applications sont notamment du domaine des transistors pour très hautes fréquences.
FR7711912A 1977-04-20 1977-04-20 Procede de realisation de transistors a effet de champ de type mos, et transistors realises selon un tel procede Granted FR2388410A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR7711912A FR2388410A1 (fr) 1977-04-20 1977-04-20 Procede de realisation de transistors a effet de champ de type mos, et transistors realises selon un tel procede
US05/897,169 US4160683A (en) 1977-04-20 1978-04-17 Method of manufacturing field effect transistors of the MOS-type
GB15315/78A GB1594537A (en) 1977-04-20 1978-04-18 Method of manufacturing field effect transistor of the mos-type and transistors produced by this method
IT48972/78A IT1102177B (it) 1977-04-20 1978-04-19 Procedimento di realizzazione di transistori ad effetto di campo di tipo mos e transistori realizzati secondo un tale procedimento
DE19782817342 DE2817342A1 (de) 1977-04-20 1978-04-20 Verfahren zur herstellung von feldeffekttransistoren

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7711912A FR2388410A1 (fr) 1977-04-20 1977-04-20 Procede de realisation de transistors a effet de champ de type mos, et transistors realises selon un tel procede

Publications (2)

Publication Number Publication Date
FR2388410A1 true FR2388410A1 (fr) 1978-11-17
FR2388410B1 FR2388410B1 (fr) 1981-11-13

Family

ID=9189666

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7711912A Granted FR2388410A1 (fr) 1977-04-20 1977-04-20 Procede de realisation de transistors a effet de champ de type mos, et transistors realises selon un tel procede

Country Status (5)

Country Link
US (1) US4160683A (fr)
DE (1) DE2817342A1 (fr)
FR (1) FR2388410A1 (fr)
GB (1) GB1594537A (fr)
IT (1) IT1102177B (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54140483A (en) * 1978-04-21 1979-10-31 Nec Corp Semiconductor device
JPS55163860A (en) * 1979-06-06 1980-12-20 Toshiba Corp Manufacture of semiconductor device
US4280855A (en) * 1980-01-23 1981-07-28 Ibm Corporation Method of making a dual DMOS device by ion implantation and diffusion
US5202574A (en) * 1980-05-02 1993-04-13 Texas Instruments Incorporated Semiconductor having improved interlevel conductor insulation
US4317276A (en) * 1980-06-12 1982-03-02 Teletype Corporation Method of manufacturing an insulated gate field-effect transistor therefore in a silicon wafer
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
FR2525389A1 (fr) * 1982-04-14 1983-10-21 Commissariat Energie Atomique Procede de positionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre
US4830975A (en) * 1983-01-13 1989-05-16 National Semiconductor Corporation Method of manufacture a primos device
US4553315A (en) * 1984-04-05 1985-11-19 Harris Corporation N Contact compensation technique
US4818714A (en) * 1987-12-02 1989-04-04 Advanced Micro Devices, Inc. Method of making a high performance MOS device having LDD regions with graded junctions
US5015595A (en) * 1988-09-09 1991-05-14 Advanced Micro Devices, Inc. Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask
JP3426043B2 (ja) * 1994-09-27 2003-07-14 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6933237B2 (en) * 2002-06-21 2005-08-23 Hewlett-Packard Development Company, L.P. Substrate etch method and device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USB381501I5 (fr) * 1964-07-09
GB1187611A (en) * 1966-03-23 1970-04-08 Matsushita Electronics Corp Method of manufacturing Semiconductors Device
US3434021A (en) * 1967-01-13 1969-03-18 Rca Corp Insulated gate field effect transistor
US3837071A (en) * 1973-01-16 1974-09-24 Rca Corp Method of simultaneously making a sigfet and a mosfet
US3959025A (en) * 1974-05-01 1976-05-25 Rca Corporation Method of making an insulated gate field effect transistor

Also Published As

Publication number Publication date
DE2817342A1 (de) 1978-10-26
US4160683A (en) 1979-07-10
IT1102177B (it) 1985-10-07
GB1594537A (en) 1981-07-30
FR2388410B1 (fr) 1981-11-13
IT7848972A0 (it) 1978-04-19

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