Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28158—Making the insulator
  • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
  • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28158—Making the insulator
  • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
  • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
  • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Definitions

• the present invention relates to a method for producing a spacer structure and in particular to a method for producing a spacer structure for field effect transistors in a sub-100 nanometer range.
• spacer structures or sidewall insulations are used in particular for sufficient isolation of so-called gate stacks and for the self-adjusting formation of source / drain regions.
• FIGS. 1A and 1B show simplified sectional views to illustrate essential manufacturing steps for producing a spacer structure according to the prior art.
• gate stacks G with a gate insulation layer 200 and an overlying control or gate layer 300 are formed on a carrier substrate 100, which usually consists of a semiconductor material.
• an anisotropic etching process such as reactive ion etching (RIE) is carried out in a subsequent production step, as a result of which the final spacer structure S400 is obtained, which provides adequate insulation or adequate protection of the gate stack G and, in addition, self-adjusting formation Source / drain regions S and D in the carrier substrate 100 are made possible, for example, by means of ion implantation (not shown).
• RIE reactive ion etching
• the disadvantage of such a conventional method for producing spacer structures is that the dimensions of the respective spacer S400 are not adequately checked.
• the conformal deposition on the gate stacks G already results in considerable fluctuations in thickness for different spacers S400, the use of reactive ion etching (RIE) also including the risk of damage to a gate insulation layer or a gate oxide.
• RIE reactive ion etching
• the invention is therefore based on the object of creating a method for producing a spacer structure which has increased accuracy. According to the invention, this object is achieved by the measures of claim 1.
• the gate insulation layer having a gate deposition inhibition layer by the subsequent structuring of the gate layer and the cover deposition inhibition layer to form gate stacks and the final deposition of an insulation layer selective to the deposition inhibition layers m of the gate insulation layer and on the gate layer, for the first time spacer structures can also be easily controlled in a sub-100 nanometer range and can be formed with high precision.
• the elimination of the reactive ion etching process that is normally used means that there is no risk of damaging the sensitive gate insulation layers.
• an implantation for forming weakly doped doping regions in the semiconductor substrate is preferably carried out, as a result of which a channel length can be set very precisely and in a self-adjusting manner using the spacer structure.
• a further isolation layer can preferably be carried out selectively with respect to the anti-deposition layers to form an expanded spacer structure and a further implantation to form source / dram areas in the semiconductor substrate, as a result of which a spacer structure with improved insulation properties is obtained which is suitable to form the terminal regions of a respective Feldef ⁇ Stammtransistors ustierend itself.
• the deposition inhibition layers preferably consist of a nitride layer and / or an oxynitride layer with a high nitrogen content, an ozone-assisted TEOS deposition being carried out during the selective formation of the insulation layer. leads. In this case, you not only get a particularly high-quality gate dielectric, but also a particularly high selectivity in the deposition using standard materials.
• the thin residual layers formed in the selective deposition on the deposition inhibiting layers can be removed by wet etching, as a result of which contact openings for the source / dram areas and the gate layer can be formed in a particularly simple manner.
• the selectively deposited insulation layers can be thermally cured and thus compressed.
• the deposition inhibition layers for exposing the gate layer and the source / dram regions in the semiconductor substrate are preferably removed, a siliconizable material is deposited over the entire surface and then a conversion of a surface layer of the exposed semiconductor substrate and the gate layer using the siliconizable material designed to form highly conductive connection areas.
• FIGS. 1A and 1B simplified sectional views to illustrate essential manufacturing steps in the manufacture of a spacer structure according to the prior art
• Figures 2A to 2F simplified sectional views to illustrate essential manufacturing steps in the manufacture of a spacer structure according to the invention.
• FIGS. 2A to 2F show simplified sectional views to illustrate essential production steps in the production of a spacer structure according to the present invention, reference being made, for example, to a standard process for producing CMOS transistors.
• active areas can first be formed, for example, by means of an STI method (shallow trench isolation) in a carrier substrate 1, which preferably consists of a silicon semiconductor substrate. Subsequently, in order to implement a gate insulation layer 2 with at least one gate deposition layer 2A, a nitride layer such as Si 3 N_ ⁇ and / or oxynitride layer with a high nitrogen content (SiON) is formed on the carrier substrate 1, for example by a deposition process.
• a nitride layer such as Si 3 N_ ⁇ and / or oxynitride layer with a high nitrogen content (SiON) is formed on the carrier substrate 1, for example by a deposition process.
• SiON high nitrogen content
• this gate insulation layer 2 can also consist of a multiple layer consisting of the gate deposition inhibition layer 2A described above (nitride layer and / or oxynitride layer with a high nitrogen content) and an oxide layer 2B such as SiO 2 . In this way, in particular in the area of non-volatile semiconductor memory elements, improved charge retention properties can be achieved.
• a control or gate layer 3 is then formed in accordance with FIG. 2A, preferably approximately 100 to 150 nanometer thick semiconductor material (polysilicon or polysiGe) being deposited.
• a cover anti-deposition layer 4 is also formed, which in the same way as the gate anti-deposition layer 2A has a nitride layer and / or oxynitride layer with a high nitrogen content.
• An approximately 5 to 10 nanometer thick silicon nitride layer 4 is preferably deposited on the surface of the gate layer 3 by means of an LPCVD process (low pressure chemical vapor deposition).
• LPCVD process low pressure chemical vapor deposition
• a hard mask layer 5 can be formed on the surface of the covering / deposition inhibition layer 4, for example an approximately 50 nanometer thick TEOS layer being deposited as an oxide hard mask.
• the actual structuring then takes place using conventional and therefore not shown, for example, photolithographic processes, a resist material being applied, exposed and structured and then the hard mask 5 being structured first using the structured resist.
• the resist is then removed or stripped and the actual structuring of the layers 3 and 4 is carried out using the structured hard mask 5 to form gate stacks G, the gate deposition inhibiting layer 2A also being used as an etching stop layer.
• An anisotropic etching process is usually used here, in which case the hard mask 5 is finally removed and a sectional view according to FIG. 2B is obtained.
• an insulation layer 6 is now selectively deposited selectively with respect to the gate deposition inhibition layer 2A between the gate stacks G and the cover deposition inhibition layer 4 on the gate stacks G.
• selectivities are obtained with an oxide deposition in a range from 5 to 10, which is why a high oxide growth occurs on the side walls of the gate stack G, while only a small oxide growth can be observed on the horizontal surface of the deposition inhibiting layers 2A and 4.
• spacer structures with a thickness of, for example, 12 to 15 can be created Nanometers can be easily controlled and adjusted with high precision, which is why field-effect transistors in the sub 100 nanometer range can now be implemented in a simple and precise manner. In particular, however, no additional anisotropic etching processes such as reactive ion etching (RIE) have to be used in this production process, which is why damage or destruction of the sensitive gate insulation layers can be reliably prevented.
• RIE reactive ion etching
• weakly doped connection doping regions LDD can subsequently be formed in a self-adjusting manner in the semiconductor substrate 1 using the selectively deposited insulation layer 6, as a result of which effective channel lengths can be set very precisely, in particular in the case of very small structures below 100 nanometers.
• An ozone-assisted TEOS deposition process is preferably used for the selective deposition of the insulation layer 6, which can be implemented in a conventional chemical gas deposition device and with which a 0-zone-activated TEOS (tetraethyl orthosilicate) is produced can.
• a 0-zone-activated TEOS tetraethyl orthosilicate
• the growth of the insulation layer 6 or of the TEOS is strongly dependent on the exposed silicon surfaces. As a result, a significantly lower one occurs
• the gas flow ratio of TEOS to the ozone-containing gas has the value 10, while in the case of the stable or steady state of the gas flow ratio it has the value 0.4 after about one minute.
• This method advantageously also reduces the thickness of the anti-deposition layers 2A and 4, which results in a simplified removal of these layers at a later point in time. Since such a process is also at temperatures between 350 degrees Celsius to 600
• the thermal loads for the semiconductor circuits to be formed can be kept low, in particular in a lower temperature range.
• a so-called “densification anneal” or an additional oxidation step for densifying the selectively deposited insulation layer 6 can be carried out, as a result of which the electrical properties and in particular the insulation properties of this layer can be further improved.
• the selectively istschie ⁇ dene insulating layer may by means of a conventional Nassatz- The process is etched in such a way that the very thin residual layers formed on the anti-deposition layers 2A and 4 are completely removed and thus the gate anti-deposition layer 2A and the cover anti-deposition layer 4 are exposed.
• one or more further insulation layer (s) 7 can in turn be deposited selectively with respect to the anti-deposition layers 2A and 4, a thicker, preferably approximately 30 to 50 nanometer thick oxide layer now being formed on the rare walls of the gate stack G.
• the selective deposition method according to FIG. 2D again corresponds essentially to the selective deposition method according to FIG. 2C, which is why a repeated description is not given below.
• a further implantation 12 for forming the actual source / dramatic S / D in the semiconductor substrate 1 can be carried out, as a result of which reduced resistances in the Source- / Dramgeb ⁇ eten and improved electrical properties for the spacer structure consisting of the insulation layers 6 and 7 obtained.
• thermal healing can take place to improve the electrical properties of the spacer structure, as a result of which the deposited oxide is compacted and the damage to the substrate 1 that occurs during implantation is healed.
• a wet etching is carried out in a subsequent step, for example, as a result of which the anti-deposition layers 2A and 4 are removed and the semiconductor substrate 1 and the gate layer 3 are exposed.
• a nitride wet-etching process is preferably carried out.
• siliconizable material or a siliconizable metal layer such as cobalt, nickel or platinum can be used be deposited over the entire surface.
• a conversion of the crystalline surface layer of the semiconductor substrate 1 or polycrystalline surface layer of the gate layer 3 is then carried out using the siliconizable material to form highly conductive connection regions 8, with no silicide on the surfaces of this material that are not in contact with semiconductor material (silicon) is formed, but the deposited material (metal) remains, which in turn allows selective etching back of the deposited layer by means of a preferably wet chemical etching process.
• a large number of structuring steps can be carried out to form the spacer structures and the connection regions, which is why the manufacturing costs are further reduced.
• the transistor structure is completed in the usual way, which is why a detailed description is omitted below.
• CMOS transistor has been described above with reference to a CMOS transistor, although it is not restricted to this and in the same way comprises other semiconductor components which have field effect transistors with spacer structures, such as, for example, non-volatile semiconductor memory elements.
• the invention is not limited to the described nitride and / or oxynitride layers as anti-deposition layers in connection with the described Selox method, but also includes alternative anti-deposition layers and associated selective deposition methods.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Power Engineering (AREA)
• General Chemical & Material Sciences (AREA)
• Physics & Mathematics (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Crystallography & Structural Chemistry (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Chemical & Material Sciences (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Semiconductor Memories (AREA)
• Non-Volatile Memory (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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• 2002
  • 2002-06-17 DE DE10226914A patent/DE10226914B4/de not_active Expired - Fee Related
• 2003
  • 2003-05-14 CN CNB038142082A patent/CN100409410C/zh not_active Expired - Fee Related
  • 2003-05-14 TW TW092113140A patent/TWI229389B/zh not_active IP Right Cessation
  • 2003-05-14 EP EP03737879A patent/EP1514298A1/de not_active Withdrawn
  • 2003-05-14 JP JP2004514124A patent/JP2005534166A/ja active Pending
  • 2003-05-14 WO PCT/DE2003/001551 patent/WO2003107405A1/de active Application Filing
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