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DE69837135D1 - Integrierte Halbleiterschaltungsanordnung - Google Patents

Integrierte Halbleiterschaltungsanordnung

Info

Publication number
DE69837135D1
DE69837135D1 DE69837135T DE69837135T DE69837135D1 DE 69837135 D1 DE69837135 D1 DE 69837135D1 DE 69837135 T DE69837135 T DE 69837135T DE 69837135 T DE69837135 T DE 69837135T DE 69837135 D1 DE69837135 D1 DE 69837135D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
semiconductor circuit
integrated semiconductor
integrated
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69837135T
Other languages
English (en)
Other versions
DE69837135T2 (de
Inventor
Taketo Maesako
Kouki Yamamoto
Yoshinori Matsui
Kenichi Sakakibara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of DE69837135D1 publication Critical patent/DE69837135D1/de
Application granted granted Critical
Publication of DE69837135T2 publication Critical patent/DE69837135T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Static Random-Access Memory (AREA)
DE69837135T 1997-09-16 1998-09-11 Integrierte Halbleiterschaltungsvorrichtung Expired - Fee Related DE69837135T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP29023897 1997-09-16
JP29023897A JP3092558B2 (ja) 1997-09-16 1997-09-16 半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE69837135D1 true DE69837135D1 (de) 2007-04-05
DE69837135T2 DE69837135T2 (de) 2007-12-13

Family

ID=17753554

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69837135T Expired - Fee Related DE69837135T2 (de) 1997-09-16 1998-09-11 Integrierte Halbleiterschaltungsvorrichtung

Country Status (7)

Country Link
US (3) US6243279B1 (de)
EP (1) EP0908890B1 (de)
JP (1) JP3092558B2 (de)
KR (1) KR100396538B1 (de)
CN (1) CN1192391C (de)
DE (1) DE69837135T2 (de)
TW (1) TW397992B (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
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JP3092557B2 (ja) * 1997-09-16 2000-09-25 日本電気株式会社 半導体記憶装置
US6484065B1 (en) * 1997-12-29 2002-11-19 Kawasaki Microelectronics, Inc. DRAM enhanced processor
JP2000339954A (ja) * 1999-05-31 2000-12-08 Fujitsu Ltd 半導体記憶装置
US6151236A (en) * 2000-02-29 2000-11-21 Enhanced Memory Systems, Inc. Enhanced bus turnaround integrated circuit dynamic random access memory device
JP4209064B2 (ja) * 2000-02-29 2009-01-14 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
JP3871853B2 (ja) * 2000-05-26 2007-01-24 株式会社ルネサステクノロジ 半導体装置及びその動作方法
JP2002074941A (ja) * 2000-08-23 2002-03-15 Nec Corp 複数ラインバッファ型メモリｌｓｉ
US6587920B2 (en) * 2000-11-30 2003-07-01 Mosaid Technologies Incorporated Method and apparatus for reducing latency in a memory system
US6892279B2 (en) * 2000-11-30 2005-05-10 Mosaid Technologies Incorporated Method and apparatus for accelerating retrieval of data from a memory system with cache by reducing latency
JP3815717B2 (ja) * 2001-06-26 2006-08-30 シャープ株式会社 半導体集積回路
US6452865B1 (en) * 2001-08-09 2002-09-17 International Business Machines Corporation Method and apparatus for supporting N-bit width DDR memory interface using a common symmetrical read data path with 2N-bit internal bus width
US6493285B1 (en) * 2001-08-09 2002-12-10 International Business Machines Corporation Method and apparatus for sampling double data rate memory read data
JP2003242784A (ja) * 2002-02-15 2003-08-29 Kawasaki Microelectronics Kk 連想メモリ装置
KR100484254B1 (ko) * 2002-10-31 2005-04-22 주식회사 하이닉스반도체 반도체 메모리 장치의 리던던시 회로 및 그를 이용한 페일구제방법
KR100606242B1 (ko) * 2004-01-30 2006-07-31 삼성전자주식회사 불휘발성 메모리와 호스트간에 버퍼링 동작을 수행하는멀티 포트 휘발성 메모리 장치, 이를 이용한 멀티-칩패키지 반도체 장치 및 이를 이용한 데이터 처리장치
WO2006128090A2 (en) * 2005-05-26 2006-11-30 E. I. Du Pont De Nemours And Company High strength multilayer laminates comprising twisted nematic liquid crystals
US7744970B2 (en) * 2005-05-26 2010-06-29 E. I. Du Pont De Nemours And Company Multilayer laminates comprising twisted nematic liquid crystals
KR100717113B1 (ko) * 2005-09-12 2007-05-10 삼성전자주식회사 반도체 메모리 모듈 및 반도체 메모리 시스템
US7736532B2 (en) * 2005-12-29 2010-06-15 E.I. Du Pont De Nemours And Company Composition for reducing the transmission of infrared radiation
FR2920584B1 (fr) * 2007-08-29 2009-11-13 Commissariat Energie Atomique Memoire partagee
JP5731730B2 (ja) * 2008-01-11 2015-06-10 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置及びその半導体記憶装置を含むデータ処理システム
EP2418648B1 (de) * 2010-07-29 2013-03-06 STMicroelectronics (Grenoble 2) SAS RAM-Speichergerät, das selektiv mit ECC geschützt werden kann
CN103019983B (zh) * 2012-11-23 2016-03-30 北京宏思电子技术有限责任公司 Usb接口控制模块和usb设备的数据传输控制方法
KR102262550B1 (ko) * 2015-03-03 2021-06-10 에스케이하이닉스 주식회사 복수의 기능 블록들을 포함하는 반도체 장치 및 그것의 동작 방법
US9728236B1 (en) * 2016-10-21 2017-08-08 Dell Products, Lp System and method of training optimization for dual channel memory modules
US11226909B2 (en) 2018-08-24 2022-01-18 Rambus Inc. DRAM interface mode with interruptible internal transfer operation
CN117476053B (zh) * 2023-12-25 2024-03-26 长鑫闵科存储技术(上海)有限公司 存储器的布线结构及存储器

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5720983A (en) 1980-07-15 1982-02-03 Hitachi Ltd Memory chip
JPH069114B2 (ja) 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
JPS6238590A (ja) 1985-08-13 1987-02-19 Fujitsu Ltd 半導体記憶装置
JPH01145187A (ja) * 1987-07-05 1989-06-07 Japan Metaritsuku:Kk 金属箔の転写方法とその方法に用いる転写用シ−ト
JPH01146187A (ja) 1987-12-02 1989-06-08 Mitsubishi Electric Corp キヤッシュメモリ内蔵半導体記憶装置
JP2938511B2 (ja) 1990-03-30 1999-08-23 三菱電機株式会社 半導体記憶装置
JP2862948B2 (ja) * 1990-04-13 1999-03-03 三菱電機株式会社 半導体記憶装置
US5732241A (en) * 1990-06-27 1998-03-24 Mos Electronics, Corp. Random access cache memory controller and system
JP3238717B2 (ja) 1991-04-16 2001-12-17 三菱電機株式会社 半導体記憶装置におけるデータ転送装置
JP3268785B2 (ja) * 1990-12-25 2002-03-25 三菱電機株式会社 半導体記憶装置
JPH04307495A (ja) * 1991-04-04 1992-10-29 Mitsubishi Electric Corp 半導体記憶装置
JP3240161B2 (ja) 1991-04-18 2001-12-17 三菱電機エンジニアリング株式会社 半導体記憶装置
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
EP0535701A1 (de) * 1991-10-03 1993-04-07 Standard Microsystems Corporation Architektur und Verfahren zum Kombinieren eines statischen Cache-Speichers und eines dynamischen Hauptspeichers auf dem gleichen Chip (CDRAM)
EP0552667B1 (de) * 1992-01-22 1999-04-21 Enhanced Memory Systems, Inc. DRAM mit integrierten Registern
WO1994023374A2 (en) * 1993-03-30 1994-10-13 Ast Research Inc STROBOSCOPIC LOGIC FOR TRIGGERING SIMULATED BUS CONTROL CYCLES
US5581513A (en) * 1995-04-19 1996-12-03 Cirrus Logic, Inc. Continuous page random access memory and systems and methods using the same
US5657287A (en) * 1995-05-31 1997-08-12 Micron Technology, Inc. Enhanced multiple block writes to adjacent blocks of memory using a sequential counter
US5875470A (en) * 1995-09-28 1999-02-23 International Business Machines Corporation Multi-port multiple-simultaneous-access DRAM chip
US5761694A (en) * 1995-11-30 1998-06-02 Cirrus Logic, Inc. Multi-bank memory system and method having addresses switched between the row and column decoders in different banks
US5844856A (en) * 1996-06-19 1998-12-01 Cirrus Logic, Inc. Dual port memories and systems and methods using the same
JPH10326486A (ja) 1997-03-07 1998-12-08 Mitsubishi Semiconductor America Inc メモリ装置、およびデータ転送方法

Also Published As

Publication number Publication date
EP0908890A2 (de) 1999-04-14
JPH1186560A (ja) 1999-03-30
JP3092558B2 (ja) 2000-09-25
CN1212429A (zh) 1999-03-31
US6243279B1 (en) 2001-06-05
US6252788B1 (en) 2001-06-26
DE69837135T2 (de) 2007-12-13
CN1192391C (zh) 2005-03-09
KR100396538B1 (ko) 2003-11-28
TW397992B (en) 2000-07-11
EP0908890B1 (de) 2007-02-21
KR19990029792A (ko) 1999-04-26
EP0908890A3 (de) 1999-04-28
US6151256A (en) 2000-11-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee