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DE69326269D1 - Herstellungsverfahren von Kontaktöffnungen in integrierten Schaltungen - Google Patents

Herstellungsverfahren von Kontaktöffnungen in integrierten Schaltungen

Info

Publication number
DE69326269D1
DE69326269D1 DE69326269T DE69326269T DE69326269D1 DE 69326269 D1 DE69326269 D1 DE 69326269D1 DE 69326269 T DE69326269 T DE 69326269T DE 69326269 T DE69326269 T DE 69326269T DE 69326269 D1 DE69326269 D1 DE 69326269D1
Authority
DE
Germany
Prior art keywords
manufacturing process
integrated circuits
contact openings
openings
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69326269T
Other languages
English (en)
Other versions
DE69326269T2 (de
Inventor
Kuei-Wu Huang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE69326269D1 publication Critical patent/DE69326269D1/de
Publication of DE69326269T2 publication Critical patent/DE69326269T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
DE69326269T 1992-02-28 1993-02-23 Herstellungsverfahren von Kontaktöffnungen in integrierten Schaltungen Expired - Fee Related DE69326269T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/843,507 US5384483A (en) 1992-02-28 1992-02-28 Planarizing glass layer spaced from via holes

Publications (2)

Publication Number Publication Date
DE69326269D1 true DE69326269D1 (de) 1999-10-14
DE69326269T2 DE69326269T2 (de) 1999-12-30

Family

ID=25290206

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69326269T Expired - Fee Related DE69326269T2 (de) 1992-02-28 1993-02-23 Herstellungsverfahren von Kontaktöffnungen in integrierten Schaltungen

Country Status (4)

Country Link
US (2) US5384483A (de)
EP (1) EP0558260B1 (de)
JP (1) JP3517426B2 (de)
DE (1) DE69326269T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3068378B2 (ja) * 1993-08-03 2000-07-24 日本電気アイシーマイコンシステム株式会社 半導体記憶装置
US5531018A (en) * 1993-12-20 1996-07-02 General Electric Company Method of micromachining electromagnetically actuated current switches with polyimide reinforcement seals, and switches produced thereby
US5710460A (en) * 1995-04-21 1998-01-20 International Business Machines Corporation Structure for reducing microelectronic short circuits using spin-on glass as part of the interlayer dielectric
KR100208442B1 (ko) * 1995-06-24 1999-07-15 김영환 반도체 소자의 비아홀 형성방법
US5611941A (en) * 1995-07-17 1997-03-18 Rainbow Display Serivices Method for forming a ferroelectric liquid crystal spatial light modulator utilizing a planarization process
US6191484B1 (en) * 1995-07-28 2001-02-20 Stmicroelectronics, Inc. Method of forming planarized multilevel metallization in an integrated circuit
US5856707A (en) * 1995-09-11 1999-01-05 Stmicroelectronics, Inc. Vias and contact plugs with an aspect ratio lower than the aspect ratio of the structure in which they are formed
US5847460A (en) * 1995-12-19 1998-12-08 Stmicroelectronics, Inc. Submicron contacts and vias in an integrated circuit
US6111319A (en) * 1995-12-19 2000-08-29 Stmicroelectronics, Inc. Method of forming submicron contacts and vias in an integrated circuit
US5849637A (en) * 1996-06-10 1998-12-15 Wang; Chin-Kun Integration of spin-on gap filling dielectric with W-plug without outgassing
US5928960A (en) * 1996-10-24 1999-07-27 International Business Machines Corporation Process for reducing pattern factor effects in CMP planarization
KR100230405B1 (ko) 1997-01-30 1999-11-15 윤종용 반도체장치의 다층 배선 형성방법
JPH10223304A (ja) * 1997-01-31 1998-08-21 Whitaker Corp:The 防水型電気コネクタ組立体
JP3085231B2 (ja) * 1997-02-20 2000-09-04 日本電気株式会社 半導体装置の製造方法
EP0954017A3 (de) * 1998-04-16 2000-08-09 STMicroelectronics, Inc. Eine Halbleiterstruktur mit einem verbesserten Pre-metal-Dielektrik-Stapel
US6409312B1 (en) 2001-03-27 2002-06-25 Lexmark International, Inc. Ink jet printer nozzle plate and process therefor
DE102006015096B4 (de) * 2006-03-31 2011-08-18 Globalfoundries Inc. Verfahren zur Verringerung der durch Polieren hervorgerufenen Schäden in einer Kontaktstruktur durch Bilden einer Deckschicht
US8264091B2 (en) * 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3383568A (en) * 1965-02-04 1968-05-14 Texas Instruments Inc Semiconductor device utilizing glass and oxides as an insulator for hermetically sealing the junctions
JPS5819129B2 (ja) * 1975-12-10 1983-04-16 株式会社東芝 ハンドウタイソウチノ セイゾウホウホウ
US4489481A (en) * 1982-09-20 1984-12-25 Texas Instruments Incorporated Insulator and metallization method for VLSI devices with anisotropically-etched contact holes
US4615984A (en) * 1984-02-23 1986-10-07 Becton Dickinson & Company Dissociation of ligand-binder complex using ultrasound
BE901350A (fr) * 1984-12-21 1985-06-21 Itt Ind Belgium Methode pour preparer un dispositif semiconducteur avant d'y deposer un metal.
US4614021A (en) * 1985-03-29 1986-09-30 Motorola, Inc. Pillar via process
US4675984A (en) * 1985-09-19 1987-06-30 Rca Corporation Method of exposing only the top surface of a mesa
GB2216336A (en) * 1988-03-30 1989-10-04 Philips Nv Forming insulating layers on substrates
JPH02170553A (ja) * 1988-12-23 1990-07-02 Nec Corp 半導体装置の製造方法
US5068711A (en) * 1989-03-20 1991-11-26 Fujitsu Limited Semiconductor device having a planarized surface
JPH0435048A (ja) * 1990-05-31 1992-02-05 Kawasaki Steel Corp 半導体装置の多層配線形成方法
JPH0435047A (ja) * 1990-05-31 1992-02-05 Kawasaki Steel Corp 半導体装置の多層配線形成方法
JPH04139828A (ja) * 1990-10-01 1992-05-13 Nec Corp 半導体装置の製造方法
US5117273A (en) * 1990-11-16 1992-05-26 Sgs-Thomson Microelectronics, Inc. Contact for integrated circuits
JPH0645327A (ja) * 1991-01-09 1994-02-18 Nec Corp 半導体装置の製造方法
JPH04370934A (ja) * 1991-06-20 1992-12-24 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
DE69326269T2 (de) 1999-12-30
US5437763A (en) 1995-08-01
US5384483A (en) 1995-01-24
JP3517426B2 (ja) 2004-04-12
EP0558260B1 (de) 1999-09-08
EP0558260A1 (de) 1993-09-01
JPH0645274A (ja) 1994-02-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee