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DE69327600D1 - Herstellungsverfahren von Submikronkontakten - Google Patents

Herstellungsverfahren von Submikronkontakten

Info

Publication number
DE69327600D1
DE69327600D1 DE69327600T DE69327600T DE69327600D1 DE 69327600 D1 DE69327600 D1 DE 69327600D1 DE 69327600 T DE69327600 T DE 69327600T DE 69327600 T DE69327600 T DE 69327600T DE 69327600 D1 DE69327600 D1 DE 69327600D1
Authority
DE
Germany
Prior art keywords
manufacturing process
submicron
contacts
submicron contacts
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69327600T
Other languages
English (en)
Other versions
DE69327600T2 (de
Inventor
Fusen E Chen
Robert O Miller
Girish Anant Dixit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE69327600D1 publication Critical patent/DE69327600D1/de
Publication of DE69327600T2 publication Critical patent/DE69327600T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
DE69327600T 1992-02-28 1993-02-24 Herstellungsverfahren von Submikronkontakten Expired - Fee Related DE69327600T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84382292A 1992-02-28 1992-02-28

Publications (2)

Publication Number Publication Date
DE69327600D1 true DE69327600D1 (de) 2000-02-24
DE69327600T2 DE69327600T2 (de) 2000-06-21

Family

ID=25291102

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69327600T Expired - Fee Related DE69327600T2 (de) 1992-02-28 1993-02-24 Herstellungsverfahren von Submikronkontakten

Country Status (4)

Country Link
US (2) US5523624A (de)
EP (1) EP0558304B1 (de)
JP (1) JP3481965B2 (de)
DE (1) DE69327600T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563089A (en) * 1994-07-20 1996-10-08 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
US6791131B1 (en) * 1993-04-02 2004-09-14 Micron Technology, Inc. Method for forming a storage cell capacitor compatible with high dielectric constant materials
US5527736A (en) * 1995-04-03 1996-06-18 Taiwan Semiconductor Manufacturing Co. Dimple-free tungsten etching back process
US5639691A (en) * 1995-06-05 1997-06-17 Advanced Micro Devices, Inc. Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device
US5747379A (en) * 1996-01-11 1998-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating seamless tungsten plug employing tungsten redeposition and etch back
US5756396A (en) * 1996-05-06 1998-05-26 Taiwan Semiconductor Manufacturing Company Ltd Method of making a multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect
JPH10214895A (ja) * 1997-01-31 1998-08-11 Nec Corp 配線構造及びその製造方法
US6150691A (en) * 1997-12-19 2000-11-21 Micron Technology, Inc. Spacer patterned, high dielectric constant capacitor
US6075293A (en) * 1999-03-05 2000-06-13 Advanced Micro Devices, Inc. Semiconductor device having a multi-layer metal interconnect structure
US6245629B1 (en) * 1999-03-25 2001-06-12 Infineon Technologies North America Corp. Semiconductor structures and manufacturing methods
JP2003086669A (ja) * 2001-09-10 2003-03-20 Mitsubishi Electric Corp 電子装置およびその製造方法
KR100480632B1 (ko) * 2002-11-16 2005-03-31 삼성전자주식회사 반도체 소자의 금속 배선 형성 방법
US20060151822A1 (en) * 2005-01-07 2006-07-13 Shrinivas Govindarajan DRAM with high K dielectric storage capacitor and method of making the same
US20060151845A1 (en) * 2005-01-07 2006-07-13 Shrinivas Govindarajan Method to control interfacial properties for capacitors using a metal flash layer
US7316962B2 (en) * 2005-01-07 2008-01-08 Infineon Technologies Ag High dielectric constant materials
JP2009135219A (ja) 2007-11-29 2009-06-18 Renesas Technology Corp 半導体装置およびその製造方法
US8952553B2 (en) * 2009-02-16 2015-02-10 Toyota Jidosha Kabushiki Kaisha Semiconductor device with stress relaxation during wire-bonding
CN102299177B (zh) * 2010-06-22 2014-12-10 中国科学院微电子研究所 一种接触的制造方法以及具有该接触的半导体器件
JP6247551B2 (ja) * 2014-01-29 2017-12-13 新日本無線株式会社 半導体装置
KR102290538B1 (ko) 2015-04-16 2021-08-19 삼성전자주식회사 반도체 소자 및 이의 제조 방법

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0196142A (ja) * 1981-03-02 1989-04-14 Wako Pure Chem Ind Ltd 脂肪族ヨウ化物の製法
US4630357A (en) * 1985-08-02 1986-12-23 Ncr Corporation Method for forming improved contacts between interconnect layers of an integrated circuit
JPS62102559A (ja) * 1985-10-29 1987-05-13 Mitsubishi Electric Corp 半導体装置及び製造方法
US5084413A (en) * 1986-04-15 1992-01-28 Matsushita Electric Industrial Co., Ltd. Method for filling contact hole
KR900003618B1 (ko) * 1986-05-30 1990-05-26 후지쓰가부시끼가이샤 반도체장치 및 그 제조방법
US4782380A (en) * 1987-01-22 1988-11-01 Advanced Micro Devices, Inc. Multilayer interconnection for integrated circuit structure having two or more conductive metal layers
US4884123A (en) * 1987-02-19 1989-11-28 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
US4960732A (en) * 1987-02-19 1990-10-02 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
JPS63299251A (ja) * 1987-05-29 1988-12-06 Toshiba Corp 半導体装置の製造方法
US4994410A (en) * 1988-04-04 1991-02-19 Motorola, Inc. Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process
JPH01270347A (ja) * 1988-04-22 1989-10-27 Sony Corp 半導体装置
JPH0666287B2 (ja) * 1988-07-25 1994-08-24 富士通株式会社 半導体装置の製造方法
DE3915337A1 (de) * 1989-05-10 1990-11-15 Siemens Ag Verfahren zum herstellen einer niederohmigen planen kontaktmetallisierung fuer hochintegrierte halbleiterschaltungen
US5108951A (en) * 1990-11-05 1992-04-28 Sgs-Thomson Microelectronics, Inc. Method for forming a metal contact
US5472912A (en) * 1989-11-30 1995-12-05 Sgs-Thomson Microelectronics, Inc. Method of making an integrated circuit structure by using a non-conductive plug
JPH03201482A (ja) * 1989-12-28 1991-09-03 Mitsubishi Electric Corp 半導体装置及びその製造方法
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten
US5066612A (en) * 1990-01-05 1991-11-19 Fujitsu Limited Method of forming wiring of a semiconductor device
JPH0680638B2 (ja) * 1990-07-05 1994-10-12 株式会社東芝 半導体装置の製造方法
US5475266A (en) * 1992-02-24 1995-12-12 Texas Instruments Incorporated Structure for microelectronic device incorporating low resistivity straps between conductive regions
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias

Also Published As

Publication number Publication date
US5582971A (en) 1996-12-10
US5523624A (en) 1996-06-04
EP0558304A3 (en) 1994-05-18
JP3481965B2 (ja) 2003-12-22
DE69327600T2 (de) 2000-06-21
EP0558304B1 (de) 2000-01-19
EP0558304A2 (de) 1993-09-01
JPH0620986A (ja) 1994-01-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee