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DE60236994D1 - Halbleiterbauelement und dessen Herstellungsverfahren - Google Patents

Halbleiterbauelement und dessen Herstellungsverfahren

Info

Publication number
DE60236994D1
DE60236994D1 DE60236994T DE60236994T DE60236994D1 DE 60236994 D1 DE60236994 D1 DE 60236994D1 DE 60236994 T DE60236994 T DE 60236994T DE 60236994 T DE60236994 T DE 60236994T DE 60236994 D1 DE60236994 D1 DE 60236994D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor component
semiconductor
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60236994T
Other languages
English (en)
Inventor
Yukinobu Hikosaka
Akio Itoh
Kazuaki Takai
Takeyasu Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Application granted granted Critical
Publication of DE60236994D1 publication Critical patent/DE60236994D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE60236994T 2002-01-08 2002-08-14 Halbleiterbauelement und dessen Herstellungsverfahren Expired - Lifetime DE60236994D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002001675A JP4368085B2 (ja) 2002-01-08 2002-01-08 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE60236994D1 true DE60236994D1 (de) 2010-08-26

Family

ID=19190641

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60236994T Expired - Lifetime DE60236994D1 (de) 2002-01-08 2002-08-14 Halbleiterbauelement und dessen Herstellungsverfahren

Country Status (7)

Country Link
US (1) US6710422B2 (de)
EP (1) EP1326277B1 (de)
JP (1) JP4368085B2 (de)
KR (1) KR100851167B1 (de)
CN (1) CN1240133C (de)
DE (1) DE60236994D1 (de)
TW (1) TW552698B (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4901105B2 (ja) * 2003-04-15 2012-03-21 富士通セミコンダクター株式会社 半導体装置の製造方法
US7002196B2 (en) * 2003-11-13 2006-02-21 Infineon Technologies Ag Ferroelectric capacitor devices and FeRAM devices
JP2005191345A (ja) * 2003-12-26 2005-07-14 Nec Electronics Corp 半導体装置及びその製造方法
JP4803995B2 (ja) * 2004-06-28 2011-10-26 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP4785030B2 (ja) * 2005-01-18 2011-10-05 富士通セミコンダクター株式会社 半導体装置とその製造方法
JP2007073909A (ja) * 2005-09-09 2007-03-22 Oki Electric Ind Co Ltd 半導体メモリの製造方法
JP4809367B2 (ja) * 2005-12-02 2011-11-09 富士通セミコンダクター株式会社 半導体装置とその製造方法
KR100755673B1 (ko) * 2006-08-04 2007-09-05 삼성전자주식회사 반도체 소자 제조 방법 및 이에 따라 제조된 반도체 소자
JP2009130188A (ja) * 2007-11-26 2009-06-11 Seiko Epson Corp メモリ装置の製造方法
JP5875368B2 (ja) * 2011-12-28 2016-03-02 キヤノン株式会社 半導体装置の製造方法
CN106910708B (zh) * 2015-12-22 2020-06-19 中芯国际集成电路制造(上海)有限公司 具有局部互连结构的器件及其制造方法
CN109755245B (zh) * 2017-11-08 2020-12-01 华邦电子股份有限公司 存储器装置及其制造方法
KR20210090768A (ko) * 2020-01-10 2021-07-21 삼성전자주식회사 반도체 소자 및 이의 제조 방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09116123A (ja) * 1995-10-20 1997-05-02 Sony Corp 強誘電体不揮発性半導体記憶装置
JPH1022466A (ja) * 1996-03-01 1998-01-23 Motorola Inc 強誘電体不揮発性メモリ・セルおよびメモリ・セルの形成方法
DE19640246A1 (de) * 1996-09-30 1998-04-02 Siemens Ag Halbleiteranordnung mit geschützter Barriere für eine Stapelzelle
US5773314A (en) 1997-04-25 1998-06-30 Motorola, Inc. Plug protection process for use in the manufacture of embedded dynamic random access memory (DRAM) cells
JPH11150245A (ja) * 1997-11-18 1999-06-02 Nec Corp 半導体装置の製造方法
US6509601B1 (en) * 1998-07-31 2003-01-21 Samsung Electronics Co., Ltd. Semiconductor memory device having capacitor protection layer and method for manufacturing the same
JP2000307084A (ja) * 1999-04-23 2000-11-02 Hitachi Ltd 半導体集積回路装置およびその製造方法
TW454330B (en) 1999-05-26 2001-09-11 Matsushita Electronics Corp Semiconductor apparatus and its manufacturing method

Also Published As

Publication number Publication date
CN1431713A (zh) 2003-07-23
US6710422B2 (en) 2004-03-23
KR100851167B1 (ko) 2008-08-08
CN1240133C (zh) 2006-02-01
US20030127703A1 (en) 2003-07-10
EP1326277A3 (de) 2006-06-28
EP1326277B1 (de) 2010-07-14
JP2003204040A (ja) 2003-07-18
TW552698B (en) 2003-09-11
JP4368085B2 (ja) 2009-11-18
EP1326277A2 (de) 2003-07-09
KR20030060744A (ko) 2003-07-16

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE