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DE60207641D1 - Halbleiterspeicher, Informationsgerät und Verfahren zur Bestimmung von Speicherzugriffzeit des Halbleiterspeichers - Google Patents

Halbleiterspeicher, Informationsgerät und Verfahren zur Bestimmung von Speicherzugriffzeit des Halbleiterspeichers

Info

Publication number
DE60207641D1
DE60207641D1 DE60207641T DE60207641T DE60207641D1 DE 60207641 D1 DE60207641 D1 DE 60207641D1 DE 60207641 T DE60207641 T DE 60207641T DE 60207641 T DE60207641 T DE 60207641T DE 60207641 D1 DE60207641 D1 DE 60207641D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory
access time
information device
determining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60207641T
Other languages
English (en)
Other versions
DE60207641T2 (de
Inventor
Ken Sumitani
Haruyasu Fukui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE60207641D1 publication Critical patent/DE60207641D1/de
Publication of DE60207641T2 publication Critical patent/DE60207641T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
DE60207641T 2001-06-28 2002-06-27 Halbleiterspeicher, Informationsgerät und Verfahren zur Bestimmung von Speicherzugriffzeit des Halbleiterspeichers Expired - Lifetime DE60207641T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001197537A JP2003015954A (ja) 2001-06-28 2001-06-28 半導体記憶装置および情報機器、半導体記憶装置のアクセス期間設定方法
JP2001197537 2001-06-28

Publications (2)

Publication Number Publication Date
DE60207641D1 true DE60207641D1 (de) 2006-01-05
DE60207641T2 DE60207641T2 (de) 2006-08-03

Family

ID=19035125

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60207641T Expired - Lifetime DE60207641T2 (de) 2001-06-28 2002-06-27 Halbleiterspeicher, Informationsgerät und Verfahren zur Bestimmung von Speicherzugriffzeit des Halbleiterspeichers

Country Status (6)

Country Link
US (1) US6785185B2 (de)
EP (1) EP1271540B1 (de)
JP (1) JP2003015954A (de)
KR (1) KR100458699B1 (de)
DE (1) DE60207641T2 (de)
TW (1) TW573249B (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6829195B2 (en) * 2001-03-22 2004-12-07 Fujitsu Limited Semiconductor memory device and information processing system
GB0123416D0 (en) * 2001-09-28 2001-11-21 Memquest Ltd Non-volatile memory control
US7613880B2 (en) 2002-11-28 2009-11-03 Renesas Technology Corp. Memory module, memory system, and information device
KR100609623B1 (ko) 2005-02-16 2006-08-08 삼성전자주식회사 내부 메모리 디바이스간의 직접적 데이터 이동이 가능한 복합 메모리 칩 및 데이터 이동방법
US8099608B2 (en) 2005-05-09 2012-01-17 The Invention Science Fund I, Llc Limited use data storing device
US8462605B2 (en) * 2005-05-09 2013-06-11 The Invention Science Fund I, Llc Method of manufacturing a limited use data storing device
US9396752B2 (en) 2005-08-05 2016-07-19 Searete Llc Memory device activation and deactivation
US20110181981A1 (en) * 2005-05-09 2011-07-28 Searete Llc, A Limited Liability Corporation Of The State Of Delaware Method and system for rotational control of data storage devices
US7565596B2 (en) * 2005-09-09 2009-07-21 Searete Llc Data recovery systems
US8275949B2 (en) * 2005-12-13 2012-09-25 International Business Machines Corporation System support storage and computer system
US8264928B2 (en) * 2006-06-19 2012-09-11 The Invention Science Fund I, Llc Method and system for fluid mediated disk activation and deactivation
JP2008010070A (ja) * 2006-06-29 2008-01-17 Toshiba Corp 半導体記憶装置
JP2008047244A (ja) * 2006-08-18 2008-02-28 Toshiba Corp 半導体記憶装置、半導体装置、及びデータ書き込み方法
JP5062251B2 (ja) 2007-03-28 2012-10-31 富士通株式会社 可変抵抗メモリ及びそのデータ書込み方法
JP5823097B2 (ja) * 2010-04-28 2015-11-25 ブラザー工業株式会社 電子回路、画像形成装置およびｄｄｒ−ｓｄｒａｍの初期化方法
TWI479491B (zh) * 2011-07-05 2015-04-01 Phison Electronics Corp 記憶體控制方法、記憶體控制器與記憶體儲存裝置
KR102025263B1 (ko) 2012-10-05 2019-09-25 삼성전자주식회사 메모리 시스템 및 그것의 읽기 교정 방법
US11086534B2 (en) * 2018-06-28 2021-08-10 Apple Inc. Memory data distribution based on communication channel utilization

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317183A (en) * 1979-12-11 1982-02-23 Casio Computer Co., Ltd. Unused program number indicating system for a small program type electronic calculator
JP2750704B2 (ja) 1988-08-29 1998-05-13 日立マクセル株式会社 Ｉｃカードの情報書込み方式及びｉｃカード
US5031146A (en) * 1988-12-22 1991-07-09 Digital Equipment Corporation Memory apparatus for multiple processor systems
JP3061836B2 (ja) 1990-05-22 2000-07-10 日本電気株式会社 メモリ装置
JPH06195258A (ja) * 1992-07-08 1994-07-15 Nec Corp 半導体記憶装置
JP3479385B2 (ja) * 1995-06-29 2003-12-15 東芝マイクロエレクトロニクス株式会社 情報処理装置
JP2859178B2 (ja) * 1995-09-12 1999-02-17 日本電気通信システム株式会社 プロセッサ間データ転送方式及びプロセッサ間データ転送用リングバッファメモリ
EP0784301B1 (de) * 1996-01-08 2002-10-16 Jürgen Dethloff Verfahren und System zum Bezahlen von Leistungen sowie tragbarer Datenträger für ein derartiges System
KR100189530B1 (ko) * 1996-05-21 1999-06-01 윤종용 마이크로 프로세서와 메모리간의 데이타 인터페이스 방법
EP0818749A3 (de) * 1996-07-12 1999-05-12 Jürgen Dethloff Verfahren und System zum Sichern von Daten
US6418506B1 (en) 1996-12-31 2002-07-09 Intel Corporation Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array
US6502149B2 (en) * 1997-12-23 2002-12-31 Emc Corporation Plural bus data storage system
US5943287A (en) * 1998-03-31 1999-08-24 Emc Corporation Fault tolerant memory system
JP2000298614A (ja) 1999-04-15 2000-10-24 Sony Corp メモリインタフェースおよびデータ処理装置
JP3871184B2 (ja) 2000-06-12 2007-01-24 シャープ株式会社 半導体記憶装置

Also Published As

Publication number Publication date
DE60207641T2 (de) 2006-08-03
EP1271540B1 (de) 2005-11-30
EP1271540A3 (de) 2003-04-02
JP2003015954A (ja) 2003-01-17
US20030002377A1 (en) 2003-01-02
US6785185B2 (en) 2004-08-31
KR20030003092A (ko) 2003-01-09
TW573249B (en) 2004-01-21
KR100458699B1 (ko) 2004-12-03
EP1271540A2 (de) 2003-01-02

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Legal Events

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8364 No opposition during term of opposition