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DE60127402D1 - Verfahren zur herstellung von substraten und dadurch hergestellte substrate - Google Patents

Verfahren zur herstellung von substraten und dadurch hergestellte substrate

Info

Publication number
DE60127402D1
DE60127402D1 DE60127402T DE60127402T DE60127402D1 DE 60127402 D1 DE60127402 D1 DE 60127402D1 DE 60127402 T DE60127402 T DE 60127402T DE 60127402 T DE60127402 T DE 60127402T DE 60127402 D1 DE60127402 D1 DE 60127402D1
Authority
DE
Germany
Prior art keywords
layer
substrates
bonding
amorphous
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60127402T
Other languages
English (en)
Other versions
DE60127402T2 (de
Inventor
Andre Auberton-Herve
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Application granted granted Critical
Publication of DE60127402D1 publication Critical patent/DE60127402D1/de
Publication of DE60127402T2 publication Critical patent/DE60127402T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers

Landscapes

  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Vapour Deposition (AREA)
  • Photovoltaic Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Liquid Crystal (AREA)
  • Optical Integrated Circuits (AREA)
  • Laminated Bodies (AREA)
DE60127402T 2000-06-16 2001-06-15 Verfahren zur herstellung von substraten und dadurch hergestellte substrate Expired - Lifetime DE60127402T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0007755 2000-06-16
FR0007755A FR2810448B1 (fr) 2000-06-16 2000-06-16 Procede de fabrication de substrats et substrats obtenus par ce procede
PCT/FR2001/001876 WO2001097282A1 (fr) 2000-06-16 2001-06-15 Procede de fabrication de substrats et substrats obtenus par ce procede

Publications (2)

Publication Number Publication Date
DE60127402D1 true DE60127402D1 (de) 2007-05-03
DE60127402T2 DE60127402T2 (de) 2007-11-29

Family

ID=8851376

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60127402T Expired - Lifetime DE60127402T2 (de) 2000-06-16 2001-06-15 Verfahren zur herstellung von substraten und dadurch hergestellte substrate

Country Status (11)

Country Link
US (2) US6936482B2 (de)
EP (1) EP1292975B1 (de)
JP (2) JP5374006B2 (de)
KR (1) KR100738145B1 (de)
CN (1) CN100349278C (de)
AT (1) ATE357740T1 (de)
AU (1) AU6767601A (de)
DE (1) DE60127402T2 (de)
FR (1) FR2810448B1 (de)
TW (1) TWI266359B (de)
WO (1) WO2001097282A1 (de)

Families Citing this family (58)

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FR2855650B1 (fr) * 2003-05-30 2006-03-03 Soitec Silicon On Insulator Substrats pour systemes contraints et procede de croissance cristalline sur un tel substrat
FR2856192B1 (fr) * 2003-06-11 2005-07-29 Soitec Silicon On Insulator Procede de realisation de structure heterogene et structure obtenue par un tel procede
US6982210B2 (en) 2003-07-10 2006-01-03 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for manufacturing a multilayer semiconductor structure that includes an irregular layer
KR20060118437A (ko) * 2003-09-26 2006-11-23 위니베르시트카솔리끄드루뱅 저항손을 감소시키는 다층 반도체 구조의 제조 방법
FR2860341B1 (fr) * 2003-09-26 2005-12-30 Soitec Silicon On Insulator Procede de fabrication de structure multicouche a pertes diminuees
FR2864336B1 (fr) * 2003-12-23 2006-04-28 Commissariat Energie Atomique Procede de scellement de deux plaques avec formation d'un contact ohmique entre celles-ci
FR2866983B1 (fr) * 2004-03-01 2006-05-26 Soitec Silicon On Insulator Realisation d'une entite en materiau semiconducteur sur substrat
EP1571705A3 (de) * 2004-03-01 2006-01-04 S.O.I.Tec Silicon on Insulator Technologies Verfahren zur Herstellung einer Hableiterstruktur auf einem Substrat
FR2872627B1 (fr) * 2004-06-30 2006-08-18 Commissariat Energie Atomique Assemblage par adhesion moleculaire de deux substrats
WO2006037783A1 (fr) * 2004-10-04 2006-04-13 S.O.I.Tec Silicon On Insulator Technologies Procédé de transfert d'une couche mince comprenant une perturbation controlée d'une structure cristalline
US7560322B2 (en) * 2004-10-27 2009-07-14 Northrop Grumman Systems Corporation Method of making a semiconductor structure for high power semiconductor devices
US10374120B2 (en) * 2005-02-18 2019-08-06 Koninklijke Philips N.V. High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
US8101498B2 (en) * 2005-04-21 2012-01-24 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US7462552B2 (en) * 2005-05-23 2008-12-09 Ziptronix, Inc. Method of detachable direct bonding at low temperatures
US7420226B2 (en) * 2005-06-17 2008-09-02 Northrop Grumman Corporation Method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates
DE102006007293B4 (de) * 2006-01-31 2023-04-06 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zum Herstellen eines Quasi-Substratwafers und ein unter Verwendung eines solchen Quasi-Substratwafers hergestellter Halbleiterkörper
US20070243703A1 (en) * 2006-04-14 2007-10-18 Aonex Technololgies, Inc. Processes and structures for epitaxial growth on laminate substrates
TW200802544A (en) * 2006-04-25 2008-01-01 Osram Opto Semiconductors Gmbh Composite substrate and method for making the same
US7732301B1 (en) 2007-04-20 2010-06-08 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
FR2933234B1 (fr) * 2008-06-30 2016-09-23 S O I Tec Silicon On Insulator Tech Substrat bon marche a structure double et procede de fabrication associe
FR2933233B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
FR2933235B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat bon marche et procede de fabrication associe
KR101548173B1 (ko) * 2008-09-18 2015-08-31 삼성전자주식회사 실리콘 다이렉트 본딩(ｓｄｂ)을 이용한 임시 웨이퍼 임시 본딩 방법, 및 그 본딩 방법을 이용한 반도체 소자 및 반도체 소자 제조 방법
FR2940520B1 (fr) * 2008-12-22 2011-03-18 Tile S Structure semiconductrice
SA110310235B1 (ar) 2009-03-31 2014-03-03 بيكر هوغيس انكوربوريتد طرق لترابط مناضد التقطيع مسبقة التشكيل بركائز عامل القطع وعامل القطع المكونة بهذه العمليات
US8267204B2 (en) * 2009-08-11 2012-09-18 Baker Hughes Incorporated Methods of forming polycrystalline diamond cutting elements, cutting elements, and earth-boring tools carrying cutting elements
US8536021B2 (en) 2010-12-24 2013-09-17 Io Semiconductor, Inc. Trap rich layer formation techniques for semiconductor devices
US9754860B2 (en) 2010-12-24 2017-09-05 Qualcomm Incorporated Redistribution layer contacting first wafer through second wafer
US8481405B2 (en) 2010-12-24 2013-07-09 Io Semiconductor, Inc. Trap rich layer with through-silicon-vias in semiconductor devices
US9624096B2 (en) 2010-12-24 2017-04-18 Qualcomm Incorporated Forming semiconductor structure with device layers and TRL
US9553013B2 (en) * 2010-12-24 2017-01-24 Qualcomm Incorporated Semiconductor structure with TRL and handle wafer cavities
CN103348473B (zh) 2010-12-24 2016-04-06 斯兰纳半导体美国股份有限公司 用于半导体装置的富陷阱层
CN102769033B (zh) * 2011-05-05 2015-04-08 中国科学院微电子研究所 具有高击穿电压的hemt及其制造方法
PL2534996T3 (pl) * 2011-06-16 2015-10-30 Electrolux Home Products Corp Nv Urządzenie gospodarstwa domowego i sposób
FR2983342B1 (fr) * 2011-11-30 2016-05-20 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure limitant la formation de defauts et heterostructure ainsi obtenue
CN102543834A (zh) * 2012-02-14 2012-07-04 上海先进半导体制造股份有限公司 绝缘层上的半导体结构及其制造方法
JP6061251B2 (ja) * 2013-07-05 2017-01-18 株式会社豊田自動織機 半導体基板の製造方法
WO2015125770A1 (ja) * 2014-02-18 2015-08-27 日本碍子株式会社 半導体用複合基板のハンドル基板および半導体用複合基板
EP3479854A1 (de) 2014-04-15 2019-05-08 Tc1 Llc Katheterpumpe mit zugangsports
JP6156252B2 (ja) * 2014-05-16 2017-07-05 株式会社豊田自動織機 半導体基板の製造方法および半導体基板
JP6152827B2 (ja) * 2014-05-16 2017-06-28 株式会社豊田自動織機 半導体基板の製造方法
WO2016006663A1 (ja) 2014-07-10 2016-01-14 株式会社豊田自動織機 半導体基板および半導体基板の製造方法
CN107484431B (zh) 2015-03-04 2018-10-02 有限会社Ｍｔｅｃ 半导体基板的制造方法
WO2016149113A1 (en) * 2015-03-17 2016-09-22 Sunedison Semiconductor Limited Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures
CN105140107B (zh) * 2015-08-25 2019-03-29 上海新傲科技股份有限公司 带有电荷陷阱和绝缘埋层衬底的制备方法
FR3076292B1 (fr) * 2017-12-28 2020-01-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de transfert d'une couche utile sur un substrat support
JP2019210162A (ja) 2018-05-31 2019-12-12 ローム株式会社 半導体基板構造体及びパワー半導体装置
FR3098985B1 (fr) * 2019-07-15 2022-04-08 Soitec Silicon On Insulator Procédé de collage hydrophile de substrats
FR3118828B1 (fr) * 2021-01-14 2023-10-27 Commissariat Energie Atomique Procédé de collage direct de substrats
FR3127330B1 (fr) * 2021-09-22 2023-09-22 Soitec Silicon On Insulator Procede de fabrication d’un substrat support en carbure de silicium poly-cristallin
FR3127842B1 (fr) * 2021-10-05 2024-08-02 Soitec Silicon On Insulator Structure composite comprenant une couche utile en sic monocristallin sur un substrat support en sic poly-cristallin et procede de fabrication de ladite structure
FR3127843B1 (fr) * 2021-10-05 2023-09-08 Soitec Silicon On Insulator ProcÉdÉ de transfert d’une couche de SiC monocristallin sur un support en SiC polycristallin utilisant une couche intermÉdiaire de SiC polycristallin
FR3128056B1 (fr) * 2021-10-07 2023-10-27 Soitec Silicon On Insulator Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic poly-cristallin
US20250006492A1 (en) * 2021-10-07 2025-01-02 Soitec Method for manufacturing a composite structure comprising a thin film of monocrystalline sic on a carrier substrate of polycrystalline sic
JP2024130800A (ja) * 2023-03-15 2024-09-30 信越半導体株式会社 半導体基板の製造方法、半導体基板、及び半導体装置
JP2025084380A (ja) * 2023-11-22 2025-06-03 住友金属鉱山株式会社 接合半導体基板および接合半導体基板の製造方法
JP2025084381A (ja) * 2023-11-22 2025-06-03 住友金属鉱山株式会社 接合半導体基板および接合半導体基板の製造方法

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Also Published As

Publication number Publication date
DE60127402T2 (de) 2007-11-29
US6936482B2 (en) 2005-08-30
AU6767601A (en) 2001-12-24
JP2004503942A (ja) 2004-02-05
US20030129780A1 (en) 2003-07-10
JP5461593B2 (ja) 2014-04-02
KR20030047900A (ko) 2003-06-18
CN1436369A (zh) 2003-08-13
JP5374006B2 (ja) 2013-12-25
WO2001097282A1 (fr) 2001-12-20
FR2810448A1 (fr) 2001-12-21
TWI266359B (en) 2006-11-11
EP1292975A1 (de) 2003-03-19
JP2012099848A (ja) 2012-05-24
CN100349278C (zh) 2007-11-14
EP1292975B1 (de) 2007-03-21
US20050151155A1 (en) 2005-07-14
ATE357740T1 (de) 2007-04-15
KR100738145B1 (ko) 2007-07-10
FR2810448B1 (fr) 2003-09-19
US7221038B2 (en) 2007-05-22
WO2001097282B1 (fr) 2002-03-07

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