CN221979451U - Chip packaging structure of memory and memory device - Google Patents

Abstract

The utility model discloses a memory chip packaging structure and a storage device, wherein the chip packaging structure comprises a first substrate, a second substrate and a flexible connection board, the first substrate and the second substrate are electrically connected through the flexible connection board, the first substrate is a rigid substrate, and a plurality of chip devices are arranged on the side of the first substrate facing the second substrate. The memory chip packaging structure of the utility model effectively saves the layout area of the chip packaging structure, realizes the miniaturization of the high-sealing package, and effectively reduces the inductance of the bonding wire interconnection line.

Description

Chip packaging structure of memory and storage device

Technical Field

The utility model relates to the technical field of chip packaging and testing, and in particular to a chip packaging structure of a memory and a storage device using the chip packaging structure.

Background Art

As people's living standards continue to improve, their requirements for material life are also increasing. Electronic products, as an important part of people's material life, also need to change to meet people's different requirements, such as lighter and thinner. This poses a challenge to the technology of microelectronic packaging in electronic products.

Multi-chip stacking technology is a basic technology used in three-dimensional packaging of memory. Multi-chip stacking technology affects the integration level of multiple components of electronic products, thereby directly or indirectly affecting the size of electronic products. The carrier using multi-chip stacking technology is usually a packaging substrate, which can provide electrical connection, protection, support, heat dissipation and other functions for the chip.

In the existing memory chip packaging structure, the packaging carrier is generally a rigid substrate, and a variety of chip devices are arranged between at least two rigid substrates. The two rigid substrates are interconnected by bonding wires. The bonding wires have a small wire diameter and a large inductance, which can easily affect the integrity of the power supply and signal.

Utility Model Content

The main purpose of the utility model is to propose a chip packaging structure of a memory, aiming to solve the technical problem that in the chip packaging structure of the memory in the prior art, two rigid substrates are interconnected by bonding wires, the bonding wires have a small wire diameter and a large inductance, which easily affects the integrity of the power supply and the signal.

To achieve the above object, the utility model provides a memory chip packaging structure, comprising a first substrate, a second substrate and a flexible connecting board, wherein:

The first substrate is electrically connected to the second substrate through the flexible connecting board. The first substrate is a rigid substrate. A plurality of chip devices are arranged on a side of the first substrate facing the second substrate.

In some embodiments, the second substrate is electrically connected to the adjacent chip devices.

In some embodiments, the second substrate is connected to the adjacent chip device via bonding wires.

In some embodiments, a FOW layer is disposed on a side of the chip device adjacent to the second substrate away from the second substrate.

In some embodiments, a redistribution layer is provided on a side of the chip device adjacent to the second substrate close to the second substrate, and the second substrate is electrically connected to the chip device through the redistribution layer.

In some embodiments, the chip device has a through hole, and the second substrate is electrically connected to the chip device through the through hole.

The second substrate is a flexible substrate, and the flexible connecting plate is integrally formed with the second substrate.

In some embodiments, the chip device fans out signals via SMT reflow soldering.

In some embodiments, the chip device bonds the fan-out signal by gold wire bonding technology.

Furthermore, the utility model also provides a storage device, comprising the chip packaging structure of the memory described above.

In the scheme of the utility model, through the arrangement of the first substrate, the second substrate and the flexible connecting board, a plurality of chip devices are vertically stacked and arranged on the side of the first substrate facing the second substrate. This arrangement replaces the arrangement of the traditional flat chip package. The chip devices vertically stacked on the first substrate occupy less plane space than the arrangement of the chip devices flat on the first substrate, saving a lot of plane space. The high sealing and miniaturization of the chip package are achieved, and the first substrate and the second substrate are electrically interconnected by using a flexible circuit board instead of the original bonding wire. The chip packaging structure of the memory of the utility model effectively reduces the line inductance of the bonding wire interconnecting the two, and effectively protects the integrity of the power supply and signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of a chip packaging structure of a memory in an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a chip packaging structure of a memory in yet another embodiment of the present invention.

The purpose, features and advantages of the present invention will be further described in conjunction with the embodiments and with reference to the accompanying drawings.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

1 and 2 , the present invention provides a memory chip packaging structure, including a first substrate 1, a second substrate 2 and a flexible connecting board 3, wherein:

The first substrate 1 is electrically connected to the second substrate 2 via a flexible connecting plate 3. The first substrate 1 is a rigid substrate. A plurality of chip devices 4 are arranged on a side of the first substrate 1 facing the second substrate.

In this embodiment, the first substrate 1 in the chip packaging structure is a rigid substrate, and a plurality of chip devices 4 are stacked on the first substrate 1 in the vertical direction. The first substrate 1 serves as a base and carries a plurality of chip devices 4. The second substrate 2 is spaced apart from the first substrate 1 in the vertical direction, and a plurality of chip devices 4 are stacked between the first substrate 1 and the second substrate 2. The first substrate 1 and the second substrate 2 are electrically interconnected through a flexible connection board 3. The first substrate 1, the second substrate 2 and the flexible connection board 3 are physically connected and connected in circuit. The flexible connection board 3 is connected to one side of the first substrate 1, and the position where it is connected to the second substrate 2 is the same side as the side connected to the first substrate 1.

In some embodiments, the second substrate 2 may also be disposed between a plurality of chip devices 4 stacked on the first substrate 1 along the vertical direction.

In some embodiments, the number of circuit layers of the first substrate 1 , the second substrate 2 , and the flexible connecting board 3 is not limited.

In some embodiments, the number of stacked layers of the chip device 4 is not limited, and the flexible connecting board 3 is arranged according to the number of stacked layers of the chip device 4 to achieve the effect of connecting the first substrate 1 and the second substrate 2 .

In some embodiments, the second substrate, the flexible connecting board, and the peripheral sides of the chip device proposed in the embodiments of the present utility model are filled with plastic packaging materials.

In some embodiments, the molding materials provided in the embodiments of the present invention include but are not limited to the following: epoxy resin, silicone resin and polyimide resin.

Except for the bottom of the first substrate 1, the plastic encapsulation material should wrap the second substrate, the flexible connecting board, and the chip device in Figure 1 or 2. The plastic encapsulation material is a sealing packaging material for the chip, and the purpose is to protect the chip from particles (particles or microparticles) or chemical pollution in the external environment; the plastic encapsulation material has a good electrical insulation effect, and the plastic encapsulation material can provide good electrical insulation performance to prevent short circuits in the conductive parts of the chip device 4; some plastic encapsulation materials can provide a certain anti-breakthrough effect to improve the anti-breakthrough voltage strength of the package; some plastic encapsulation materials can provide heat dissipation performance for the chip device 4. Since the plastic encapsulation material has good thermal conductivity, it can help the chip device 4 to dissipate heat well; the plastic encapsulation material can also provide a certain mechanical support strength for the chip device 4; some plastic encapsulation materials have good corrosion resistance, and the use of highly corrosion-resistant plastic encapsulation materials can increase the service life of the package.

It should be noted that epoxy resin is a widely used chip-level packaging material with good processing performance, low cost, excellent moisture resistance and insulation properties; silicone resin is used for packaging products with high environmental protection and heat resistance requirements, with good insulation and high temperature resistance; polyimide resin is a packaging product used for high-frequency and high-speed digital products, with excellent dielectric properties, good high-frequency signal integrity, and can also be used as a bonding layer.

The chip packaging structure of the utility model is provided with a first substrate 1, a second substrate 2 and a flexible connecting board 3, and a plurality of chip devices 4 are stacked and arranged on the side of the first substrate 1 facing the second substrate. This arrangement replaces the traditional arrangement of flat chip packaging. The chip devices 4 stacked vertically on the first substrate 1 occupy less plane space than the arrangement of the chip devices 4 flat on the first substrate 1, saving a lot of plane space. High sealing and miniaturization of chip packaging are achieved, and the first substrate 1 and the second substrate 2 are electrically interconnected by using a flexible circuit board instead of the original bonding wire, which effectively reduces the line inductance of the bonding wire interconnecting the two, and effectively protects the integrity of the power supply and signal.

In some embodiments, the second substrate provided in the embodiments of the present invention is electrically connected to the adjacent chip device.

In this embodiment, the second substrate 2 is electrically connected to the adjacent chip device 4. The second substrate 2 can lead the electrical signals inside the chip device 4 to the outside, thereby realizing the connection and interaction between the chip device 4 and the external circuit.

The conductive wiring on the second substrate 2 can redistribute the high-density layout of the pads inside the chip device 4 to achieve a fan-out effect. The second substrate 2 may also carry some key circuits that control the operation of the chip device 4. The electrical connection allows the chip device 4 to receive control signals.

In some embodiments, the second substrate also carries power conversion and regulation circuits required for the operation of the chip device 4. Electrical connection is also indispensable for power transmission.

In summary, in order to ensure the realization of functions such as signal extraction, circuit control and power supply, stable electrical connection between the second substrate 2 and the chip device 4 is a basic requirement of the packaging structure.

1 and 2 , in some embodiments, the second substrate 2 provided in the embodiments of the present invention is connected to the adjacent chip device 4 via bonding wires.

In this embodiment, the bonding wire connection can be achieved by laying out a fan-out wire at the wire output pad position of the chip device 4 and ultrasonically welding it to the chip pad; laying out a matching stud pad in the corresponding area of the second substrate 2 for subsequent welding with the fan-out wire; using a metal bonding wire, one end is brazed with the fan-out wire pad on the chip device 4, and the other end is brazed with the pad on the second substrate 2; each chip wire is connected in turn through a bonding wire process; after processing, post-processing such as removing the oxide layer and drilling holes is performed to improve the reliability of the wire connection.

The second substrate 2 and the adjacent chip device 4 can also be electrically connected by solder ball connection. Specifically, the solder ball connection is as follows: a through hole is opened at the position of the lead-out pad of the chip device 4, and a UDL (microball bottom layer) and a UBM (passivation layer) are deposited to form a copper pad after surface treatment;

A mask is placed in the corresponding area of the second substrate 2, the groove position matches the pad, and then a nickel/gold layer is electroplated;

Flip the chip over and place it on the second substrate 2, and use a machine vision system to accurately align the chip;

After hot pressing welding in the reflow oven, the solder balls and the solder pads of the second substrate 2 are reliably electrically connected;

Remove the hot press plate and perform electrical testing to confirm the quality of solder ball connection;

Inject and cure underfill compound to improve connection reliability;

The chip is packaged and the solder ball electrical connection process between the chip and the second substrate 2 is completed.

2 , in some embodiments, a FOW layer is disposed on a side of the chip device 4 adjacent to the second substrate 2 away from the second substrate 2 according to the embodiment of the present invention.

In this embodiment, the FOW layer refers to the film over wire layer, which is a thin film flip packaging technology on a chip. The specific operation of setting the FOW layer is: preparing a filter membrane layer on the electrode pad side of the chip device 4, and the filter membrane layer contains a redistribution circuit layer surrounding the pad;

depositing spacer solder balls on the filter membrane layer;

Turn the chip device 4 over, with the solder balls facing downward, and aligning them with the solder pads on the second substrate;

Perform hot pressing welding, and the redistribution circuit in the filter membrane layer realizes the fan-out connection from the chip device 4 pads to the solder balls;

After the film flipping process is completed, the filter membrane layer plays the role of fan-out connection and chip device 4 protection.

Packaging and testing complete the production of the fan-out line layer.

In some embodiments, referring to FIG2 , a wirebond die refers to a bare chip that is packaged and connected using a gold wire bonding technique. It should be noted that the wirebond die layer is a bare chip that is not sealed and protected, and then the chip surface pads are electrically connected to the second substrate 2 using a gold wire.

1 , in some embodiments, a redistribution layer is provided on a side of the chip device 4 adjacent to the second substrate 2 close to the second substrate 2 proposed in the embodiment of the utility model, and the second substrate 2 is electrically connected to the chip device 4 through the redistribution layer.

In this embodiment, the fan-out and rewiring of the surface pads of the chip device 4 can use the redistribution wiring layer (Redistribution Layer) process, referred to as the RDL process. The RDL process can be used to prepare the chip surface pads for bonding wire connections. Specifically, the RDL layer is laser drilled to form pads, and then solder balls are welded to facilitate subsequent bonding wire connections; the RDL process realizes the fan-out and rewiring of the chip surface pads, which matches the fan-out pad position of the gold wire bonding, so that the high-density chip can be reliably connected to the low-density carrier. After adopting the RDL process, the size gap between the chip and the carrier can be reduced, which is conducive to reducing the length of the bonding wire and increasing the line speed. The RDL process can also be made on a wire frame type carrier, replacing the metal frame, and bonding with the chip to achieve electrical connection. In general, the RDL process is conducive to optimizing the bonding wire connection and realizing reliable interconnection between high-density chips and carriers by changing the pad layout.

The chip device has a through hole, and the second substrate is electrically connected to the chip device through the through hole.

In this embodiment, a through hole is provided so that the second substrate is electrically connected to the chip device through the through hole, which can be called a through silicon via vertical interconnection technology connection, specifically: a through hole penetrating silicon is etched in the area corresponding to the chip device 4, directly reaching the copper pad inside the chip device 4;

An electrical insulating layer is formed on the sidewalls of the through-hole by thermal oxidation, and then a conductive seed layer is deposited according to standard processes;

Surface flattening technology is used to form conductive pads that fill TSVs to achieve vertical conductive paths;

Constructing a small-scale redistribution wiring at the TSV exit position of the chip device 4, electrically connected to the TSV;

Arrange pads on the second substrate 2 corresponding to the TSV array;

The chip device 4 is turned over and placed on the second substrate 2, and hot-pressed and welded after precise alignment;

The TSV forms a reliable metal diffusion bond with the second substrate pad, thereby achieving high-density electrical connection of the chip device 4 .

In some embodiments, the second substrate provided in the embodiments of the present invention is a flexible substrate, and the flexible connecting plate and the second substrate are integrally formed.

In this embodiment, when the second substrate 2 is a flexible substrate, the flexible connecting plate 3 and the second substrate 2 can be an integrated substrate, further simplifying the arrangement structure of the chip packaging structure of the utility model. When the flexible connecting plate 3 and the second substrate 2 are integrated, the second substrate 2 can be arranged between any stacked chip devices 4.

In some embodiments, the chip device 4 provided in the embodiments of the present invention fans out signals through SMT reflow soldering.

In this embodiment, the specific operation of the SMT (surface mount technology) reflow soldering fan-out signal is as follows: arranging the outgoing pins on the pads of the chip device 4, performing pattern design, and matching the pad layout on the PCB (printed circuit board);

Place the chip device 4 on the PCB board and dispense glue using a dispensing robot;

Transported to the reflow oven, and goes through the process curve of preheating, reflow and cooling;

The chip device 4 pads and the PCB board pads complete the surface mount (SMT) fusion welding to achieve electrical connection;

Conduct electrical testing to verify the connection quality between the chip device 4 alkaline pins and the PCB fan-out lines.

After cleaning and drying, impurities in the welding process are removed.

The surface mounting welding of the chip device 4 is completed to realize the electrical connection of the fan-out leads.

In some embodiments, the chip device 4 provided in the embodiments of the present invention bonds the fan-out signal through gold wire bonding technology.

In this embodiment, the specific operation of bonding the fan-out signal of the chip device 4 through the gold wire bonding technology (Wirebond) is as follows: opening a through hole at the pad position of the chip device 4 to expose the copper pad inside the chip;

Prepare the lead frame and pre-plating the surface with nickel/gold to improve the adhesion of the bonding wire;

Place the chip on the lead frame, aligning the pads with the pins of the lead frame;

Ultrasonic metal bonding is used to connect the chip pads to the lead frame pins using metal microwires;

Solder the bonding wires one pad at a time to form fan-out leads;

Conduct electrical testing to confirm the electrical performance of the bond wire connections;

Packaging and moisture-proofing complete the gold wire bonding between the chip device 4 and the lead frame.

In some embodiments, the utility model further proposes a storage device, including the chip packaging structure of the memory described in the aforementioned embodiments. The specific structure of the chip packaging structure of the memory refers to the aforementioned embodiments. Since the storage device adopts all the technical solutions of all the aforementioned embodiments, it at least has all the technical effects brought by the technical solutions of the aforementioned embodiments, which will not be described one by one here.

The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct/indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims (10)

1. The chip packaging structure of the memory is characterized by comprising a first substrate, a second substrate and a flexible connecting plate, wherein:

The first substrate and the second substrate are electrically connected through the flexible connecting plate, the first substrate is a rigid substrate, and a plurality of chip devices are arranged on one side of the first substrate, which faces the second substrate.

2. The chip package structure of claim 1, wherein the second substrate is electrically connected to the adjacent chip device.

3. The chip package structure of a memory according to claim 2, wherein the second substrate is connected to the adjacent chip device by a bonding wire.

4. A chip package structure of a memory according to claim 3, wherein a side of the chip device adjacent to the second substrate remote from the second substrate is provided with a FOW layer.

5. The chip package structure of a memory according to claim 3, wherein a rewiring layer is provided on a side of the chip device adjacent to the second substrate, which is adjacent to the second substrate, the second substrate being electrically connected to the chip device through the rewiring layer.

6. The chip package structure of a memory according to claim 2, wherein the chip device has a via hole thereon, and the second substrate is electrically connected to the chip device through the via hole.

7. The memory chip package structure of claim 2, wherein the second substrate is a flexible substrate, and the flexible connection board is integrally formed with the second substrate.

8. The chip package structure of the memory of claim 1, wherein the chip device is attached with fan-out signals by SMT reflow soldering.

9. The chip package structure of the memory of claim 1, wherein the chip device bonds the fan-out signal by a gold wire bonding technique.

10. A memory device characterized by a chip package structure comprising the memory according to any one of claims 1 to 9.