CN221947145U - Packaging structure and electronic equipment - Google Patents
Packaging structure and electronic equipment Download PDFInfo
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- CN221947145U CN221947145U CN202420537490.8U CN202420537490U CN221947145U CN 221947145 U CN221947145 U CN 221947145U CN 202420537490 U CN202420537490 U CN 202420537490U CN 221947145 U CN221947145 U CN 221947145U
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Abstract
The utility model discloses a packaging structure and electronic equipment, the packaging structure comprises a substrate and a packaging tube shell, at least a first chip, a first anisotropic conductive film and a first flexible circuit board are arranged between the substrate and the packaging tube shell, the lower surface of the substrate is a first plate surface, the upper surface of the substrate is a second plate surface, the first plate surface is fixedly provided with a plurality of first bonding pads, the first chip is fixedly arranged on the second plate surface, the substrate is respectively and electrically connected with the first chip and the first bonding pads, the upper end of the first chip is provided with a plurality of second bonding pads, the upper end of the second bonding pads is bonded with the first anisotropic conductive film, the upper end of the first anisotropic conductive film is provided with the first flexible circuit board, a plurality of third bonding pads are arranged between the first anisotropic conductive film and the first flexible circuit board, and the first anisotropic conductive film is respectively and electrically connected with the second bonding pads and the third bonding pads along the vertical direction; the utility model can increase the contact area between the electrode leading-out part and the chip and improve the heat dissipation capacity of the device.
Description
Technical Field
The present utility model relates to the field of semiconductor packaging technology, and in particular, to a packaging structure and an electronic device.
Background
With the development of semiconductor technology, the chip size is smaller and smaller, and moore's law gradually tends to be limited. The development of chip technology has also led to various packaging forms, as well as the development and progress of packaging technology. The current device packaging has a development trend of modularization, multifunction and compactness. How to reduce the packaging volume and how to release the heat dissipation of the chip to the external environment in time and efficiently in a limited packaging space so as to reduce the junction temperature of the chip and the working temperature of each packaging material in the device has become one of the important problems to be considered in the current packaging design stage.
The chip stacking technology, which stacks chips, logic, memory, etc. into a whole, provides possibility for downsizing the package. Common stacking techniques are Through Silicon Vias (TSVs), flip-chip bonding, and the like. The TSV technology has complex process, and the formation and metallization process of the through holes face great challenges; on the other hand, the TSV technology also has reliability problems due to plating defects, thermal mismatch, and the like.
Flip chip bonding is to interconnect the chip functional area with the substrate via solder bumps (Bump) facing down and opposite to the substrate. And manufacturing lead-free welding spots at an input/output (I/O) end of the integrated circuit chip by adopting a planar process, aligning the welding spots on the chip with welding spots on the substrate, mounting, forming welding balls between the chip and the substrate welding spots by adopting a reflow soldering process, filling underfill in a gap between the chip and the substrate, and finally realizing electric, thermal and mechanical connection between the chip and the substrate. The high consistency requirement on the salient points in the welding process is high, meanwhile, due to the small size of the flip chip, high accuracy, high yield and high repeatability are ensured, and great challenges are brought to traditional equipment and process.
The bonding wire connection limits the way of heat dissipation by the heat sink installed on the bonding side due to the requirement of the chip wire bonding, namely, the bonding quality reliability and insulation, and only has a single heat dissipation path.
Disclosure of utility model
In view of the above, it is necessary to provide a packaging structure and an electronic device for solving the problems of poor heat dissipation effect and complex process of the semiconductor packaging structure in the prior art.
A packaging structure comprises a substrate and a packaging tube shell, wherein at least a first chip, a first anisotropic conductive film and a first flexible circuit board are arranged between the substrate and the packaging tube shell;
The lower surface of the substrate is a first plate surface, the upper surface of the substrate is a second plate surface, a plurality of first bonding pads are fixedly arranged on the first plate surface, the first chip is fixedly arranged on the second plate surface, and the substrate is respectively and electrically connected with the first chip and the first bonding pads;
the first chip upper end is equipped with a plurality of evenly distributed's second bonding pad, second bonding pad upper end bonds first anisotropic conductive film, first anisotropic conductive film upper end is equipped with first flexible circuit board, first anisotropic conductive film with be equipped with a plurality of evenly distributed's third bonding pad between the first flexible circuit board, first anisotropic conductive film respectively with second bonding pad the third bonding pad is along vertical direction electric connection, the second bonding pad with third bonding pad quantity is unanimous and along the vertical direction alignment.
According to the utility model, the flexible circuit board is used for replacing point contact connection by surface contact, so that the contact area between the electrode lead-out part and the chip is increased, and the heat dissipation capacity of the device is improved; meanwhile, the parasitic inductance of a loop caused by the bonding of a long wire with a smaller sectional area is reduced; in addition, the anisotropic conductive film is utilized to realize stacking packaging among chips, superfine interval packaging is realized, high integration is realized, the packaging volume is small, the process is simple, and the cost is low; the utility model forms the bonding wire-free package through the flexible circuit board, thereby not only improving the heat dissipation of the chip, but also having the advantage of the reliability of the package.
Further, a plurality of second chips are arranged between the substrate and the package tube, and the second chips are stacked along the vertical direction or are arranged side by side along the horizontal direction or are a combination of stacked along the vertical direction and arranged side by side along the horizontal direction.
Further, when the plurality of second chips are stacked in the vertical direction, the plurality of second chips are stacked on the first chip, the bonding pads of the second chips are respectively aligned with and electrically connected with the second bonding pads and the third bonding pads in the vertical direction, a second anisotropic conductive film is bonded between the first chip and the second chip adjacent to the first chip, and the second anisotropic conductive film is only conductive in the vertical direction.
Further, when the plurality of second chips are arranged side by side along the horizontal direction, the plurality of second chips are arranged side by side with the first chip, the substrate is respectively electrically connected with the second chips and the first bonding pads, the bonding pads of the second chips are electrically connected with the third bonding pads, a third anisotropic conductive film is bonded between the second chips and the first flexible circuit board, and the third anisotropic conductive film is only conductive along the vertical direction.
Further, the package tube is welded on the base plate.
In addition, the utility model also provides electronic equipment, which comprises the packaging structure.
Drawings
Fig. 1 is a front view of a first embodiment of the present utility model.
Fig. 2 is a top view of a first embodiment of the present utility model.
Fig. 3 is a front view of a second embodiment of the present utility model.
Fig. 4 is a front view of a third embodiment of the present utility model.
Fig. 5 is a front view of a fourth embodiment of the present utility model.
Fig. 6 is a front view of a fifth embodiment of the present utility model.
1. A first substrate; 2. a first chip; 21. a second bonding pad; 3. a first anisotropic conductive film; 4. a first flexible circuit board; 41. a third bonding pad; 5. a first package tube shell; 6. a second chip; 61. a fourth pad; 62; a fifth bonding pad; 7. a second anisotropic conductive film; 8. a third chip; 81. a sixth bonding pad; 9. a third anisotropic conductive film; 10. a first bonding pad; 11. a fourth chip; 111. a seventh bonding pad; 112. an eighth pad; 12. and a fourth anisotropic conductive film.
Detailed Description
In order that the utility model may be readily understood, a more complete description of the utility model will be rendered by reference to the appended drawings. Embodiments of the utility model are illustrated in the accompanying drawings. This utility model may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, this embodiment is provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used herein in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. In addition, the features of the embodiments, the embodiments and the features of the embodiments of the present utility model can be freely combined on the premise of no obvious conflict.
Example 1
As shown in fig. 1 and 2, a package structure includes a first substrate 1, a first package case 5, a first flexible circuit board 4, and a first chip 2 and a first anisotropic conductive film 3 packaged between the first substrate 1 and the first package case 5;
the lower surface of the first substrate is a first plate surface, the upper surface of the first substrate is a second plate surface, a plurality of first bonding pads 10 are fixedly arranged on the first plate surface, the first chip 2 is fixedly arranged on the second plate surface, the first substrate 1 is respectively and electrically connected with the first chip 2 and the first bonding pads 10, and the first bonding pads 10 are electrically connected with an external circuit;
The upper end of the first chip 2 is provided with a plurality of second bonding pads 21 which are uniformly distributed, the upper end of the second bonding pads 21 is adhered with the first anisotropic conductive film 3, the upper end of the first anisotropic conductive film 3 is provided with a first flexible circuit board 4, a plurality of third bonding pads 41 which are uniformly distributed are arranged between the first anisotropic conductive film 3 and the first flexible circuit board 4, the first anisotropic conductive film 3 is respectively and electrically connected with the second bonding pads 21 and the third bonding pads 41 along the vertical direction, the second bonding pads 21 and the third bonding pads 41 are consistent in quantity and are aligned along the vertical direction, the first anisotropic conductive film 3 is only conductive along the vertical direction and is not conductive along the horizontal direction, the first flexible circuit board 4 is only conductive along the horizontal direction, and the first packaging tube shell 5 is welded on the first substrate 1.
Example two
As shown in fig. 3, in this embodiment, a second chip 6 and a second anisotropic conductive film 7 are added on the basis of the first embodiment, specifically:
The second chip 6 is stacked on the first chip 2, the second bonding pad 21 of the first chip 2 is electrically connected with the fourth bonding pad 61 of the second chip 6, the second anisotropic conductive film 7 is bonded between the second bonding pad 21 of the first chip 2 and the fourth bonding pad 61 of the second chip 6, the first flexible circuit board 4 is arranged above the second chip 6, the first anisotropic conductive film 3 is arranged between the fifth bonding pad 62 of the second chip 6 and the first flexible circuit board 4, a plurality of uniformly distributed third bonding pads 41 are arranged between the first anisotropic conductive film 3 and the first flexible circuit board 4, the second bonding pads 21 are respectively aligned with the third bonding pad 31, the fourth bonding pad 61 and the fifth bonding pad 62 in number along the vertical direction, and the second anisotropic conductive film 7 is only conductive along the vertical direction and is nonconductive along the horizontal direction.
Example III
As shown in fig. 4, in this embodiment, a third chip 8 and a third anisotropic conductive film 6 are added on the basis of the first embodiment, specifically:
A third chip 8 is arranged beside the first chip 2 on the second plate surface, and the first substrate 1 is electrically connected with the third chip 8 and the first bonding pad 10 respectively;
The upper end of the third chip 8 is provided with a plurality of uniformly distributed sixth bonding pads 81, the upper ends of the sixth bonding pads 81 are bonded with the third anisotropic conductive film 9, the third anisotropic conductive film 9 is respectively and electrically connected with the sixth bonding pads 81 and the third bonding pads 41 along the vertical direction, the sixth bonding pads 81 are aligned with the third bonding pads 41 along the vertical direction, the third anisotropic conductive film 9 is only conductive along the vertical direction and is not conductive along the horizontal direction, and the first anisotropic conductive film 3 and the third anisotropic conductive film 9 are electrically connected through the first flexible circuit board 4.
Example IV
As shown in fig. 5, this embodiment is obtained by combining the second embodiment and the third embodiment, and is specifically:
The second chip 6 is stacked on the first chip 2, a third chip 8 is arranged beside the first chip 2 on the second board surface, and the first substrate 1 is respectively and electrically connected with the first chip 2, the third chip 8 and the first bonding pad 10;
The second bonding pad 21 of the first chip 2 is electrically connected with the fourth bonding pad 61 of the second chip 6, the second anisotropic conductive film 7 is bonded between the second bonding pad 21 of the first chip 2 and the fourth bonding pad 61 of the second chip 6, the first flexible circuit board 4 is arranged above the second chip 6, the first anisotropic conductive film 3 is arranged between the fifth bonding pad 62 of the second chip 6 and the first flexible circuit board 4, a plurality of uniformly distributed third bonding pads 41 are arranged between the first anisotropic conductive film 3 and the first flexible circuit board 4, the second bonding pads 21 are respectively consistent in number with the third bonding pad 31, the fourth bonding pad 61 and the fifth bonding pad 62 and are aligned in the vertical direction, and the second anisotropic conductive film 7 is only conductive in the vertical direction and is nonconductive in the horizontal direction;
The upper end of the third chip 8 is provided with a plurality of uniformly distributed sixth bonding pads 81, the upper ends of the sixth bonding pads 81 are bonded with the third anisotropic conductive film 9, the third anisotropic conductive film 9 is respectively and electrically connected with the sixth bonding pads 81 and the third bonding pads 41 along the vertical direction, the sixth bonding pads 81 are aligned with the third bonding pads 41 along the vertical direction, the third anisotropic conductive film 9 is only conductive along the vertical direction and is not conductive along the horizontal direction, and the first anisotropic conductive film 3 and the third anisotropic conductive film 9 are electrically connected through the first flexible circuit board 4.
Example five
As shown in fig. 6, this embodiment is a combination of the second embodiment and the third embodiment, except that a fourth chip 11 and a fourth anisotropic conductive film 12 are added, specifically:
The fourth chip 11 is stacked on the third chip 8 along the vertical direction, the sixth bonding pad 81 of the third chip 8 is electrically connected with the seventh bonding pad 111 of the fourth chip 11, the fourth anisotropic conductive film 12 is bonded between the sixth bonding pad 81 of the third chip 8 and the seventh bonding pad 111 of the fourth chip 11, the first flexible circuit board 4 is arranged above the fourth chip 11, the fourth anisotropic conductive film 12 is arranged between the eighth bonding pad 112 of the fourth chip 11 and the first flexible circuit board 4, a plurality of uniformly distributed third bonding pads 21 are arranged between the fourth anisotropic conductive film 12 and the first flexible circuit board 4, the sixth bonding pad 81 is respectively aligned with the seventh bonding pad 111, the eighth bonding pad 112 and the third bonding pad 41 along the vertical direction, and the fourth anisotropic conductive film 12 is only conductive along the vertical direction and is nonconductive along the horizontal direction.
According to the utility model, the first flexible circuit board 4 is connected by surface contact instead of point contact, so that the contact area between the electrode lead-out part and the chip is increased, and the heat dissipation capacity of the device is improved. And meanwhile, the parasitic inductance of a loop caused by the bonding of the long wires with smaller sectional areas is reduced. In addition, the anisotropic conductive film is utilized to realize stacking packaging among chips, superfine interval packaging is realized, high integration is realized, the packaging volume is small, the process is simple, and the cost is low; the bonding-wire-free package formed by the first flexible circuit board 4 not only can improve the heat dissipation of the chip, but also has advantages for the reliability of the package.
It will be appreciated that in the case described in the above embodiments, the chip size, the process capability and the production cost need to be comprehensively considered in actual production, and the larger the package structure is, the better.
The embodiment of the application also provides electronic equipment, which comprises the packaging structure.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples merely illustrate embodiments of the utility model and are described in more detail and are not to be construed as limiting the scope of the utility model. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the utility model, which are all within the scope of the utility model. Accordingly, the scope of protection of the present utility model is to be determined by the appended claims.
Claims (6)
1. A package structure, characterized in that: the packaging structure comprises a substrate and a packaging tube shell, wherein at least a first chip, a first anisotropic conductive film and a first flexible circuit board are arranged between the substrate and the packaging tube shell;
The lower surface of the substrate is a first plate surface, the upper surface of the substrate is a second plate surface, a plurality of first bonding pads are fixedly arranged on the first plate surface, the first chip is fixedly arranged on the second plate surface, and the substrate is respectively and electrically connected with the first chip and the first bonding pads;
the first chip upper end is equipped with a plurality of evenly distributed's second bonding pad, second bonding pad upper end bonds first anisotropic conductive film, first anisotropic conductive film upper end is equipped with first flexible circuit board, first anisotropic conductive film with be equipped with a plurality of evenly distributed's third bonding pad between the first flexible circuit board, first anisotropic conductive film respectively with second bonding pad the third bonding pad is along vertical direction electric connection, the second bonding pad with third bonding pad quantity is unanimous and along the vertical direction alignment.
2. The package structure of claim 1, wherein: and a plurality of second chips are arranged between the substrate and the packaging tube shell, and are stacked along the vertical direction or are arranged side by side along the horizontal direction or are a combination of stacked along the vertical direction and arranged side by side along the horizontal direction.
3. The package structure of claim 2, wherein: when a plurality of second chips are stacked along the vertical direction, the second chips are stacked on the first chip, bonding pads of the second chips are respectively aligned with and electrically connected with the second bonding pads and the third bonding pads along the vertical direction, a second anisotropic conductive film is bonded between the first chip and the second chip adjacent to the first chip, and the second anisotropic conductive film is only conductive along the vertical direction.
4. The package structure of claim 2, wherein: when a plurality of second chips are arranged side by side along the horizontal direction, a plurality of second chips are arranged side by side with the first chips, the substrate is respectively electrically connected with the second chips and the first bonding pads, the bonding pads of the second chips are electrically connected with the third bonding pads, a third anisotropic conductive film is bonded between the second chips and the first flexible circuit board, and the third anisotropic conductive film is only conductive along the vertical direction.
5. The package structure of claim 1, wherein: the packaging tube shell is welded on the base plate.
6. An electronic device, characterized in that: a package structure comprising the device of any one of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202420537490.8U CN221947145U (en) | 2024-03-19 | 2024-03-19 | Packaging structure and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202420537490.8U CN221947145U (en) | 2024-03-19 | 2024-03-19 | Packaging structure and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221947145U true CN221947145U (en) | 2024-11-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202420537490.8U Active CN221947145U (en) | 2024-03-19 | 2024-03-19 | Packaging structure and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN221947145U (en) |
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- 2024-03-19 CN CN202420537490.8U patent/CN221947145U/en active Active
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