CN102376666B - A kind of ball grid array package structure and manufacture method thereof - Google Patents
A kind of ball grid array package structure and manufacture method thereof Download PDFInfo
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- CN102376666B CN102376666B CN201010248782.2A CN201010248782A CN102376666B CN 102376666 B CN102376666 B CN 102376666B CN 201010248782 A CN201010248782 A CN 201010248782A CN 102376666 B CN102376666 B CN 102376666B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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Abstract
Description
技术领域 technical field
本发明涉及一种球栅阵列封装结构及其制造方法,尤其涉及一种通过将芯片倒装于基板而提高电性能的球栅阵列封装结构及其制造方法。The invention relates to a ball grid array packaging structure and a manufacturing method thereof, in particular to a ball grid array packaging structure and a manufacturing method thereof that improve electrical performance by flipping a chip onto a substrate.
背景技术 Background technique
球栅阵列(BGA)封装技术是一种表面贴装型封装,它通过在基板的背面按阵列方式制作出球形凸点(ballbump)来代替传统的引线,使得半导体装置的集成度更高、性能更好。BGA封装技术会显著地增加器件的I/O引脚数、减小焊盘间距,进而缩小封装件的尺寸、节省封装的占位空间,从而使PC芯片组、微处理器等高密度、高性能、多引脚封装器件的微型化成为可能。随着封装技术和产品多样化需求的不断加深,高速度、低成本、小尺寸、优秀的电性能是其重要的发展趋势。Ball grid array (BGA) packaging technology is a surface mount package, which replaces traditional leads by making ball bumps (ballbumps) in an array on the back of the substrate, making semiconductor devices more integrated and high performance. better. BGA packaging technology will significantly increase the number of I/O pins of the device and reduce the pad pitch, thereby reducing the size of the package and saving the footprint of the package, so that PC chipsets, microprocessors, etc. performance, miniaturization of multi-pin packaged devices is possible. With the increasing demand for packaging technology and product diversification, high speed, low cost, small size, and excellent electrical performance are important development trends.
在传统的BGA封装的制造工艺中,芯片通过其下表面固定于基板,然后通过引线键合(wirebonding)工艺使设置于芯片上表面的焊盘通过金属线与基板上的焊点形成电气连接。然后,对所述芯片及基板进行模封(molding),以保护芯片及内部的金属线。最后,通过植球工艺在基板的下侧形成凸球,以使芯片与外部的其他电路形成电气连接。In the traditional manufacturing process of BGA package, the chip is fixed on the substrate through its lower surface, and then the pads arranged on the upper surface of the chip are electrically connected to the soldering points on the substrate through a wire bonding process through a wire bonding process. Then, the chip and the substrate are molded to protect the chip and the internal metal wires. Finally, bumps are formed on the lower side of the substrate through a ball planting process, so that the chip can be electrically connected with other external circuits.
但是,由于现有的BGA封装结构需要经过引线键合工艺制造,因此其成本较高,而且由于金属线较长,导致信号完整性较差,工艺步骤较复杂。However, because the existing BGA package structure needs to be manufactured through a wire bonding process, its cost is relatively high, and the signal integrity is poor due to the long metal wires, and the process steps are relatively complicated.
发明内容 Contents of the invention
本发明是为了解决上述问题而提出的,其目的在于提供一种球栅阵列封装结构及其制造方法,以省去引线键合工艺的同时提高球栅阵列封装结构的电性能。The present invention is proposed to solve the above problems, and its purpose is to provide a ball grid array packaging structure and a manufacturing method thereof, so as to save the wire bonding process and improve the electrical performance of the ball grid array packaging structure.
根据本发明的一方面,一种球栅阵列封装结构,包括:芯片,其上表面形成有固定单元及多个焊盘;基板,其上表面形成有与所述固定单元对应的放置单元以及与所述焊盘分别对应的多个通孔,所述芯片以倒装的方式使所述固定单元与所述放置单元接合,且使每个所述通孔分别暴露与该通孔对应的所述焊盘。According to one aspect of the present invention, a ball grid array packaging structure includes: a chip, a fixed unit and a plurality of pads are formed on its upper surface; a substrate, a placement unit corresponding to the fixed unit is formed on its upper surface, and a A plurality of through holes corresponding to the pads, the chip is flip-chip bonded to the fixing unit and the placement unit, and each of the through holes is exposed to the corresponding through hole. pad.
而且,所述固定单元与所述放置单元通过粘接胶固定在一起。Moreover, the fixing unit and the placement unit are fixed together by adhesive.
并且,所述粘接胶为导热型粘接胶,以对芯片进行散热。Moreover, the adhesive is a thermally conductive adhesive to dissipate heat from the chip.
根据本发明的球栅阵列封装结构还包括用于保护所述芯片及所述基板的塑封体。The ball grid array package structure according to the present invention further includes a plastic package for protecting the chip and the substrate.
根据本发明的球栅阵列封装结构还包括:用于保护所述焊盘的导电材料,该导电材料设置于所述通孔内部;设置于通孔下端的凸球,该凸球通过所述导电材料与所述焊盘形成电气连接。The ball grid array package structure according to the present invention further includes: a conductive material for protecting the pad, the conductive material is arranged inside the through hole; a convex ball is arranged at the lower end of the through hole, and the convex ball passes through the conductive Material forms an electrical connection with the pad.
根据本发明的另一方面,一种球栅阵列封装结构的制造方法包括以下步骤:将所述芯片倒置,且使每个所述焊盘分别与所述通孔对准;通过粘接胶将所述芯片的所述固定单元固定于所述基板的所述放置单元;在所述通孔内填入用于保护焊盘导电材料;对所述芯片及所述基板进行模封;在所述基板的所述通孔下端形成与所述焊盘构成电气连接的凸球。According to another aspect of the present invention, a manufacturing method of a ball grid array package structure includes the following steps: turning the chip upside down, and aligning each of the pads with the through hole respectively; The fixing unit of the chip is fixed to the placement unit of the substrate; filling the through hole with a conductive material for protecting the pad; molding the chip and the substrate; The lower end of the through hole of the substrate forms a bump electrically connected to the pad.
根据本发明的球栅阵列封装结构及其制造方法,通过将芯片倒装于基板,并通过设置于基板的通孔暴露芯片上的每一个焊盘,且通过导电材料保护焊盘后直接在焊盘上植球,由此实现低成本、工艺简单,且具有高电性能。According to the ball grid array package structure and its manufacturing method of the present invention, the chip is flipped on the substrate, and each pad on the chip is exposed through the through hole provided on the substrate, and the pad is protected by a conductive material and directly on the solder pad. The balls are planted on the plate, thereby achieving low cost, simple process, and high electrical performance.
附图说明 Description of drawings
图1为根据本发明的芯片上表面的示意图;Fig. 1 is the schematic diagram according to the upper surface of the chip of the present invention;
图2为根据本发明的芯片的侧视图;Figure 2 is a side view of a chip according to the present invention;
图3为根据本发明的基板的剖视图;3 is a cross-sectional view of a substrate according to the present invention;
图4为根据本发明的球栅阵列封装结构的示意图;4 is a schematic diagram of a ball grid array package structure according to the present invention;
图5为根据本发明的球栅阵列封装结构的制造工艺流程图。FIG. 5 is a flow chart of the manufacturing process of the ball grid array package structure according to the present invention.
具体实施方式 detailed description
以下,参照附图来详细说明根据本发明的实施例的引线加热装置。然而,本发明可以以许多不同的方式来实施,而不应被理解为限于下面的实施例。在附图中,为了清晰起见,夸大尺寸进行表示,并且不同的附图中使用相同的标号表示相同的部件。Hereinafter, a lead wire heating device according to an embodiment of the present invention will be described in detail with reference to the drawings. However, the present invention can be implemented in many different ways and should not be construed as being limited to the following examples. In the drawings, the dimensions are exaggerated for clarity, and the same reference numerals are used in different drawings to designate the same components.
图1为根据本发明的芯片上表面的示意图,图2为根据本发明的芯片的侧视图,图3为根据本发明的基板的剖视图,图4为根据本发明的球栅阵列封装结构的示意图。Fig. 1 is a schematic diagram of the upper surface of a chip according to the present invention, Fig. 2 is a side view of a chip according to the present invention, Fig. 3 is a cross-sectional view of a substrate according to the present invention, and Fig. 4 is a schematic diagram of a ball grid array package structure according to the present invention .
由图可知,根据本发明的芯片10的上表面形成有多个焊盘11以及固定单元12。所述焊盘11作为输入/输出端子与外部电路连接而使芯片能够执行特定的功能。所述固定单元12用于将所述芯片10设置在基板13上,以对芯片10进行封装。所述基板13用于搭载所述芯片10,在其上表面形成有用于与芯片10的固定单元12接合的放置单元15。所述固定单元12与所述放置单元15之间通过粘接胶19进行固定。优选地,所述放置单元15形成有具有一定深度的凹槽,以设置所述粘接胶19。所述粘接胶19具有导热功能,以对芯片10运行时产生的热量进行散热。在所述基板13上还形成有多个贯穿其上下表面而形成的通孔14,并且每个通孔14可分别与所述芯片10的焊盘11对应,由此当所述芯片10搭载并固定于所述基板13时,所述通孔14暴露所述焊盘11。由图4可知,由于本发明的芯片10的焊盘11及固定单元12都形成在上表面,因此在将所述芯片10固定于所述基板13时,所述芯片10的上表面与所述基板13的上表面紧密接触,即所述芯片10倒装粘贴到所述基板13。而且,在所述基板13的通孔14内设置导电材料18,以保护所述焊盘10,防止芯片10失去作用。并且,与现有技术相比,本发明中所述焊盘11通过导电材料18直接与焊球17形成电气连接。即,本发明中所述基板13无需布线,仅起到一种支撑框架的作用。符号16表示用于保护芯片等内部结构的塑封体。It can be seen from the figure that a plurality of pads 11 and fixing units 12 are formed on the upper surface of the chip 10 according to the present invention. The pads 11 are used as input/output terminals to connect with external circuits so that the chip can perform specific functions. The fixing unit 12 is used for disposing the chip 10 on the substrate 13 to package the chip 10 . The substrate 13 is used to mount the chip 10 , and a placement unit 15 for bonding with the fixing unit 12 of the chip 10 is formed on its upper surface. The fixing unit 12 and the placing unit 15 are fixed by an adhesive 19 . Preferably, the placement unit 15 is formed with a groove with a certain depth for setting the adhesive 19 . The adhesive 19 has a heat conduction function to dissipate heat generated when the chip 10 is running. A plurality of through holes 14 formed through the upper and lower surfaces of the substrate 13 are also formed, and each through hole 14 can correspond to the pad 11 of the chip 10 respectively, so that when the chip 10 is loaded and When fixed on the substrate 13 , the through hole 14 exposes the pad 11 . As can be seen from FIG. 4 , since the pads 11 and the fixing unit 12 of the chip 10 of the present invention are all formed on the upper surface, when the chip 10 is fixed on the substrate 13, the upper surface of the chip 10 and the The upper surface of the substrate 13 is in close contact, that is, the chip 10 is flip-chip bonded to the substrate 13 . Moreover, a conductive material 18 is provided in the through hole 14 of the substrate 13 to protect the pad 10 and prevent the chip 10 from losing its function. Moreover, compared with the prior art, the pad 11 in the present invention is directly electrically connected to the solder ball 17 through the conductive material 18 . That is, in the present invention, the substrate 13 does not need wiring, and only serves as a supporting frame. Symbol 16 represents a plastic package for protecting internal structures such as chips.
以下,结合图1至图5详细说明根据本发明的球栅阵列封装结构的制造工艺。图5为根据本发明的球栅阵列封装结构的制造工艺流程图。由图可知,根据本发明的球栅阵列封装结构的制造工艺如下:首先,如图5的(a)所示,将芯片倒置,并对齐芯片上的焊盘与基板上的通孔。此时,当所述芯片上的焊盘与所述基板上的通孔对准时,所述芯片的固定单元自然地与所述基板上的放置单元对齐。然后,如图5的(b)所示,利用粘接胶将所述芯片固定于所述基板。此时所述粘接胶为导热型粘接胶,以对芯片运行时产生的热量进行散热。然后,在所述基板的通孔内填入导电材料,以保护所述焊盘,避免芯片失去作用。此时,相邻的焊盘之间需要保持一定的间距,以避免相邻的焊盘通过导电材料形成连点。然后,如图5的(d)所示,对经过上述工艺的芯片及基板进行模封(molding),以保护芯片。然后,如图5的(e)所示,在所述基板的所述通孔下端形成与所述焊盘构成电气连接的凸球。此时,所述凸球通过导电材料直接与焊盘形成电气连接,由此提高了电性能。Hereinafter, the manufacturing process of the ball grid array package structure according to the present invention will be described in detail with reference to FIG. 1 to FIG. 5 . FIG. 5 is a flow chart of the manufacturing process of the ball grid array package structure according to the present invention. It can be seen from the figure that the manufacturing process of the ball grid array package structure according to the present invention is as follows: first, as shown in FIG. 5 (a), turn the chip upside down and align the pads on the chip with the through holes on the substrate. At this time, when the pads on the chip are aligned with the through holes on the substrate, the fixing unit of the chip is naturally aligned with the placement unit on the substrate. Then, as shown in (b) of FIG. 5 , the chip is fixed to the substrate with an adhesive. At this time, the adhesive is a heat-conducting adhesive to dissipate heat generated when the chip is running. Then, a conductive material is filled into the through hole of the substrate to protect the pad and prevent the chip from losing its function. At this time, a certain distance needs to be kept between adjacent pads, so as to prevent adjacent pads from forming connection points through conductive materials. Then, as shown in (d) of FIG. 5 , molding is performed on the chip and the substrate after the above process to protect the chip. Then, as shown in (e) of FIG. 5 , bumps electrically connected to the pads are formed at the lower ends of the through holes of the substrate. At this time, the bumps are directly electrically connected to the pads through the conductive material, thereby improving the electrical performance.
根据本发明的球栅阵列封装结构及其制造方法,通过将芯片倒装于基板,并通过设置于基板的通孔暴露芯片上的每一个焊盘,且通过导电材料保护焊盘后直接在焊盘上植球,由此实现低成本、工艺简单,且具有高电性能。而且,本发明中的基板无需进行布线,由此节省了工艺,并降低了成本。According to the ball grid array package structure and its manufacturing method of the present invention, the chip is flipped on the substrate, and each pad on the chip is exposed through the through hole provided on the substrate, and the pad is protected by a conductive material and directly on the solder pad. The balls are planted on the plate, thereby achieving low cost, simple process, and high electrical performance. Moreover, the substrate in the present invention does not need to be wired, thereby saving processes and reducing costs.
本发明不限于上述实施例,在不脱离本发明范围的情况下,可以进行各种变形和修改。The present invention is not limited to the above-described embodiments, and various variations and modifications can be made without departing from the scope of the present invention.
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