CN101118901B - Stacked chip package structure and manufacturing process thereof - Google Patents

Abstract

The invention discloses a stacked chip packaging structure and a manufacturing process thereof. The stacked chip packaging structure comprises a first packaging structure unit and a second packaging structure unit. The first package structure unit includes a carrier, a chip, a first sealant, a wiring element, a conductive element and a second sealant. The second sealant covers the surface of the carrier, the chip, the first sealant, the wiring element and the conductive element, and exposes the top of the conductive element. The second packaging structure unit is electrically connected to the wiring element through the conductive element. The invention uses the wiring element to connect the two packaging structure units, thereby saving the available space of the loader and improving the integration level. The molding compound covers the whole bearing surface, so the shape is not influenced by the size and the configuration of the chip, and the molding compound mold of the manufacturing process can be used for the size and the configuration of various chips.

Description

Stacked chip packaging structure and its manufacturing process

【Technical field】

The present invention relates to a semiconductor device package and its manufacturing process, and in particular to a stacked type chip packaging structure and its manufacturing process.

【Background technique】

In today's highly informationized society, the market for multimedia applications continues to expand rapidly, and integrated circuit (IC) packaging technology also needs to develop in line with the trend of digitalization, networking, regional connectivity, and user-friendly electronic devices. In order to achieve the above requirements, it is necessary to strengthen the requirements of high-speed processing, multi-function, integration, small size, light weight and low price of electronic components, so the integrated circuit packaging technology is also developing towards miniaturization and high density. . In addition to the existing common ball grid array package (Ball Grid Array, BGA), chip scale package (Chip-Scale Package, CSP), flip chip package (Flip Chip package, F/C package), recently proposed stacking A chip packaging technology, which stacks multiple chip packaging units to increase the overall packaging density.

FIG. 1 is a schematic cross-sectional view of a conventional stacked chip packaging structure. 1, the existing stacked chip package structure 100 includes a first package unit 110, a second package unit 120 and a plurality of solder balls (solder ball) 130, wherein the solder ball 130 is configured in the first package unit 110 The periphery of the chip 114 is used to connect the first packaging unit 110 and the second packaging unit 120 . However, since the solder balls 130 are disposed on the periphery of the chip 114 and occupy the available area of the circuit substrate 112 , the volume of the stacked chip package structure 100 cannot be further reduced. In addition, the chip 114 is connected to the circuit substrate 112 by wire bonding, and the encapsulant 118 is only formed on a partial area of the circuit substrate 112 to cover the chip 114 and the wires 116 . In this way, it is not conducive to the design of the sealing mold, that is to say, the sealing mold must be designed corresponding to the size and position of the sealing compound 118 , and cannot be shared in the manufacturing process of the packaging units designed in different sizes.

FIG. 2 is a schematic cross-sectional view of another existing stacked chip packaging structure. Please refer to FIG. 2, the stacked chip packaging structure 200 is similar to the stacked chip packaging structure 100 in FIG. The substrate 216 exposes a plurality of solder balls 214 disposed on the circuit substrate 216 and surrounding the chip 218 . The second packaging unit 220 is fixed above the first packaging unit 210 and is electrically connected to the first packaging unit 210 through the solder ball 230 and the solder ball 214 .

The sealant 212 in FIG. 2 covers the entire circuit substrate 216 , and this design helps to improve the compatibility of the sealant mold. However, since the solder balls 214 and the solder balls 230 are still disposed on the periphery of the chip 218 , they also occupy the available area of the circuit substrate 216 and limit the size of the stacked chip package structure 200 .

FIG. 3 is a schematic cross-sectional view of yet another conventional stacked chip packaging structure. 3, in the stacked chip package structure 300, a circuit substrate 312b is arranged on the first packaging unit 310 instead, and the circuit substrate 312b is electrically connected to the circuit substrate 312a of the first packaging unit 310 through wires 316. . In addition, the second package unit 320 is connected to the circuit substrate 312b through a plurality of solder balls 330, so that the first package unit 310 and the second package unit 320 are electrically connected to each other through the circuit substrate 312b. This design can solve the problem of occupying the space of the circuit substrate 312a to arrange the solder balls. However, it is necessary to form a special-shaped sealant 318 to cover the wires 316 and expose the surface of the circuit substrate 312b for the solder balls 330. configuration, so there is also the problem that the sealing film cannot be shared, and different sealing films must be designed corresponding to the appearance of the packaging unit.

【Content of invention】

The main purpose of the present invention is to provide a stacked chip packaging structure to improve the above-mentioned shortcomings of the existing chip packaging structure technology.

Another object of the present invention is to provide a chip packaging structure, which can be applied to the above-mentioned stacked chip packaging structure, so as to solve the problems of the existing chip packaging structure technology.

Another object of the present invention is to provide a manufacturing process of a chip packaging structure, which is used to manufacture the above-mentioned chip packaging structure.

In order to achieve the above or other objects, the present invention adopts the following technical solutions: a chip packaging structure, including a carrier (carrier), a chip, a first sealant, a wiring element (circuit distribution device), a plurality of conductive elements And a second sealant. The carrier has a carrying surface and an opposite back. The chip is disposed on the bearing surface and electrically connected to the bearing. The first sealant is arranged on the bearing surface and covers the chip. The wiring element is disposed on the first encapsulant and is electrically connected to the carrier, and a plurality of ball pads are provided above the surface of the first encapsulant. The conductive elements are respectively configured on the pads. The second encapsulant covers the bearing surface, covers the chip, the first encapsulant, the wiring element and the conductive element, and exposes the top of the conductive element.

The present invention further proposes a stacked chip packaging structure, which is mainly formed by using the above-mentioned chip packaging structure as a packaging structural unit and stacking it with another packaging structural unit. Wherein, the two packaging structural units are electrically connected to each other through the above-mentioned conductive elements and wiring elements.

In an embodiment of the present invention, the above-mentioned carrier or wiring element is, for example, a circuit substrate, respectively.

In an embodiment of the present invention, the above-mentioned first package structure unit may further include a plurality of conductive bumps, and the chip is electrically connected to the carrier through these conductive bumps in a flip-chip manner.

In an embodiment of the present invention, the above-mentioned first package structure unit may further include a plurality of first wires connected between the chip and the carrier, and covered by the first encapsulant.

In an embodiment of the present invention, the above-mentioned first package structure unit may further include a plurality of second wires connected between the wiring element and the carrier, and covered by the second encapsulant.

In an embodiment of the present invention, the above-mentioned conductive elements are, for example, a plurality of first solder balls. In addition, the pads on the wiring element are arranged in an array, for example, and correspondingly, the second package structure unit can be a ball grid array package structure unit or other package structure components with array pins.

In an embodiment of the present invention, the first package structure unit may further include a plurality of second solder balls disposed on the back of the carrier. The second solder balls are electrically connected to the chip and the wiring elements through the carrier.

The present invention further provides a chip packaging structure manufacturing process, which includes the following steps. Firstly, a carrier is provided, and the carrier has a carrying surface and an opposite back surface. Next, a chip is arranged on the carrying surface, and the chip is electrically connected to the carrier. Then, a first sealant is formed on the carrying surface to cover the chip. Afterwards, a wiring component is disposed on the first molding compound to provide a plurality of pads above the surface of the first molding compound. Next, a plurality of conductive elements are disposed on the pads. Then, electrically connect the wiring element to the carrier. Afterwards, a second encapsulant is covered on the carrying surface, so as to cover the chip, the first encapsulant, the wiring elements and these conductive elements through the second encapsulant, and the second encapsulant exposes the top of the conductive element.

In one embodiment of the present invention, for example, the chip and the carrier are electrically connected through a flip chip bonding process or a wire bonding process.

In an embodiment of the present invention, the step of arranging the conductive element is, for example, arranging a first solder ball on each pad.

In an embodiment of the present invention, the above-mentioned chip packaging structure manufacturing process further includes disposing a plurality of second solder balls on the back of the carrier, so that the second solder balls are electrically connected to the chip and the wiring elements through the carrier.

In one embodiment of the present invention, the above-mentioned chip packaging structure manufacturing process further includes disposing a second packaging structure unit on the first packaging structure unit, so that the second packaging structure unit is electrically connected to the wiring element through a conductive element, so as to form A stacked chip packaging structure.

Based on the above, the present invention arranges the wiring element above the chip to connect the two packaging units, thus helping to save the available space on the carrier of the packaging unit, thereby improving the integration of the stacked chip packaging structure. In addition, since the encapsulant covers the entire carrying surface of the carrier, and its appearance is not affected by the size and configuration of the chip, the encapsulant mold used in the chip packaging structure manufacturing process of the present invention can be applied to various chip sizes and configuration.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

【Description of drawings】

FIG. 1 is a schematic cross-sectional view of a conventional stacked chip packaging structure.

FIG. 2 is a schematic cross-sectional view of another existing stacked chip packaging structure.

FIG. 3 is a schematic cross-sectional view of yet another conventional stacked chip packaging structure.

FIG. 4 is a schematic cross-sectional view of a chip packaging structure according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a stacked chip package structure according to an embodiment of the present invention.

6A to 6I illustrate the manufacturing process of the above-mentioned chip package structure.

【Detailed ways】

FIG. 4 is a schematic cross-sectional view of a chip packaging structure according to an embodiment of the present invention. Referring to FIG. 4 , the chip packaging structure 400 of this embodiment includes a carrier 410 , a chip 420 , a first encapsulant 430 , a wiring element 440 , a plurality of conductive elements 450 , and a second encapsulant 460 . The carrier 410 has a carrying surface 412 and an opposite back surface 414 . The chip 420 is disposed on the carrying surface 412 and electrically connected to the carrier 410 . The first encapsulant 430 is disposed on the carrying surface 412 and covers the chip 420 . The wiring element 440 is disposed on the first encapsulant 430 and electrically connected to the carrier 410 , and the wiring element 440 provides a plurality of pads 442 above the surface of the first encapsulant 430 . The conductive elements 450 are respectively disposed on the pads 442 . The second encapsulant 460 covers the carrying surface 412 and covers the chip 420 , the first encapsulant 430 , the wiring element 440 and the conductive element 450 , and exposes the top of the conductive element 450 .

In this embodiment, the wiring element 440 and the carrier 410 can be a circuit substrate or a printed circuit board (printed circuit board, PCB) respectively. However, the present invention does not limit the types of the wiring element 440 and the carrier 410 . In other embodiments, the wiring element 440 can also be other packaging structural elements that can provide a plurality of pads 442 above the surface of the first encapsulant 430, and the carrier 410 can also be other packaging structural elements suitable for carrying the chip 420. . In addition, in this embodiment, the conductive element 450 is, for example, a solder ball. However, in other embodiments of the present invention, the conductive element 450 may also be a conductive block or other types of conductors.

Based on the above, since the chip packaging structure 400 of this embodiment utilizes the wiring elements 440 arranged above the chip 420 to concentrate the conductive elements 450 electrically connected to the outside world above the chip 420, it helps to save available space on the carrier 410. area, so as to improve the integration degree of the chip package structure 400, and enable the carrier 410 to have enough carrying area to carry a larger-sized chip 420. In addition, since the second sealant 460 of the chip packaging structure 400 of this embodiment covers the entire bearing surface 412, and its appearance is not affected by the size and configuration of the chip 420, the sealant used to form the second sealant 460 Dies are available for various chip 420 sizes and configurations. That is to say, a single sealing mold can be used to manufacture the chip packaging structure 400 of various specifications, so that there is no need to order a variety of corresponding sealing molds for various specifications, thereby reducing the manufacturing cost of the chip packaging structure 400 .

In this embodiment, the chip 420 is electrically connected to the carrier 410 through a plurality of first wires 470 by wire bonding, wherein the first wires 470 are covered by the first encapsulant 430 . However, in another embodiment of the present invention, the chip 420 can also be electrically connected to the carrier 410 through a plurality of conductive bumps (not shown) in a flip-chip manner. In addition, in this embodiment, the wiring element 440 can be electrically connected to the carrier 410 through a plurality of second wires 480 by wire bonding, wherein the second wires 480 are covered by the second encapsulant 460 .

In this embodiment, the pads 442 are arranged in an array on the upper surface of the wiring element 440 . However, in other embodiments of the present invention, the pads 442 may also be arranged in other forms on the surface of the first encapsulant 430 . In addition, the chip package structure 400 may further include a plurality of solder balls 490 disposed on the back surface 414 of the carrier 410 . The solder balls 490 are electrically connected to the chip 420 and the wiring element 440 through the carrier 410 , and the chip package structure 400 can be electrically connected to other electronic components (such as a motherboard) through the solder balls 490 .

The present invention further proposes a stacked chip packaging structure, which is mainly formed by using the above-mentioned chip packaging structure as a packaging structural unit and stacking it with another packaging structural unit. FIG. 5 is a schematic cross-sectional view of a stacked chip package structure according to an embodiment of the present invention. Referring to FIG. 5 , the stacked chip package structure 500 of this embodiment includes a first package structure unit 510 and a second package structure unit 520 . The first packaging structure unit 510 is the above-mentioned chip packaging structure 400 . The second packaging structure unit 520 is disposed on the first packaging structure unit 510 and is electrically connected to the wiring element 440 through the conductive element 450 . Specifically, in this embodiment, the second package structure unit 520 is a ball grid array package structure unit, and its spherical leads (spherical leads) 522 are correspondingly connected to the conductive elements 450 arranged in an array. In addition, since the wiring element 440 has a sufficient area for disposing the conductive element 450 , it is suitable for bonding between highly integrated packaging structural units.

6A to 6I illustrate the manufacturing process of the above-mentioned chip packaging structure, which mainly includes the following steps. First, as shown in FIG. 6A , the above-mentioned carrier 410 is provided. Next, as shown in FIG. 6B , the chip 420 is disposed on the carrying surface 412 of the carrier 410 , and the chip 420 is electrically connected to the carrier 410 . In this embodiment, a wire bonding process is performed so that the chip 420 is electrically connected to the carrier 410 through a plurality of first wires 470 . Certainly, other embodiments of the present invention may also use flip-chip bonding or other methods to electrically connect the chip 420 to the carrier 410 .

Then, as shown in FIG. 6C , a first sealant 430 is formed on the carrying surface 412 of the carrier 410 so as to cover the chip 420 . For example, a mold can be used to form the first sealant 430 . In this embodiment, the formed first encapsulant 430 also covers the first wire 470 .

Afterwards, as shown in FIG. 6D , the wiring element 440 is disposed on the first encapsulant 430 to provide a plurality of pads 442 above the surface of the first encapsulant 430 . Next, as shown in FIG. 6E , a conductive element 450 is formed on the pad 442 . Specifically, in this embodiment, a solder ball is disposed on each pad 442 . However, other embodiments of the present invention may also form a conductive block or other types of conductors on each pad 442 .

Then, as shown in FIG. 6F , electrically connect the wiring element 440 to the carrier 410 . In this embodiment, for example, a wire bonding process is performed to electrically connect the wiring element 440 to the carrier 410 through the second wire 480 .

Afterwards, as shown in FIG. 6G, the second sealant 460 is covered on the carrying surface 412 of the carrier 410, so that the second sealant 460 covers the chip 420, the first sealant 430, the wiring elements 440 and the conductive elements. 450 , and make the second sealant 460 expose the top of the conductive element 450 . For example, in this embodiment, the second sealant 460 can be formed by sealing a mold. Since the second sealant 460 covers the entire bearing surface 412, its appearance is not affected by the size and configuration of the chip 420, so the sealant The mold is applicable to various sizes and configurations of the chip 420 and has high process compatibility. In addition, in this embodiment, the formed second sealant 460 also covers the second wire 480 . So far, the fabrication of the chip package structure 400 or the first package structure unit 510 is completed.

The chip packaging structure manufacturing process of this embodiment may further include the steps shown in FIG. 6H and FIG. 6I to form a stacked chip packaging structure. After the above steps, as shown in FIG. 6H , the second package structure unit 520 is disposed on the first package structure unit 510 , so that the second package structure unit 520 is electrically connected to the wiring element 440 through the conductive elements 450 . Then, as shown in FIG. 6I , in this embodiment, a plurality of solder balls 490 can also be optionally arranged on the back surface 414 of the carrier 410 , so that these solder balls 490 are electrically connected to the chip 420 and the wiring element 440 through the carrier 410 . So far, the fabrication of the stacked chip packaging structure 500 is roughly completed.

In summary, the present invention arranges the wiring elements above the chip to connect the two packaging structural units, thus helping to save the available space on the carrier of the packaging structural unit, thereby improving the integration of the stacked chip packaging structure, and The carrier can have enough carrying area to carry larger size chips. Furthermore, since there is enough area on the wiring element to dispose a large number of conductive elements, it is helpful to increase the number of pins of the package structure unit. In addition, since the stacked chip packaging structure of the present invention adopts the design that the encapsulant covers the entire surface of the carrier, the appearance of the encapsulant is not affected by the size and configuration of the chips. That is to say, the sealing mold used in the chip packaging structure manufacturing process of the present invention is applicable to various chip packaging structure designs, has high compatibility, and helps to save production costs.

Claims (10)

1. stack type chip packaging structure, comprise: one first encapsulating structure unit and one second encapsulating structure unit, the described first encapsulating structure unit comprises a carrier, one chip and one first sealing, wherein carrier has a loading end and opposing backside surface, chip configuration is on this loading end and be electrically connected to this carrier, first sealing is disposed on this loading end and covers this chip, the described second encapsulating structure configuration of cells is on this first encapsulating structure unit, it is characterized in that: described stack type chip packaging structure also comprises a wire element, a plurality of conducting elements and one second sealing, this wire element is disposed in this first sealing, be electrically connected to this carrier and provide a plurality of connection pads in this first sealing surface, described a plurality of conducting element is disposed at respectively on those connection pads, described second sealing covers this loading end, and coat this chip, this first sealing, this wire element and those conducting elements, and this second sealing exposes the top of those conducting elements, the described second encapsulating structure unit has a plurality of spherical pins, and those spherical pins and those conducting elements by this first encapsulating structure unit are electrically connected to this wire element in this second sealing.

2. stack type chip packaging structure as claimed in claim 1 is characterized in that: at least one in this carrier and this wire element is a circuit base plate.

3. stack type chip packaging structure as claimed in claim 1 is characterized in that: this first encapsulating structure unit also comprises a plurality of conductive projections, and this chip is electrically connected to this carrier with flip chip by those conductive projections.

4. stack type chip packaging structure as claimed in claim 1, it is characterized in that: this first encapsulating structure unit also comprises many leads, at least a portion is connected between this chip and this carrier and/or between this wire element and this carrier in these leads, this first sealing of lead that is connected between this chip and this carrier coats, and the lead that is connected between this wire element and this carrier is coated by this second sealing.

5. stack type chip packaging structure as claimed in claim 1 is characterized in that: those conducting elements comprise a plurality of first soldered balls.

6. as claim 1,2,3,4 or 5 described stack type chip packaging structures, it is characterized in that: those connection pads are array configurations.

7. stack type chip packaging structure as claimed in claim 1 is characterized in that: this second encapsulating structure unit is a spherical grid array type encapsulating structure unit.

8. as claim 1 or 7 described stack type chip packaging structures, it is characterized in that: this first encapsulating structure unit also comprises a plurality of second soldered balls, those second soldered balls are disposed at the back side of this carrier, are electrically connected to this chip and this wire element by this carrier.

9. chip-packaging structure, comprise a carrier, one chip and one first sealing, wherein said carrier has a loading end and opposing backside surface, chip configuration is on this loading end and be electrically connected to this carrier, first sealing is disposed on this loading end and covers this chip, it is characterized in that: described chip-packaging structure also comprises: a wire element, a plurality of conducting elements and one second sealing, wherein wire element is disposed in this first sealing, this wire element is electrically connected to this carrier and provides a plurality of connection pads in this first sealing surface, a plurality of conducting elements are disposed at respectively on those connection pads, second sealing covers this loading end, and coat this chip, this first sealing, this wire element and those conducting elements, and this second sealing exposes the top of those conducting elements, electrically connects a plurality of spherical pin that another encapsulating structure unit of this chip-packaging structure top configuration is had with correspondence.

10. chip-packaging structure processing procedure comprises:

One carrier is provided, and this carrier has a loading end and opposing backside surface;

Dispose a chip on this loading end, and make this chip be electrically connected to this carrier;

Form one first sealing on this loading end, make it cover chip;

Dispose a wire element in this first sealing, to provide a plurality of connection pads in this first sealing surface;

Dispose a plurality of conducting elements on those connection pads;

Electrically connect this wire element to this carrier;

Cover one second sealing in this loading end, with by this this chip of second sealant covers, this first sealing, this wire element and those conducting elements, and this second sealing exposes the top of those conducting elements, to constitute one first encapsulating structure unit; And

Dispose one second encapsulating structure unit in this top, first encapsulating structure unit, this second encapsulating structure unit has a plurality of spherical pins, and those spherical pins and those conductive components by this first encapsulating structure unit are electrically connected to this cloth line component in this second sealing.

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