CN101527292B - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
- Publication number
- CN101527292B CN101527292B CN200810083178A CN200810083178A CN101527292B CN 101527292 B CN101527292 B CN 101527292B CN 200810083178 A CN200810083178 A CN 200810083178A CN 200810083178 A CN200810083178 A CN 200810083178A CN 101527292 B CN101527292 B CN 101527292B
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- CN
- China
- Prior art keywords
- chip
- lead frame
- packing colloid
- packaging structure
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 32
- 239000000084 colloidal system Substances 0.000 claims abstract description 37
- 238000012856 packing Methods 0.000 claims description 35
- 239000011248 coating agent Substances 0.000 claims description 30
- 238000000576 coating method Methods 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 14
- 239000003822 epoxy resin Substances 0.000 claims description 8
- 229920000647 polyepoxide Polymers 0.000 claims description 8
- 239000004568 cement Substances 0.000 claims description 3
- 229920001187 thermosetting polymer Polymers 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 34
- 229910000679 solder Inorganic materials 0.000 abstract description 18
- 239000000126 substance Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明公开了一种芯片封装结构，其包括基板、芯片、多个凸块以及封装胶体。基板具有至少一开口，且具有多个第一焊垫以及多个焊球垫，其中第一焊垫与焊球垫分别配置于基板的二个相对表面上。芯片具有主动表面以及位于主动表面上的多个第二焊垫，其中芯片的主动表面是面向基板。凸块配置于第一焊垫与第二焊垫之间，并连接第一焊垫与第二焊垫。封装胶体包覆芯片与凸块，且填满开口。
The present invention discloses a chip packaging structure, which includes a substrate, a chip, a plurality of bumps and a packaging colloid. The substrate has at least one opening, and has a plurality of first solder pads and a plurality of solder ball pads, wherein the first solder pads and the solder ball pads are respectively arranged on two opposite surfaces of the substrate. The chip has an active surface and a plurality of second solder pads located on the active surface, wherein the active surface of the chip faces the substrate. The bump is arranged between the first solder pad and the second solder pad, and connects the first solder pad and the second solder pad. The packaging colloid covers the chip and the bump, and fills the opening.
Description
Technical field
The invention relates to a kind of chip-packaging structure, and particularly relevant for a kind of chip-packaging structure that can improve element efficiency.
Background technology
Along with science and technology is maked rapid progress, (integrated circuits, IC) element has been widely used in the middle of our daily life integrated circuit.Generally speaking, the production of integrated circuit mainly is divided into three phases: the encapsulation of the manufacturing of Silicon Wafer, the making of integrated circuit and integrated circuit.
Fig. 1 is the generalized section of traditional a kind of chip-packaging structure.Please with reference to Fig. 1, chip-packaging structure 100 comprises circuit board 102, chip 104, adhesion coating 106, packing colloid 108 and soldered ball 109.Circuit board 102 has opening 110, and has weld pad 112 and solder ball pad 114.Chip 104 has active surface and is positioned at the weld pad 116 on the active surface, and chip 104 is to be disposed on the surface with weld pad 112 and solder ball pad 114 opposed circuit boards 102 with the mode of covering crystalline substance (flip chip).Lead 118 electrically connects weld pad 112 and weld pad 116.Adhesion coating 106 is disposed between circuit board 102 and the chip 104.Packing colloid 108 coating chips 104, adhesion coating 106, weld pad 112, weld pad 116 and lead 118.On the soldered ball 109 configuration solder ball pads 114.
Because chip 104 is to be disposed on the circuit board 102 to cover brilliant mode; And lay respectively at two sides of circuit board 102 with weld pad 112; Therefore when chip 104 electrically connects with circuit board 102 through lead 118; Influence the electrical transmitting speed between chip 104 and the circuit board 102 easily because of the length of lead 118 is long, and then influence the usefulness of element.
Summary of the invention
In view of this, the object of the invention is providing a kind of chip-packaging structure exactly, and it can promote the electrical transmitting speed between chip and the substrate.
Another object of the present invention is providing a kind of chip-packaging structure exactly, and it can improve element efficiency effectively.
The present invention proposes a kind of chip-packaging structure, and it comprises substrate, chip, a plurality of projection and packing colloid.Substrate has at least one opening, and has a plurality of first weld pads and a plurality of solder ball pad, and wherein first weld pad and solder ball pad are disposed at respectively on two apparent surfaces of substrate.Chip has active surface and is positioned at a plurality of second weld pads on the active surface, and the active surface of its chips is towards substrate.Projection is disposed between first weld pad and second weld pad, and connects first weld pad and second weld pad.Packing colloid coating chip and projection, and fill up opening.Chip-packaging structure more can comprise the adhesion coating that is disposed between chip and the substrate and centers on the projection setting.
According to the described chip-packaging structure of the embodiment of the invention, above-mentioned adhesion coating is the thermosetting cement material for having second order (B-stage) characteristic for example.
According to the described chip-packaging structure of the embodiment of the invention, more can comprise a plurality of soldered balls, and each soldered ball is disposed at respectively on one of them solder ball pad.
According to the described chip-packaging structure of the embodiment of the invention, the material of above-mentioned packing colloid for example is epoxy resin (epoxy resin).
The present invention proposes a kind of chip-packaging structure in addition, and it comprises a plurality of lead frame pins, chip, a plurality of projection, adhesion coating, first packing colloid and second packing colloid.The lead frame pin has at least one opening.Chip has active surface and is positioned at a plurality of weld pads on the active surface, and the active surface of its chips is towards the lead frame pin.Projection is disposed between weld pad and the lead frame pin, and connects weld pad and lead frame pin.Adhesion coating is disposed between lead frame pin and the chip, and coats projection.First packing colloid is disposed in the opening.Second packing colloid coating chip and the adhesion coating.Adhesion coating is arranged on first packing colloid of opening.
According to the described chip-packaging structure of the embodiment of the invention, the material of the first above-mentioned packing colloid for example is an epoxy resin.
According to the described chip-packaging structure of the embodiment of the invention, the material of the second above-mentioned packing colloid for example is an epoxy resin.
The contact that the present invention will connect chip and substrate (or lead frame pin) is arranged at the same side of substrate (or lead frame pin); And utilize projection that chip and substrate (or lead frame pin) are electrically connected; Therefore shortened the path that chip and substrate (or lead frame pin) electrically connect, the electrical transmitting speed between chip and the substrate (or lead frame pin) is increased.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs., elaborates as follows.
Description of drawings
Fig. 1 is the generalized section of traditional a kind of chip-packaging structure.
Fig. 2 is the generalized section according to the chip-packaging structure that one embodiment of the invention illustrated.
Fig. 3 is the generalized section according to the chip-packaging structure that another embodiment of the present invention illustrated.
Embodiment
Fig. 2 is the generalized section according to the chip-packaging structure that one embodiment of the invention illustrated.Please with reference to Fig. 2, chip-packaging structure 200 comprises substrate 202, chip 204, projection 206, packing colloid 208 and soldered ball 209.Substrate 202 has opening 210, and has weld pad 212 and solder ball pad 214.Weld pad 212 is disposed at respectively on two apparent surfaces of substrate 202 with solder ball pad 214.Chip 204 has active surface and is positioned at the weld pad 216 on the active surface, and the active surface of chip 204 is towards substrate 202.That is to say that chip 204 is to be disposed on the substrate 202 to cover brilliant mode.Projection 206 is disposed between weld pad 212 and the weld pad 216, and connects weld pad 212 and weld pad 216.Anticipate promptly, chip 204 electrically connects with substrate 202 through projection 206.The generation type of projection 206 of the present invention for example is the tie lines projection (studbump) that the general routing processing procedure of utilization forms; Perhaps can be to utilize the formed metal coupling of other plating modes, perhaps can be to form the glue material projection that contains metal with modes such as coating, wire marks.
In addition, can optionally between chip 204 and substrate 202, dispose adhesion coating 218, and make adhesion coating 218 around projection 206.The material of adhesion coating 218 is for example for having the thermosetting cement material of second-order characteristics (B stage).In addition, on the soldered ball 209 configuration solder ball pads 214.Packing colloid 208 coating chips 204, projection 206, weld pad 212, weld pad 216 and adhesion coating 218, and fill up opening 210.The material of packing colloid 208 for example is an epoxy resin.At length say; In the process that forms packing colloid 208; Packing colloid 208 on directly overlaying substrate 202; Also can get between chip 204 and the circuit board 202,, promote reliability with the bonding area that increases packing colloid and substrate to coat projection 206, weld pad 212 and weld pad 216 through opening 210.
From the above; Because chip 204 is to be disposed on the circuit board 202 and through the projection 206 between chip 204 and substrate 202 with the mode of covering crystalline substance chip 204 and substrate 202 are electrically connected; That is to say that chip 204 and projection 206 are positioned at the same side of substrate 202; Therefore make the path contraction that chip 204 and substrate 202 electrically connect, and then can increase the electrical transmitting speed between chip 204 and the substrate 202.
Fig. 3 is the generalized section according to the chip-packaging structure that another embodiment of the present invention illustrated.Please with reference to Fig. 3; Chip-packaging structure 300 comprises lead frame pin 302, chip 304, projection 306, adhesion coating 308, first packing colloid 310 and second packing colloid 312, and wherein first packing colloid 310 and second packing colloid 312 can be same material or different materials.Has opening 314 between the lead frame pin 302.Chip 304 has active surface and is positioned at the weld pad 316 on the active surface, and the active surface of chip 304 is towards lead frame pin 302.That is to say that chip 304 is to be disposed on the lead frame 302 to cover brilliant mode.Projection 306 is disposed between weld pad 316 and the lead frame pin 302, and connects weld pad 316 and lead frame pin 302.That is to say that chip 304 electrically connects with lead frame pin 302 through projection 306.Identical with the described embodiment of Fig. 2; Because chip 304 is to be disposed on the lead frame pin 302 and through the projection 306 between chip 304 and lead frame pin 302 with the mode of covering crystalline substance chip 304 and lead frame 302 are electrically connected; That is to say that the contact that connects chip 304 and lead frame pin 302 is positioned at the same side of lead frame pin 302; Therefore shortened the path of chip 304, to increase the electrical transmitting speed between chip 304 and the circuit board 302 with 302 electric connections of lead frame pin.
In addition, adhesion coating 308 is disposed between lead frame pin 302 and the chip 304, and coats projection 306 and weld pad 316.First packing colloid 310 is disposed in the opening 314, and second packing colloid, 312 coating chips 304 and adhesion coating 308.Say that at length in the process that forms chip-packaging structure 300, the present invention is prior to forming first packing colloid 310 in the opening 314 of lead frame pin 302.Then, chip 304 and lead frame pin 302 are electrically connected.Then, between chip 304 and lead frame 302, form adhesion coating 308.Owing to be formed with first packing colloid 310 in the opening 314, therefore can have avoided adhesion coating 308 to spill by opening 314.Afterwards, on lead frame pin 302, form second packing colloid 312 of coating chip 304 and adhesion coating 308, to accomplish the making of chip-packaging structure 300.In the present embodiment, the material of first packing colloid 310 and second packing colloid 312 for example is an epoxy resin.
In sum; The contact that the present invention will connect chip and substrate (or lead frame pin) is arranged at the same side of substrate (or lead frame pin); And utilize the mode of covering crystalline substance that chip and substrate (or lead frame pin) are electrically connected through projection; Therefore can shorten the path that chip and substrate (or lead frame pin) electrically connect,, and then improve element efficiency with the electrical transmitting speed between increase chip and the substrate (or lead frame pin).
Though the present invention discloses as above with embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion with what claim defined.
Claims (4)
1. chip-packaging structure comprises:
A plurality of lead frame pins have at least one opening between those lead frame pins;
One chip has an active surface and is positioned at a plurality of weld pads on this active surface, and wherein this active surface of this chip is towards those lead frame pins;
A plurality of projections are disposed between those weld pads and those lead frame pins, and connect those weld pads and this lead frame;
One adhesion coating is disposed between those lead frame pins and this chip, and coats those projections;
One first packing colloid is disposed in this at least one opening, and wherein this first packing colloid coats whole sides of those lead frame pins; And
One second packing colloid coats this chip and this adhesion coating;
Wherein this adhesion coating is arranged on this first packing colloid of this opening.
2. chip-packaging structure as claimed in claim 1 is characterized in that, this adhesion coating comprises the thermosetting cement material with second-order characteristics.
3. chip-packaging structure as claimed in claim 1 is characterized in that the material of this first packing colloid comprises epoxy resin.
4. chip-packaging structure as claimed in claim 1 is characterized in that the material of this second packing colloid comprises epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810083178A CN101527292B (en) | 2008-03-04 | 2008-03-04 | Chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810083178A CN101527292B (en) | 2008-03-04 | 2008-03-04 | Chip packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101527292A CN101527292A (en) | 2009-09-09 |
| CN101527292B true CN101527292B (en) | 2012-09-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810083178A Active CN101527292B (en) | 2008-03-04 | 2008-03-04 | Chip packaging structure |
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| Country | Link |
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| CN (1) | CN101527292B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104934188B (en) * | 2010-08-26 | 2018-04-10 | 乾坤科技股份有限公司 | Electronic packaging structure and packaging method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6384472B1 (en) * | 2000-03-24 | 2002-05-07 | Siliconware Precision Industries Co., Ltd | Leadless image sensor package structure and method for making the same |
| CN1921099A (en) * | 2005-08-23 | 2007-02-28 | 南茂科技股份有限公司 | Integrated circuit packaging structure with pins on chip and its chip carrier |
-
2008
- 2008-03-04 CN CN200810083178A patent/CN101527292B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6384472B1 (en) * | 2000-03-24 | 2002-05-07 | Siliconware Precision Industries Co., Ltd | Leadless image sensor package structure and method for making the same |
| CN1921099A (en) * | 2005-08-23 | 2007-02-28 | 南茂科技股份有限公司 | Integrated circuit packaging structure with pins on chip and its chip carrier |
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| Publication number | Publication date |
|---|---|
| CN101527292A (en) | 2009-09-09 |
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