CN2069171U - Pressure Sensors with Silica Isolation Structure - Google Patents

Abstract

The utility model belongs to the field of semiconductor pressure sensors. Including the silicon chip, the bottom plate for mounting the chip, the socket, the lead wire, etc., there is a silicon dioxide dielectric layer obtained by the porous silicon oxidation method as an isolation layer between the piezoresistive device and the silicon substrate. The isolation layer has excellent isolation performance, very little leakage current, and the breakdown voltage between the two separated devices exceeds 200 volts. The sensor not only maintains the high sensitivity characteristics of the single crystal silicon pressure sensor, but also can work in a high temperature environment.

Description

The utility model belongs to the field of semiconductor pressure sensors. It is a pressure sensor with a silicon dioxide isolation structure.

In traditional semiconductor pressure sensors, piezoresistive devices are generally fabricated on single crystal silicon substrates, which have the advantages of high sensitivity and low cost. However, because the piezoresistive device adopts a p-n junction isolation structure, when the working environment temperature is higher than about 120°C, the device cannot work normally due to the sudden increase of the leakage current in the device. This limits the application range of this type of pressure sensor. In recent years, some SOI (Silicon-on-Insulator) structural pressure sensors have been proposed. They are mainly polysilicon pressure sensors and SOS (Silicon-on-Sapphire) pressure sensors. Although they can all be used at higher temperatures, polysilicon pressure sensors have low pressure sensitivity (about 1/3 to 1/4 of that of single crystal silicon pressure sensors), and SOS pressure sensors are difficult to process due to heterogeneous structures. The cost is higher, so their application is also subject to greater restrictions.

The purpose of the utility model is to provide a semiconductor pressure sensor which can not only maintain the high sensitivity characteristic of the single crystal silicon semiconductor pressure sensor, but also can withstand high temperature working environment.

The pressure sensor includes a silicon chip, a bottom plate for installing the chip, a tube seat, and lead wires. The silicon chip includes a piezoresistive device and a silicon substrate, with a silicon dioxide dielectric layer between them as an isolation layer. The isolation layer is obtained by the porous silicon oxidation method, the width is 8-50 microns, and the depth is 2-5 microns. The piezoresistive device is a single crystal silicon layer fabricated on a silicon dioxide dielectric layer. Due to the excellent isolation performance of the silicon dioxide dielectric layer, the leakage current is very small, and the breakdown voltage between two discrete devices exceeds 200 volts. Therefore, the pressure sensor with this structure can be used in high temperature working environment (up to 350°C). And because the piezoresistive device of the sensor is a thin layer of single crystal silicon, it maintains the high sensitivity characteristics of the single crystal silicon pressure sensor.

The above-mentioned chip structure can be used to make a full-bridge piezoresistive pressure sensor, and can also be used to make a transverse piezoresistive pressure sensor. The former requires the isolation width of the silicon dioxide isolation layer to be 8-15 microns, and the latter requires the isolation width to be 35-50 microns. The design rules and process of the device are similar to those of the corresponding full-bridge piezoresistive sensor and single crystal lateral piezoresistive pressure sensor.

Accompanying drawing 1 is the cross-sectional view of the structure of the chip at the part of the piezoresistive device. The oblique line in the figure is the silicon dielectric layer formed by the oxidation of porous silicon. It is formed by selective anode after using antimony diffusion buried layer 4, concentrated boron diffusion isolation 2, n-type and p-type two-layer epitaxy 3 and other means. oxidation reaction and rapid oxidation of porous silicon. The single crystal silicon piezoresistive device 1 is isolated by silicon dioxide layers around and at the bottom. 5 is a silicon substrate. Piezoresistive devices are generally designed in areas where the stress of the silicon film is greater. Taking the rectangular film as an example, the four force sensitive resistors of the piezoresistive full bridge can be respectively arranged at the center and edge of the film, as shown in Figure 2. The lateral piezoresistive device can generally be arranged at the center of the film, as shown in FIG. 3 . In accompanying drawings 2 and 3, 6 is a rectangular silicon film, and 1 is a piezoresistive device.

The implementation method of the scheme is as follows: select a p-type polished single crystal silicon wafer with (100) crystal orientation; the antimony in the buried layer diffuses to form a strong n-type buried layer, which acts as a barrier layer during the anodization reaction of p-type silicon; P-type single crystal silicon and n-type single crystal silicon with a thickness of 1 to 2 microns, the thickness of the upper n-type epitaxial layer determines the thickness of the piezoresistive device, and the lower p-type epitaxial layer determines the thickness of the isolation oxide layer; boron isolation diffusion in A p-type isolation ring is formed around the piezoresistive device (n-type island); the anodization reaction is carried out in a double-chamber anodization reactor to convert the p-type silicon around and at the bottom of the n-type island into porous silicon; thermal oxidation converts the porous silicon for silicon dioxide. According to the conventional piezoresistive sensor manufacturing process, concentrated boron diffusion, boron ion implantation, anisotropic corrosion of aluminum leads and back silicon film, etc., and finally after a certain package, a porous silicon oxide film that can be used in high temperature environments is formed. Method SOI structure pressure sensor. Fig. 4 is its assembly structure diagram, in which 7 is a silicon chip, 8 is a glass base plate, 9 is a socket, and 10 is a lead wire.

FIG. 1 is a cross-sectional view of the structure of the silicon chip at the piezoresistive device.

Figure 2 is a setup diagram of a full-bridge piezoresistive force sensor.

FIG. 3 is a setup diagram of a lateral piezoresistive device.

FIG. 4 is a schematic diagram of the assembly structure of the pressure sensor.

Claims (3)

1. A silicon semiconductor pressure sensor, comprising a silicon chip, a base plate for installing a chip, a socket, and a lead wire, is characterized in that there is a silicon dioxide isolation layer between the piezoresistive device on the silicon chip and the silicon substrate, the The isolation layer has a width of 8-50 microns and a depth of 2-5 microns. 2. The silicon semiconductor pressure sensor according to claim 1, characterized in that the silicon dioxide interlayer has a width of 8-15 microns, forming a full-bridge piezoresistive pressure sensor. 3. The silicon semiconductor pressure sensor according to claim 2, characterized in that the silicon dioxide isolation layer has a width of 35-50 microns, constituting a lateral piezoresistive pressure sensor.

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