CN212010933U

CN212010933U - Semiconductor device prepared by using diffusion type SOI silicon chip

Info

Publication number: CN212010933U
Application number: CN202020397909.6U
Authority: CN
Inventors: 杨朔
Original assignee: Shanghai Anwei Electronics Co ltd
Current assignee: Shanghai Anwei Electronics Co ltd
Priority date: 2020-03-25
Filing date: 2020-03-25
Publication date: 2020-11-24
Anticipated expiration: 2030-03-25

Abstract

The utility model mainly aims at providing a semiconductor device prepared by using a diffusion type SOI silicon chip, which adopts a shallow junction diffusion silicon chip and a substrate silicon chip which plays a supporting role to replace an epitaxial wafer or a deep junction diffusion wafer with high cost through an insulating layer such as silicon dioxide bonding, thereby reducing the cost; and the back electrode is led to the front side, which is coplanar with the other front electrodes. In the manufacturing process, the active region silicon wafer is diffused firstly, and then the oxidation layer is bonded with the substrate silicon wafer to serve as a support, so that a high-low concentration transition region is reduced, and a high-concentration layer on the back can be led to the front through the diffusion high-concentration outer ring layer to form an electrode. The structure can be widely used for leading the electrodes of the vertically conducted semiconductor devices to the same surface, can form low-cost surface mounting devices, and has wide application.

Description

Semiconductor device prepared by using diffusion type SOI silicon chip

Technical Field

The utility model belongs to the technical field of semiconductor device, especially, relate to an use diffusion type SOI bonded silicon chip and at the semiconductor device who forms the electrode on one side.

Background

The semiconductor discrete device is divided into a horizontal conduction mode and a vertical conduction mode, the horizontal conduction device can be formed by electrodes on the same surface, but the current conduction capability is poor, the power is low, and the chip area is large; the vertical conduction device is suitable for high-power application and has strong current conduction capability, but the electrodes are distributed on the front surface and the back surface and are not suitable for novel packaging such as CSP and the like.

Methods of substrate growth for vertically conducting devices generally have three modes: 1. and (4) epitaxial growth. A low-concentration layer grows on a high-concentration high-purity single crystal wafer in an epitaxial growth mode, and an active region chip is manufactured on the low-concentration layer, as shown in figure 1, the mode is simple, the grown epitaxial layer and a substrate concentration transition region are narrow, and the on-resistance is small. The disadvantage is the high growth cost, especially for thick epitaxy, which increases with increasing thickness; the manufactured device is not as good as a single chip in the aspects of reverse voltage withstand voltage and reverse leakage; the quality of the substrate used is demanding. 2. Triple diffusion growth mode. High-concentration impurities are diffused on the two sides of the single crystal wafer, for example, phosphorus diffusion is carried out to form an N +/boron diffusion to form a P + layer, then high-temperature long-time diffusion is carried out, in order to achieve the thickness of a supporting effect, the junction depth generally reaches more than 150 microns, the high temperature is required to be more than 1280 ℃ for one week, and then single-side thinning and polishing are carried out, as shown in figures 2a-2 b. The advantages are low manufacturing cost and good quality of single crystal layer; the disadvantage is that the formed transition region is wide, usually more than 50um, resulting in large on-resistance; the diffusion period is long; the quality requirement of the single crystal is high. 3. Direct silicon wafer bonding mode: the two silicon chips are directly bonded to form an N-/N + or P-/P + type. The method has the advantages of low cost and the defect that the bonding surface of two silicon wafers must be polished, and the control requirements of the polished surface such as the thickness of an oxide layer, particles and the like are high, as shown in figure 3.

SUMMERY OF THE UTILITY MODEL

The main object of the present invention is to provide a semiconductor device with a novel electrode on the same side, which uses a low-cost easy-to-manufacture diffusion type SOI (silicon wafer-oxide layer-silicon wafer bonding) silicon wafer as a substrate, the silicon wafer used in the device is a shallow junction diffusion silicon wafer and a supporting substrate silicon wafer bonded by an insulating layer such as silicon dioxide, and an active region is formed on the diffusion sheet; all the electrodes are formed on the same surface; the high concentration layer on the back of the diffusion sheet is used as a back electrode and is led to the front through the high concentration layer with the same type to form an electrode. As shown in fig. 4. 10 is a substrate silicon wafer, 20 is a thick oxidation layer, 30 is a diffused high-concentration layer, 40 is a low-concentration single crystal layer, 41 is a schematic diagram of an active region of a manufactured chip, 50 is a diffused high-concentration layer, the type of impurities is the same as that of the 30 layers, 30 layers of current is led to the front side and is connected with 60 layers of metal electrodes, 70 is other electrodes, and 80 is an insulating masking layer.

The substrate silicon wafer can adopt a semiconductor grade purity single wafer or a solar photovoltaic grade purity single wafer.

The manufacturing method comprises the following steps: firstly, diffusing an upper silicon wafer to form a high-concentration region, a transition region and a low-concentration region, and thermally growing an oxide layer; forming an oxide layer on the substrate silicon wafer, wherein the oxide layer is a hydrophilic surface; aligning the two sheets, pressurizing and attaching the two sheets, and carrying out low-temperature annealing bonding. And the diffusion silicon wafer layer thins and polishes the low-concentration layer as required, and impurities of the same type are diffused at the edge of the tube core to form a high-concentration layer serving as a low-impedance conduction channel so as to lead the electrode to the upper surface. As shown in fig. 5a-5 d. And manufacturing devices such as diodes, triodes, MOSFETs and the like on the low-concentration layer.

The substrate adopts a substrate silicon wafer and a shallow junction diffusion silicon wafer to bond to replace an epitaxial wafer or a deep junction diffusion wafer with high cost, so that the cost is reduced, the thinning is easy, and the high-low concentration transition region is reduced; the thick oxide layer is used as a bonding interface, and is easy to attach at low temperature due to the hydrophilic surface, and the oxide layer can form a cavity in the middle of the flow filling through high-temperature annealing (>1000 ℃), so that the bonding force is increased. The bonding surface of the silicon chip can be a polished surface or a non-polished surface, and the manufacturing is simple.

The coplanar electrodes are used to direct the bottom current to the front by diffusing the high concentration impurities to form a low impedance conduction path 50 that connects to the diffuser bottom high concentration region 30.

The coplanar electrode can be widely used for leading the electrode of the vertically conducted semiconductor device to the same surface, can adopt the CSP packaging type to form a low-cost surface mounting device, and has wide application.

The utility model discloses a preparation method of coplanar electrode device of novel bonded silicon chip, its step includes: the method comprises the following steps of N +/P + type substrate piece-hydrophilic surface treatment-N-/P-type single chip-diffusion oxidation high-concentration N +/P + layer-two piece bonding-baking at a low temperature of 100 ℃ and more than 2 hours at a high temperature of 1000 ℃ for 2 hours, diffusion piece thinning-polishing-oxidation-photoetching corrosion conduction channel-diffusion N +/P + layer is connected with the bottom of the diffusion piece to form other chip internal structures and front electrodes.

Drawings

Figure 1 is a standard epitaxial wafer structure.

FIGS. 2a-2b are schematic diagrams of triple diffusers fabrication.

Fig. 3 is a view showing a structure of a direct bonding sheet.

Fig. 4 is a view of the structure of the device of the present invention.

Fig. 5a-5d are schematic diagrams illustrating the manufacturing process of the device of the present invention.

Detailed Description

The present invention is further illustrated by the following specific examples, which do not limit the scope of the present invention.

Examples

Taking a single-side polished N-type single crystal wafer (with the resistivity of 2 omega cm and the thickness of 300um), introducing a POCL3 diffusion source for 30 minutes at 1100 ℃, oxidizing, and enabling an oxide layer to be 0.5um in thickness, taking another N + type single crystal wafer (with the thickness of 450um) for chemical corrosion, carrying out RCA cleaning, boiling concentrated nitric acid, drying, bonding the two wafers, drying in a 200 ℃ oven for 2 hours, then placing in a diffusion furnace for 6 hours at 1200 ℃, and thinning and polishing until the thickness of an N-region is 8um., wherein the obtained diffusion region is 13um and the width of a transition region is 4 um. Oxidizing the polished surface to 1000 ℃ to 1um thickness, photoetching to conduct a channel, corroding an oxide layer, introducing a POCL3 diffusion source at 1100 ℃ for 30 minutes, then placing the diffusion source in a diffusion furnace at 1200 ℃ for 5 hours, wherein the obtained diffusion region is 10um and is connected with a diffusion sheet N + region. The other steps adopt a general plane Schottky diode manufacturing method, the obtained diode has reverse cut-off (breakdown) voltage of 138V, reverse leakage current of 1uA and forward voltage drop of 0.82V, and electrodes are formed on the front surface.

Of course, those skilled in the art should realize that the above embodiments are only used for illustrating the present invention, and not as a limitation of the present invention, and that the changes and modifications to the above embodiments are all within the scope of the claims of the present invention as long as they are within the spirit and scope of the present invention.

Claims

1. A semiconductor device manufactured using a diffusion type SOI silicon wafer is characterized by a structure comprising: a shallow junction diffusion silicon wafer, a substrate silicon wafer for supporting, a silicon dioxide layer for bonding, and a vertical conduction semiconductor device of a coplanar electrode formed by leading a back electrode to a high concentration layer on the front surface.

2. The semiconductor device according to claim 1, wherein the silicon wafer used is a shallow junction diffused silicon wafer and the supporting silicon wafer is a silicon dioxide-bonded silicon substrate, and the active region is formed on the diffused silicon wafer.

3. The semiconductor device of claim 1, wherein said shallow junction diffused silicon is less than 50 microns deep.

4. A semiconductor device fabricated using a diffusion-type SOI wafer as defined in claim 1 wherein all electrodes are formed on the same surface, and the diffusion sheet back high concentration layer is introduced as a back electrode to the front surface through the same type of high concentration layer to form a front surface electrode.