CN104103514A - Method for manufacturing vertical groove current regulative diode - Google Patents

Abstract

The invention provides a method for manufacturing a vertical channel constant current diode, which is characterized in that an N-type silicon single wafer is used as the substrate material, and there are two P+ diffusion regions on the front of the chip, and an N+ diffusion region is sandwiched between the two P+ diffusion regions. Diffusion region, P+ region and N+ region are connected to the negative electrode metal through the oxide layer window. The back of the chip is thinned, and the high-concentration P+ injection layer on the back is connected to the positive electrode metal.

Description

A method of manufacturing a vertical channel constant current diode

technical field

The invention relates to the technical field of semiconductors, in particular to a vertical channel constant current diode.

Background technique

The constant current diode is a semiconductor constant current device that has come out in recent years. It outputs a constant current in a wide voltage range and has a high dynamic impedance. Because of its good constant current performance, low price, and easy use, it has been widely used in constant current sources, voltage regulators, amplifiers, and protection circuits for electronic instruments, especially for LED (Light Emitting Diode) drivers. Constant current diodes are currently the more common way.

At present, vertical channel constant current diodes use an N-type epitaxial layer grown on a P-type substrate as the substrate material to prepare the diode. Epitaxial wafers are more expensive than single wafers.

Contents of the invention

The object of the present invention is to provide a method for preparing a vertical channel constant current diode using a silicon single crystal substrate.

The technical scheme of the present invention is: a low-doping concentration N-type silicon single wafer is used as the substrate material, and two P+ diffusion regions and two P+ diffusion regions are formed on the front surface of the substrate material through photolithography, diffusion and other processes. An N+ diffusion region is sandwiched between them. The surface of the chip is covered with an insulating oxide layer, and windows are opened at the P+ region and the N+ region through the photolithography process, and the P+ region and the N+ region are connected to the negative electrode metal through the window through the metallization process.

After the preparation of the front negative electrode structure of the constant current diode is completed, the back of the substrate material is thinned through a thinning process to reduce the thickness of the constant current diode chip, and the back is injected with boron through a high-dose implantation process to form a high concentration after annealing. P+ injection layer, and then use the back metallization process to form the positive electrode of the constant current diode.

The advantages and positive effects of the invention are: using silicon single wafer as the substrate material, compared with the traditional epitaxial wafer substrate technology, the manufacturing cost of the constant current diode chip can be reduced. In addition, the method of backside thinning and injection annealing adopted by the present invention greatly reduces the thickness of the whole diode chip, so that the thermal resistance performance of the constant current diode is improved, and the current temperature coefficient (α T, the relative change of the constant current caused by the unit temperature change) percentage) becomes smaller.

Description of drawings

Figure 1 is a schematic diagram of the structure after the P+ injection window is cut open

Figure 2 is a schematic diagram of the structure after the formation of the P+ diffusion region and the opening of the N+ implantation window

Figure 3 is a schematic diagram of the structure after the contact holes of the P+ region and the N+ region are cut.

Figure 4 is a schematic diagram of the structure after the preparation of the positive and negative electrodes

Figure 5 is a schematic diagram of the structure after back thinning

Figure 6 is a schematic diagram of the vertical channel diode chip structure

The drawings are marked as: 1—N-type silicon single crystal substrate, 2—P+ diffusion region, 3—N+ diffusion region, 4—insulating oxide layer, 5—negative electrode metal, 6—P+ injection layer, 7—positive electrode Metal.

Detailed ways

Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail

Step 1: Use N-silicon single crystal substrate 1 with low doping concentration, first grow oxide layer 4, and open P+ implantation window by photolithography process, as shown in FIG. 1 .

Step 2: After P+ implantation, push junction to form P+ diffusion region 2 through high-temperature diffusion oxidation process, and generate insulating oxide layer 4 at the same time, and then open N+ implantation window on oxide layer 4 through photolithography process, as shown in Figure 2.

Step 3: After N+ implantation, push the junction to form the N+ region 3 and the insulating oxide layer 4 through the high temperature diffusion oxidation process, and then pass the photolithography process again to carve the P+ diffusion region 2 and the oxide layer 4 above the N+ diffusion region 3 Electrode contact holes, as shown in Figure 3.

Step 4: Form the negative electrode of the diode by evaporating or sputtering metal, and the negative electrode is short-circuited with the P+ diffusion region 2 and the N+ diffusion region 3, as shown in FIG. 4 .

Step 5: Thinning the back of the N-silicon single crystal substrate 1 , and performing high-concentration P+ implantation on the back after the thinning, as shown in FIG. 5 .

Step 6: After P+ implantation and annealing on the back side, the P+ injection layer 6 is formed, and then the metal is evaporated on the back side to form the positive electrode 7. The schematic diagram of the entire constant current diode structure is shown in FIG. 6 .

Claims (4)

1. A method for manufacturing a vertical channel constant current diode, characterized in that substrate 1 is an N-type silicon single crystal, and there are two P+ diffusion regions 2 on the N-substrate 1 front, and one between the two P+ diffusion regions. The N+ diffusion region 3 has an insulating oxide layer 4 on the surface, and has windows in the P+ region 2 and the N+ region 3 respectively, the P+ region 2 and the N+ region 3 are connected to the negative electrode metal 5 through the window, and the back of the N-substrate 1 has The P+ injection layer 6 is connected to the positive electrode metal 7 . 2. A method for manufacturing a vertical channel constant current diode according to claim 1, wherein the substrate 1 is a low-doped N-type silicon wafer. 3. A method for manufacturing a vertical channel constant current diode according to claim 1, wherein a high-concentration P+ implantation layer 6 is formed on the backside thereof through an implantation annealing process. 4 . A method for manufacturing a vertical channel constant current diode according to claim 1 , before the P+ implantation on the back side, the back side of the substrate 1 should be thinned.