CN204516362U - Embedded storage chip, EMBEDDED AVIONICS - Google Patents

Abstract

The utility model relates to an embedded memory chip. The embedded memory chip includes a body, a control integrated circuit grain encapsulated in the body, a Nand Flash storage integrated circuit grain electrically connected to the control integrated circuit grain and a first interface contact, and the first interface The contact is arranged on the body; it also includes the SPI Nor Flash storage integrated circuit grain encapsulated in the body and the second interface contact point that is electrically connected to it and is arranged on the body; the second interface is an SPI interface, and the first The two interface contacts include at least 6 contacts of power line, ground line, data output line, data input line, chip select line and clock line. The above-mentioned embedded memory chip encapsulates two storage integrated circuit grains, Nand Flash and SPI Nor Flash, in one chip, so that one chip has multiple storage functions, which is convenient for the design of printed circuit boards, and can effectively reduce the printed circuit board occupied by the chip. The area of the board, thereby saving the space of the printed circuit board, is convenient for the miniaturization design of the product.

Description

Embedded memory chips, embedded electronic devices

technical field

The utility model relates to a storage device, in particular to an embedded storage chip and an embedded electronic device.

Background technique

Existing electronic products such as smart watches, smart bracelets and other devices have more and more functions, but the space for internal circuits is really limited, and the products are becoming more and more thinner and miniaturized. Therefore, embedded Chip integration requirements are getting higher and higher, and when the existing embedded memory chips are used, an additional memory chip needs to be configured to store some programs such as startup codes. Occupies a certain area on the printed circuit board, thus limiting the further miniaturization of electronic products.

Utility model content

Based on this, it is necessary to provide a highly integrated embedded memory chip for the problem that the existing embedded memory chip structure limits the further miniaturization of embedded electronic devices.

In addition, it is also necessary to provide an embedded electronic device with a high degree of integration.

An embedded memory chip, comprising a body, a control integrated circuit grain and a NandFlash storage integrated circuit grain packaged in the body, and a first interface contact arranged on the body, the control integrated circuit grain is provided with a first Interface, the Nand Flash storage integrated circuit grain is electrically connected to the control integrated circuit grain, the first interface contact is electrically connected to the first interface, and the embedded memory chip also includes a The SPI Nor Flash storage integrated circuit crystal grain in, and the second interface contact point electrically connected with the SPINor Flash storage integrated circuit grain, the second interface contact point is arranged on the body, and the second interface contact point is The SPI interface contact, the second interface contact at least includes six contacts of a power line, a ground line, a data output line, a data input line, a chip select line, and a clock line.

In one of the embodiments, the second interface contact further includes a status maintaining line contact and a write protection line contact.

In one of the embodiments, the first interface is an SD interface, the first interface contact is an SD interface contact, and the first interface contact at least includes a power line, a ground line, a data line 0, a data line 1, a data line Line 2, data line 3, clock line, command line eight contacts.

In one of the embodiments, the first interface is a USB interface, the first interface contact is a USB interface contact, and the first interface contact includes at least four power lines, ground lines, positive data lines, and negative data lines. contact.

In one of the embodiments, the first interface is an eMMC interface, the first interface contact is an eMMC interface contact, and the first interface contact at least includes a power line 1, a power line 2, a ground wire, a clock line, a command line, reset line, 8 data lines and 14 contacts.

In one of the embodiments, the body of the embedded memory chip is provided with 30 contacts, in addition to the first interface contact and the second interface contact, it also includes core power line contacts and reserved power line contacts, and the remaining contacts are Reserved contacts not used temporarily.

In one of the embodiments, the length, width and height of the embedded memory chip are 8mm*8mm*0.8mm, wherein the tolerance of length and width is plus or minus 0.1mm, and the tolerance of height is plus or minus 0.01mm .

In one of the embodiments, the 30 contacts are evenly distributed in the center of the body surface in the form of 5 rows and 6 columns, and the contacts are circular pad contacts with a radius of 0.6 mm, wherein the contacts in the first column to the first The distance between the 6 columns of contacts is 6mm, the distance between the first row of contacts and the fifth row of contacts is 4.8mm, and the distance between two adjacent contacts is 1.2mm.

An embedded electronic device includes the above-mentioned embedded memory chip.

The above-mentioned embedded memory chips and embedded electronic devices package the Nand Flash storage integrated circuit grains and the SPI Nor Flash storage integrated circuit grains in one chip, and set the interface contacts of the SPINor Flash storage integrated circuit grains on the chip body , so that one chip has multiple storage functions, which is convenient for the design of printed circuit boards of embedded electronic devices, and can effectively reduce the area of printed circuit boards occupied by chips, thereby saving the space of printed circuit boards and facilitating the miniaturization design of products.

Description of drawings

Fig. 1 is a schematic diagram of the circuit structure of an embedded memory chip in an embodiment;

Fig. 2 is a schematic diagram of pad distribution of an embedded memory chip in one embodiment;

FIG. 3 is a schematic diagram of the structural dimensions of an embedded memory chip in an embodiment.

Detailed ways

In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model, and are not intended to limit the utility model.

FIG. 1 is a schematic diagram of a circuit structure of an embedded memory chip in an embodiment; FIG. 2 is a schematic diagram of a pad distribution in an embodiment. As shown in Figures 1 and 2, the embedded memory chip 10 includes a body 106, a control integrated circuit grain 101 and a Nand Flash storage integrated circuit grain 102 packaged in the body 106, and a first chip disposed on the body Interface contact 103, the control integrated circuit grain 101 is provided with a first interface, the Nand Flash storage integrated circuit grain 102 is electrically connected to the control integrated circuit grain 101, the first interface contact 103 is connected to the The first interface is electrically connected, and the embedded memory chip 10 also includes the SPI Nor Flash storage integrated circuit grain 104 packaged in the body 106, and the first electrically connected SPI Nor Flash storage integrated circuit grain 104. Two interface contacts 105, the second interface contacts 105 are arranged on the body 106, the second interface contacts 105 are SPI interface contacts, and the second interface contacts 105 at least include a power line (SPI-VCC), a ground Line (GND), data output line (SPI-DO), data input line (SPI-DI), chip select line (SPI-CS), clock line (SPI-CLK) 6 contacts.

In a specific embodiment, as shown in FIG. 2 , the second interface contact 105 further includes a state holding line contact (SPI-HOLD) and a write protection line contact (SPI-WP).

In a specific embodiment, as shown in FIG. 2, the first interface is an SD interface, the first interface contact 103 is an SD interface contact, and the first interface contact 103 includes at least a power line (VCCSD), Ground (GND), data line 0 (SDD0), data line 1 (SDD1), data line 2 (SDD2), data line 3 (SDD3), clock line (SDCLK), command line (SDCMD) eight contacts.

In a specific embodiment, the first interface is a USB interface, the first interface contact 103 is a USB interface contact, and the first interface contact 103 includes at least a power line, a ground line, a positive data line, a negative data Line four contacts.

In a specific embodiment, the first interface is an eMMC interface, the first interface contact 103 is an eMMC interface contact, and the first interface contact 103 includes at least a power line 1, a power line 2, a ground wire, and a clock line, command line, reset line, 8 data lines and 14 contacts.

In a specific embodiment, as shown in Figure 2, the body 106 of the embedded memory chip 10 is provided with 30 contacts, in addition to the first interface contact 104 and the second interface contact 105, it also includes a core power line contact (VDDK) and the reserved power line contact (VCCS), and the rest of the contacts are temporarily unused reserved contacts (DNU).

In a specific embodiment, the dimensions of the length, width, and height of the embedded memory chip are 8mm*8mm*0.8mm (mm: millimeter millimeter), wherein the tolerance of the length and width is plus or minus 0.1mm, and the height The tolerance size is plus or minus 0.01mm.

In a specific embodiment, the 30 contacts are uniformly distributed in the center of the body surface in the form of 5 rows and 6 columns, and the contacts are circular pad contacts with a radius of 0.6 mm, wherein the contacts in the first column are to The distance between the contacts in the sixth column is 6mm, the distance between the contacts in the first row and the contacts in the fifth row is 4.8mm, and the distance between two adjacent contacts is 1.2mm.

The above-mentioned embedded memory chip encapsulates the Nand Flash storage integrated circuit grain and the SPI Nor Flash storage integrated circuit grain in one chip, and sets the interface contacts of the SPI Nor Flash storage integrated circuit grain on the chip body, so that a chip With a variety of storage functions, it is convenient for the design of printed circuit boards of embedded electronic equipment, and can effectively reduce the area of printed circuit boards occupied by chips, thereby saving the space of printed circuit boards and facilitating the miniaturization design of products.

The utility model also provides an embedded electronic device, which includes the above-described embedded memory chip.

The above-mentioned embedded electronic device can realize multiple storage functions because only one memory chip is used, which saves the area of the printed circuit board and facilitates the miniaturization design of its products.

The above-mentioned embodiments only express several implementations of the utility model, and the description thereof is relatively specific and detailed, but it should not be construed as limiting the patent scope of the utility model. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the utility model patent should be based on the appended claims.

Claims (9)

1. an embedded storage chip, comprise body, be encapsulated in intrinsic control integration circuit die and Nand Flash storage integrated-circuit die, and the first interface contact be arranged on body, described control integration circuit die is provided with first interface, described Nand Flash stores integrated-circuit die and is electrically connected with described control integration circuit die, described first interface contact is electrically connected with described first interface, it is characterized in that, described embedded storage chip also comprises and is encapsulated in described intrinsic SPI Nor Flash and stores integrated-circuit die, and store with described SPI Nor Flash the second interface contact that integrated-circuit die is electrically connected, described second interface contact is arranged on the body, described second interface contact is SPI interface contact, described second interface contact at least comprises power lead, ground wire, DOL Data Output Line, Data In-Line, chip select line, clock line 6 contacts.

2. embedded storage chip according to claim 1, is characterized in that, described second interface contact also comprises state maintaining line contact and write-protect line contact.

3. embedded storage chip according to claim 1, it is characterized in that, described first interface is SD interface, described first interface contact is SD interface contact, and described first interface contact at least comprises power lead, ground wire, data line 0, data line 1, data line 2, data line 3, clock line, order wire eight contacts.

4. embedded storage chip according to claim 1, it is characterized in that, described first interface is USB interface, and described first interface contact is USB interface contact, and described first interface contact at least comprises power lead, ground wire, correction data line, negative data line four contacts.

5. embedded storage chip according to claim 1, it is characterized in that, described first interface is eMMC interface, described first interface contact is eMMC interface contact, and described first interface contact at least comprises power lead 1, power lead 2, ground wire, clock line, order wire, reset line, 8 data lines, 14 contacts.

6. the embedded storage chip according to any one of claim 1-5, it is characterized in that, the body of described embedded storage chip is provided with 30 contacts, except first interface contact and the second interface contact, also comprise the power cord point of core power line contact and reservation, all the other contacts are the stick contact temporarily do not used.

7. embedded storage chip according to claim 6, is characterized in that, described embedded storage chip length is of a size of 8mm*8mm*0.8mm, wherein the positive and negative 0.1mm of the tolerance dimension of length and width, and high tolerance dimension is in positive and negative 0.01mm.。

8. embedded storage chip according to claim 6, it is characterized in that, the mode that described 30 contacts arrange by 5 row 6 is uniformly distributed between two parties at described body surface, described contact is circular pad contact, radius is 0.6mm, wherein the 1st row contact is 6mm to the distance of the 6th row contact, and the 1st row contact is 4.8mm to the distance of the 5th row contact, and the distance of adjacent two contacts is 1.2mm.

9. an EMBEDDED AVIONICS, is characterized in that, described EMBEDDED AVIONICS comprises the embedded storage chip according to any one of claim 1-8.