CN204516361U - Embedded storage chip, EMBEDDED AVIONICS - Google Patents

Abstract

The utility model relates to an embedded storage chip, which comprises a body, a first interface contact arranged on the body, a control integrated circuit crystal grain and a Nand Flash storage integrated circuit crystal grain packaged in the body, and the Nand Flash storage integrated circuit The crystal grain and the first interface contact are respectively electrically connected to the control integrated circuit grain; the control integrated circuit grain is provided with an SPI interface, and the body is also provided with an SPI interface contact, and the SPI interface contact is connected to the SPI interface Electrical connection, including at least 6 contacts of power line, ground line, data output line, data input line, chip select line, and clock line. The above-mentioned embedded memory chip adds an SPI interface on the control integrated circuit grain, and the external electronic device can quickly obtain the code data required for startup through the SPI interface, so that the external electronic device no longer needs to be equipped with an additional SPI Nor Flash memory chip , reducing the production cost of external electronics.

Description

Embedded memory chips, embedded electronic devices

technical field

The utility model relates to a storage device, in particular to an embedded storage chip and an embedded electronic device.

Background technique

Existing embedded electronic devices such as smart watches, smart bracelets, etc. have more and more functions, but the space for internal circuits is limited, and the products are becoming more and more thinner and miniaturized. The integration level of the chip is getting higher and higher, and when the existing embedded memory chip is used, it is necessary to configure another SPI Nor Flash memory chip to store some programs such as startup codes. In this way, due to the embedded memory chip and SPI Nor Flash memory chips all need to occupy a certain area on the printed circuit board, thus limiting the further miniaturization of electronic products. And because embedded electronic devices such as smart watches and smart bracelets need to use two types of memory chips, the cost of the embedded electronic devices will inevitably be pushed up.

Utility model content

Based on this, it is necessary to provide a new type of embedded memory chip to solve the problem that the existing embedded memory chip structure limits the further miniaturization of embedded electronic equipment.

In addition, it is also necessary to provide a new type of embedded electronic device.

An embedded memory chip, comprising a body, a control integrated circuit grain and a Nand Flash storage integrated circuit grain packaged in the body, and a first interface contact arranged on the body, the control integrated circuit grain is provided with a first An interface, the Nand Flash storage integrated circuit grain is electrically connected to the control integrated circuit grain, the first interface contact is electrically connected to the first interface, and the control integrated circuit grain is also provided with a second Interface, the embedded memory chip also includes a second interface contact electrically connected to the second interface arranged on the body, the second interface is an SPI interface, and the second interface contact is an SPI interface contact, so The second interface contacts include at least 6 contacts of power line, ground line, data output line, data input line, chip select line and clock line.

In a specific embodiment, the second interface contact further includes a state maintenance line contact and a write protection line contact.

In a specific embodiment, the first interface is an SD interface, the first interface contact is an SD interface contact, and the first interface contact at least includes a power line, a ground line, a data line 0, a data line 1, Eight contacts for data line 2, data line 3, clock line, and command line.

In a specific embodiment, the first interface is a USB interface, the first interface contact is a USB interface contact, and the first interface contact at least includes a power line, a ground line, a positive data line, and a negative data line. contacts.

In a specific embodiment, the first interface is an eMMC interface, the first interface contact is an eMMC interface contact, and the first interface contact at least includes a power line 1, a power line 2, a ground line, a clock line, Command line, reset line, 8 data lines and 14 contacts.

In a specific embodiment, the body of the embedded memory chip is provided with 30 contacts, in addition to the first interface contact and the second interface contact, it also includes core power line contacts and reserved power line contacts, and the remaining contacts Reserved for temporary unused contacts.

In a specific embodiment, the length, width and height of the embedded memory chip are 8mm*8mm*0.8mm, the tolerance of length and width is plus or minus 0.1mm, and the tolerance of height is plus or minus 0.01mm .

In a specific embodiment, the length, width and height of the embedded memory chip are 8mm*7.5mm*0.8mm, the tolerance of length and width is plus or minus 0.1mm, and the tolerance of height is plus or minus 0.01 mm.

In a specific embodiment, the 30 contacts are evenly distributed in the center of the body surface in the form of 5 rows and 6 columns, and the contacts are circular pad contacts or spherical contacts or hemispherical contacts with a radius of 0.6mm , where the distance from the first row of contacts to the sixth row of contacts is 6mm, the distance from the first row of contacts to the fifth row of contacts is 4.8mm, and the distance between two adjacent contacts is 1.2mm.

An embedded electronic device includes the above-mentioned embedded memory chip.

Above-mentioned embedded storage chip, embedded electronic equipment, by setting an SPI interface on the control integrated circuit grain, can store the startup code of external electronic equipment in the storage space that Nand Flash stores integrated circuit grain, external electronic equipment The code data required for startup can be quickly obtained through the SPI interface, so that the external electronic device no longer needs to be equipped with an additional SPI Nor Flash memory chip, which reduces the production cost of the external electronic device; at the same time, due to the reduction of the SPI Nor Flash memory chip The use of can reduce the area occupied by the printed circuit board of the external electronic equipment, and facilitate the miniaturization design of the external electronic equipment; further, since the embedded memory chip has the first interface, the external electronic equipment can pass through the first interface. Copy the upgrade program to the embedded memory chip to copy and upgrade, compared with the traditional SPI Nor Flash memory chip through burning and upgrading, it greatly facilitates the use of ordinary users.

Description of drawings

Fig. 1 is a schematic diagram of the circuit structure of an embedded memory chip in an embodiment;

Fig. 2 is a schematic diagram of pad distribution of an embedded memory chip in one embodiment;

FIG. 3 is a schematic diagram of the structural dimensions of an embedded memory chip in an embodiment.

Detailed ways

In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model, and are not intended to limit the utility model.

FIG. 1 is a schematic diagram of a circuit structure of an embedded memory chip in an embodiment; FIG. 2 is a schematic diagram of pad distribution of an embedded memory chip in an embodiment. As shown in Figures 1 and 2, the embedded memory chip 10 includes a body 105, a control integrated circuit grain 101 and a Nand Flash storage integrated circuit grain 102 packaged in the body 105, and a first chip disposed on the body Interface contact 103, the control integrated circuit grain 101 is provided with a first interface, the Nand Flash storage integrated circuit grain 102 is electrically connected to the control integrated circuit grain 101, the first interface contact 103 is connected to the The first interface is electrically connected, the control integrated circuit die 101 is also provided with a second interface, and the embedded memory chip 10 also includes a second Interface contact 104, described second interface is SPI interface, and described second interface contact 104 is SPI interface contact, and described second interface contact 104 at least comprises power line (SPI-VCC), ground wire (GND), data output Line (SPI-DO), data input line (SPI-DI), chip select line (SPI-CS), clock line (SPI-CLK) 6 contacts.

In a specific embodiment, as shown in FIG. 2 , the second interface contact 104 further includes a state holding line contact (SPI-HOLD) and a write protection line contact (SPI-WP).

In a specific embodiment, as shown in FIG. 2, the first interface is an SD interface, the first interface contact 103 is an SD interface contact, and the first interface contact 103 includes at least a power line (VCCSD), Ground (GND), data line 0 (SDD0), data line 1 (SDD1), data line 2 (SDD2), data line 3 (SDD3), clock line (SDCLK), command line (SDCMD) eight contacts.

In a specific embodiment, the first interface is a USB interface, the first interface contact 103 is a USB interface contact, and the first interface contact 103 includes at least a power line, a ground line, a positive data line, a negative data Line four contacts.

In a specific embodiment, the first interface is an eMMC interface, the first interface contact 103 is an eMMC interface contact, and the first interface contact 103 includes at least a power line 1, a power line 2, a ground wire, and a clock line, command line, reset line, 8 data lines and 14 contacts.

In a specific embodiment, as shown in FIG. 2, the body 105 of the embedded memory chip 10 is provided with 30 contacts, in addition to the first interface contact 103 and the second interface contact 104, it also includes a core power line contact (VDDK) and the reserved power line contact (VCCS), and the rest of the contacts are temporarily unused reserved contacts (DNU).

In a specific embodiment, as shown in Figure 3, the size of the embedded memory chip is 8mm*8mm*0.8mm (mm: millimeter millimeter), the tolerance of length and width is plus or minus 0.1mm, and the height The tolerance size is plus or minus 0.01mm. Of course, the embedded memory chip can also be of other sizes, which is not intended to limit the present invention.

In a specific embodiment, as shown in Figure 3, the 30 contacts are evenly distributed in the center of the surface of the body in the form of 5 rows and 6 columns, and the contacts are circular pad contacts or spherical contacts or hemispherical Contacts, the radius is 0.6mm, the distance from the first row of contacts to the sixth row of contacts is 6mm, the distance from the first row of contacts to the fifth row of contacts is 4.8mm, and the distance between two adjacent contacts is 1.2mm. Of course, the contacts can also be in other shapes, which are not intended to limit the present invention.

In another specific embodiment, the length, width and height of the embedded memory chip can also be 8mm*7.5mm*0.8mm, the tolerance of length and width is plus or minus 0.1mm, and the tolerance of height is Plus or minus 0.01mm.

The above-mentioned embedded memory chip, by setting an SPI interface on the control integrated circuit grain, can store the startup code of the external electronic device in the storage space provided by the Nand Flash storage integrated circuit grain, and the external electronic device can quickly pass through the SPI interface. Obtain the code data required at startup, so that the external electronic device no longer needs to configure an additional SPI Nor Flash memory chip, which reduces the production cost of the external electronic device; at the same time, due to the reduced use of the SPI Nor Flash memory chip, it can reduce The area occupied by the printed circuit board of the external electronic equipment is convenient for the miniaturization design of the external electronic equipment; further, since the embedded memory chip has the first interface, the external electronic equipment can copy the upgrade program to the Compared with the traditional SPI Nor Flash memory chip, the copying upgrade of the embedded memory chip greatly facilitates the use of ordinary users.

The utility model also provides an embedded electronic device, which includes the above-described embedded memory chip.

The embedded electronic devices are devices such as smart watches, smart bracelets, and tablet computers.

The embedded electronic device provided by the utility model does not need to configure a SPI Nor Flash memory chip separately, which can not only greatly reduce its hardware cost, but also facilitate the miniaturization design of its structure.

The above-mentioned embodiments only express several implementations of the utility model, and the description thereof is relatively specific and detailed, but it should not be construed as limiting the patent scope of the utility model. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the utility model, and these all belong to the protection scope of the utility model. Therefore, the scope of protection of the utility model patent should be based on the appended claims.

Claims (10)

1. an embedded storage chip, comprise body, be encapsulated in intrinsic control integration circuit die and Nand Flash storage integrated-circuit die, and the first interface contact be arranged on body, described control integration circuit die is provided with first interface, described Nand Flash stores integrated-circuit die and is electrically connected with described control integration circuit die, described first interface contact is electrically connected with described first interface, it is characterized in that, described control integration circuit die is also provided with the second interface, described embedded storage chip also comprises the second interface contact be electrically connected with described second interface be arranged on body, described second interface is SPI interface, described second interface contact is SPI interface contact, described second interface contact at least comprises power lead, ground wire, DOL Data Output Line, Data In-Line, chip select line, clock line 6 contacts.

2. embedded storage chip according to claim 1, is characterized in that, described second interface contact also comprises state maintaining line contact and write-protect line contact.

3. embedded storage chip according to claim 1, it is characterized in that, described first interface is SD interface, described first interface contact is SD interface contact, and described first interface contact at least comprises power lead, ground wire, data line 0, data line 1, data line 2, data line 3, clock line, order wire eight contacts.

4. embedded storage chip according to claim 1, it is characterized in that, described first interface is USB interface, and described first interface contact is USB interface contact, and described first interface contact at least comprises power lead, ground wire, correction data line, negative data line four contacts.

5. embedded storage chip according to claim 1, it is characterized in that, described first interface is eMMC interface, described first interface contact is eMMC interface contact, and described first interface contact at least comprises power lead 1, power lead 2, ground wire, clock line, order wire, reset line, 8 data lines, 14 contacts.

6. the embedded storage chip according to any one of claim 1-5, it is characterized in that, the body of described embedded storage chip is provided with 30 contacts, except first interface contact and the second interface contact, also comprise the power cord point of core power line contact and reservation, all the other contacts are the stick contact temporarily do not used.

7. embedded storage chip according to claim 6, is characterized in that, described embedded storage chip length is of a size of 8mm*8mm*0.8mm, and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.

8. embedded storage chip according to claim 6, is characterized in that, described embedded storage chip length is of a size of 8mm*7.5mm*0.8mm, and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.

9. the embedded storage chip according to claim 7 or 8, it is characterized in that, the mode that described 30 contacts arrange by 5 row 6 is uniformly distributed between two parties at described body surface, described interface contact is circular pad contact or spherical contact or dome shaped contact, radius is 0.6mm, wherein the 1st row contact is 6mm to the distance of the 6th row contact, and the 1st row contact is 4.8mm to the distance of the 5th row contact, and the distance of adjacent two contacts is 1.2mm.

10. an EMBEDDED AVIONICS, is characterized in that, described EMBEDDED AVIONICS comprises embedded storage chip as claimed in any one of claims 1-9 wherein.