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CN1828883A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1828883A
CN1828883A CNA2006100042029A CN200610004202A CN1828883A CN 1828883 A CN1828883 A CN 1828883A CN A2006100042029 A CNA2006100042029 A CN A2006100042029A CN 200610004202 A CN200610004202 A CN 200610004202A CN 1828883 A CN1828883 A CN 1828883A
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CN
China
Prior art keywords
distribution
dielectric film
opening
semiconductor
semiconductor substrate
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Granted
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CNA2006100042029A
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CN100524725C (zh
Inventor
金森宽
大塚茂树
森田佑一
铃木彰
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of CN1828883A publication Critical patent/CN1828883A/zh
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Abstract

一种半导体装置的制造方法，抑止半导体装置的腐蚀。本发明的半导体装置的制造方法具有如下工序，相对隔着第一绝缘膜(2)形成于半导体衬底(1)上的第一配线3，从上述半导体衬底背面蚀刻该半导体衬底(1)，形成使上述绝缘膜(2)露出的第一开口部(7)。其次，在对从上述第一开口(7)露出的上述绝缘膜(2)进行蚀刻而形成使上述第一配线(3)露出的第二开口(8)后，对上述半导体衬底(1)进行蚀刻，形成具有比上述第一开口(7)的开口直径宽的开口直径的第三开口(9)。然后，在介由上述第二及第三开口(8、9)在包含上述第一配线(3)的半导体衬底背面形成第二绝缘膜(10)后，对包覆上述第一配线(3)的第二绝缘膜(10)进行蚀刻。

Description

半导体装置及其制造方法
技术领域
本发明涉及用于提高半导体装置的成品率及可靠性的技术。
背景技术
近年来，作为封装技术，CSP(Chip Size Package：芯片尺寸封装)正在受到人们关注。所谓CSP是指，具有与半导体芯片的外形尺寸大致相同大小的小型封装件。目前，作为CSP之一种，公知有BGA(Ball Grid Array：球栅阵列)型半导体装置。该BGA型半导体装置在封装件的一主面上格子状排列多个由焊锡等金属部件构成的球状导电端子，并且将其与形成于封装件的另一面上的半导体芯片电连接。
而且，在将该BGA型半导体装置组装到电子设备中时，通过将各导电端子压装在印刷线路板的配线图案上，将半导体芯片和搭载于印刷线路板上的外部电路电连接。
这样的BGA型半导体装置与具有向侧部突出的引脚的SOP(SmallOutline Package：小外形封装)及QFP(Quad Flat Package：四方扁平封装)等其它CSP型半导体装置相比，具有可设置多个导电端子且可小型化的优点。该BGA型半导体装置具有作为例如在手机中搭载的数码相机的图像传感器芯片的用途。
图10是构成现有的BGA型半导体装置的概略结构的图，图10(a)是该BGA型半导体装置表面侧的立体图。另外，图10(b)是该BGA型半导体装置背面侧的立体图。
BGA型半导体装置100中，在第一及第二玻璃衬底104a、104b之间，夹着树脂105a、105b而密封有半导体芯片101。在第二玻璃衬底104b的一主面上，即BGA型半导体装置100的背面上格子状配置有多个球状端子(以下称为导电端子111)。该导电端子111通过第二配线109向半导体芯片1连接。在多个第二配线109上分别连接有从半导体芯片101内部引出的铝配线，进行各导电端子111和半导体芯片101的电连接。
参照图11进一步详细说明该BGA型半导体装置100的剖面结构。图11表示沿分界(也称作划线或切割线)分割成各个芯片的BGA型半导体装置100的剖面图。
如图11所示，在配置于上述半导体芯片101表面的绝缘膜102上设有第一配线103。该半导体芯片101通过树脂105a与第一玻璃衬底104a粘接。另外，该半导体芯片101的背面通过树脂105b与第二玻璃衬底104b粘接。而且，第一配线103的一端与第二配线109连接。该第二配线109从第一配线103的一端延伸到第二玻璃衬底104b的表面。而且，在延伸到第二玻璃衬底104b上的第二配线109上形成有球状的导电端子111。
上述的技术被记载于下面的专利文献1中。
另外，不使用半导体晶圆背面侧的第二玻璃衬底的技术已被记载于本申请人在先发明的如下专利文献2中。
特别是关于在半导体芯片上粘接有一个支承体时的BGA型半导体装置的制造方法，参照附图进行说明。
图12～图14是表示可适用于图像传感器芯片的现有例的BGA型半导体装置的制造方法的剖面图。
首先，如图12所示，在半导体衬底30上的表面上，隔着由氧化硅膜或氮化硅膜构成的第一绝缘膜31形成由铝层或铝合金层构成的第一配线32。而且，在包含第一配线32的半导体衬底30上，通过由环氧树脂构成的粘接剂33粘接例如玻璃衬底34。
其次，如图13所示，在与第一配线32对应的半导体衬底30的背面形成具有开口部的抗蚀膜(未图示)，以该抗蚀膜为掩模对半导体衬底30进行干式蚀刻，进而蚀刻绝缘膜31，形成从半导体衬底30的背面到达第一配线32的开口35。
而且，在包含开口35在内的半导体衬底30的背面形成第二绝缘膜36，蚀刻该第二绝缘膜36，使上述第一配线32的表面露出，然后，如图14所示，隔着该第二绝缘膜36形成与上述第一配线32连接的配线层37。进而，在配线层37上形成保护层(未图示)，在保护层的规定位置设置开口，形成与配线层接触的球状端子38。
然后，图中未图示，将半导体衬底及层积于其上的上述各层切断，分离成各个半导体芯片。这样，形成将第一配线32和球状端子38电连接的BGA型半导体装置。
专利文献1：专利公表2002-512436号公报
专利文献2：特开2004-80006号公报
但是，在上述半导体装置的制造过程中，由于上述第二绝缘膜36成膜时的状态，及在该第二绝缘膜36成膜后为使第一配线32表面露出而进行的蚀刻第二绝缘膜36时的状态，而存在如下问题，即，例如图14所示，通过将第二绝缘膜36的膜厚减薄而使绝缘耐压性降低，或通过使处理药剂等经由上述开口35从硅端部浸入半导体装置内部而在上述第一配线32上产生腐蚀。特别是如图14所示，由于向开口35的底部及侧壁部形成绝缘膜的成膜膜厚比半导体衬底30的背面薄，故存在有包覆不良的位置A。
因此，可能会对制造后侵入水分等的耐性降低。
发明内容
本发明的半导体装置，包括：第一配线，其隔着第一绝缘膜形成于半导体芯片的第一主面上；第一开口部，其使所述第一绝缘膜从所述半导体芯片的第二主面露出；第二开口部，其使所述第一配线的表面从所述半导体芯片的第二主面露出，并且具有比所述第一开口部的开口直径小的开口直径；第二绝缘膜，其形成于所述第一及第二开口部的表面；第二配线，其通过所述第一及第二开口部，与所述第一配线电连接。
另外，还具有粘接在所述半导体芯片的第一主面上的支承体。
另外，所述第二绝缘膜为无机或有机绝缘膜，或者为将它们层积形成的结构。
另外，还具有与所述第二配线连接的球状端子。
本发明的半导体装置的制造方法，其包括如下工序：准备介由第一绝缘膜形成有第一配线的半导体衬底，从所述半导体衬底背面蚀刻该半导体衬底，形成使所述第一绝缘膜露出的第一开口；对从所述第一开口露出的所述第一绝缘膜进行蚀刻，形成使所述第一配线露出的第二开口；蚀刻所述半导体衬底，形成具有比所述第一开口的开口直径宽的开口直径的第三开口；介由所述第二及第三开口在包含所述第一配线的半导体衬底背面形成第二绝缘膜；对包覆所述第一配线的第二绝缘膜进行蚀刻；介由所述第二绝缘膜在第二及第三开口内形成与所述第一配线连接的第二配线。
另外，具有在所述半导体衬底上粘接支承体，以将所述第一配线之上包覆的工序。
另外，形成所述第二绝缘膜的工序为形成无机或有机绝缘膜的工序、或将它们层积形成的工序。
蚀刻所述第二绝缘膜的工序是以抗蚀膜为掩模进行蚀刻的工序。
蚀刻所述第二绝缘膜的工序是不使用抗蚀膜为掩模的蚀刻工序。
另外，还具有形成与所述第二配线连接的球状端子的工序。
而且，具有将所述半导体衬底分割成多个半导体芯片的工序。
根据本发明，在对半导体衬底和第一绝缘膜进行蚀刻而形成使第一配线露出的第一及第二开口后，蚀刻所述半导体衬底，形成具有比该第一开口的开口直径宽的开口直径的第三开口，由此，在之后的对第二绝缘膜进行构图的工序中，已被构图了的第二绝缘膜的蚀刻端部存在于第一绝缘膜上，使绝缘耐性提高，同时，可抑止制造过程中药剂等从硅端部浸入以及制造后的水分等的浸入，并且可抑止对第一配线的腐蚀的产生。
附图说明
图1是表示本发明实施例的半导体装置的制造方法的剖面图；
图2是表示本发明实施例的半导体装置的制造方法的剖面图；
图3是表示本发明实施例的半导体装置的制造方法的剖面图；
图4是表示本发明实施例的半导体装置的制造方法的剖面图；
图5是表示本发明实施例的半导体装置的制造方法的剖面图；
图6是表示本发明实施例的半导体装置的制造方法的剖面图；
图7是表示本发明实施例的半导体装置的制造方法的剖面图；
图8是表示本发明实施例的半导体装置的制造方法的剖面图；
图8(a)是表示本发明实施例的半导体装置的制造方法的剖面图；
图9是表示本发明其它实施例的半导体装置的制造方法的剖面图；
图10(a)、(b)是表示现有的半导体装置的立体图；
图11是表示现有的半导体装置的制造方法的剖面图；
图12是表示现有的半导体装置的制造方法的剖面图；
图13是表示现有的半导体装置的制造方法的剖面图；
图14是表示现有的半导体装置的制造方法的剖面图。
符号说明
1半导体衬底
2第一绝缘膜
3第一配线
4粘接剂
5支承体
6第一抗蚀膜
7第一开口
8第二开口
9第三开口
10第二绝缘膜
10a无机绝缘膜
10b有机绝缘膜
11第二抗蚀膜
12第二配线
13保护膜
14球状端子
具体实施方式
下面，参照图1～图9说明采用本发明的半导体装置及其制造方法。
图1～图9是表示可适用于图像传感器芯片的BGA型半导体装置的制造方法的剖面图。
首先，如图1所示，准备例如由硅等半导体晶圆构成的半导体衬底1。该半导体衬底1是利用半导体工艺形成例如CCD的图像传感器及半导体存储器等器件的衬底。在该半导体衬底1的表面，隔着例如由氧化硅膜及氮化硅膜等构成的第一绝缘膜2而形成由铝、铝合金或铜等构成的第一配线3。在此，上述第一配线3是外部连接用的焊盘电极，其与半导体装置的未图示的电路电连接。另外，包含上述第一配线3的半导体衬底1之上被例如由氧化硅膜及氮化硅膜等构成的钝化膜包覆。
而且，在包含上述第一配线3的半导体衬底1之上，通过由环氧树脂等构成的透明粘接剂4粘接支承体5。支承体5可以是例如薄膜状的保护带，也可以是玻璃、石英、陶瓷、塑料、金属、树脂等。另外，作为所述粘接剂4，如果不是所述图像传感器用途，则没有透明的必要，无论是透明还是不透明，都可以使用抗蚀树脂及丙稀树脂等。
其次，在与第一配线3对应的半导体衬底1的背面形成具有开口部的第一抗蚀膜6，如图2所示，以该抗蚀膜6为掩模，对上述半导体衬底1进行干式蚀刻，形成使上述第一绝缘膜2从半导体衬底1的背面露出的第一开口7。
然后，如图3所示，在除去上述抗蚀膜6后，对从上述第一开口7露出的上述绝缘膜2进行蚀刻，形成使上述第一配线3的表面露出的第二开口8。另外，也可以在形成上述第二开口8后，将该抗蚀膜6除去。
之后，如图4所示，蚀刻上述半导体衬底1，形成具有比上述第一开口7的开口直径宽的开口直径的第三开口9。在此，在本实施例中，第三开口9的上部开口直径约为150μm，底部开口直径约为60μm，而且，第二开口8的开口直径约为30μm。
接下来，如图5所示，介由上述第二及第三开口8、9，在包含上述第一配线3的半导体衬底1的背面形成第二绝缘膜10。在此，在本实施例中，将无机绝缘膜形成为该第二绝缘膜10。作为该无机绝缘膜，形成例如由低温CVD(Chemical Vapor Deposition：化学气相淀积法)法得到的TEOS膜。在此，无机绝缘膜通常其包覆性好，且可实现在三维结构下也稳定的包覆形状。另外，在本工序中形成的绝缘膜不限于无机绝缘膜，也可以为例如环氧类树脂的有机绝缘膜。在此，有机绝缘膜通常其表面光滑，对提高在其上成膜的金属膜(后述的第二配线12)的包覆性是有效的。
其次，如图6所示，以形成于上述半导体衬底1背面的第二抗蚀膜11为掩模，对包覆上述第一配线3的第二绝缘膜10进行蚀刻，使该第一配线3露出。
另外，在形成上述第二绝缘膜10的工序中，也可以如图9所示形成无机绝缘膜10a，然后形成有机绝缘膜10b，对它们的层积膜进行蚀刻而使上述第一配线3露出。由此，兼有上述的无机绝缘膜和有机绝缘膜的各自的优点，且通过采用层积结构可谋求耐压的提高。
在此，在上述第二绝缘膜10、无机绝缘膜10a及有机绝缘膜10b的蚀刻工序中，在本实施例中使用抗蚀膜11进行构图，但本发明不限于此，也可以通过利用例如在上述第二、第三开口8、9的底部、侧壁部、半导体衬底1表面成膜的该绝缘膜10、10a、10b的膜厚之差进行，而不使用抗蚀膜为掩模。即，上述绝缘膜10、10a、10b的膜厚中，半导体衬底1的表面最厚，随着从该半导体衬底1向侧壁部、从侧壁部向底部而逐渐变薄，利用这样的趋势，即使将在底部成膜的上述绝缘膜10、10a、10b去除而使第一配线3露出，也可以使在上述侧壁部及半导体衬底1表面上成膜的该绝缘膜10、10a、10b残留，由此，可以无掩模地进行蚀刻，谋求工艺的合理化。
在本发明中，通过在蚀刻半导体衬底1和第一绝缘膜2，形成使第一配线3露出的第一及第二开口7、8后，蚀刻上述半导体衬底1，形成具有比该第一开口7的开口直径宽的开口直径的第三开口9，从而如图6所示，对形成于上述第二、第三开口8、9上的第二绝缘膜10、10a、10b进行构图时的第二绝缘膜的构图端部至少存在于第一绝缘膜2上，故能够抑制由于现有这样的绝缘膜的包覆不充分而使绝缘耐性降低的问题，还可抑止制造过程中药剂等从硅端部浸入或制造后水分等侵入，将第一配线3等腐蚀的问题。
其次，在除去上述抗蚀膜11后，如图7所示，形成隔着上述第二绝缘膜10在第二及第三开口8、9内与上述第一配线3电连接的第二配线12。另外，在本实施例中，作为第二配线12，使用例如溅射法形成铝、铝合金等，或使用镀敷法形成铜等。换言之，省略图示的说明，但在第二配线12下形成有由氮化钛(TiN)膜构成的势垒膜。另外，上述势垒膜也可以为钛(Ti) 膜及钽(Ta)膜等高熔点金属和作为其化合物的钛钨(TiW)膜、氮化钽(TaN)膜、以及上述各种膜的层积膜。另外，在形成由铜构成的镀敷膜的情况下，在上述势垒膜上形成镀敷用的籽晶膜(例如铜)，并在该籽晶膜上进行镀敷处理，形成由铜构成的配线层。另外，既可以对该配线层进行构图，也可以不对其进行构图。
其次，如图8所示，在上述第二配线12上形成保护膜13，在该保护膜13的规定位置设置开口，形成与该第二配线12接触的球状端子14。在此，也可以为如下结构，即，上述第二配线12仅在第二及第三开口8、9内形成，而没有延伸到半导体衬底1的背面，且在该第二及第三开口8、9上将第二配线12和球状端子14连接。
然后，省略图示的说明，将半导体衬底及层积于其上的上述各层切断，分离成各个半导体芯片。这样，形成将第一配线3和球状端子14电连接的BGA型半导体装置。
另外，本实施例对适用于形成有球状端子14的半导体装置的情况进行了说明，但本发明不限于此，例如若形成贯通半导体衬底的开口部的结构，则也可以适用于未形成球状端子的半导体装置，例如也适用于LGA(LandGrid Array：焊盘阵列)型半导体装置。另外，以上的实施例中关于在半导体1的表面粘贴有支承体5的实施方式进行了说明，但也可以适用于图8(a)所示地不使用支承体5的半导体装置及其制造方法。图8(a)中，具有所述第一配线3的半导体衬底1之上被由绝缘体构成的保护膜15(例如钝化膜或将钝化膜与聚酰亚胺树脂膜层积的膜)包覆。另外，在图8(a)中，保护膜15完全包覆第一配线3，但该保护膜15也可以包覆第一配线3的一部分之上，使第一配线3局部露出。并且，在该露出的第一配线3之上进行引线接合、形成突起电极(バンプ電極)或者使该半导体装置与其他半导体装置层积的用途下使用时，也可以将所述第一配线3与其他半导体装置的导电端子连接。换言之，即使是图9所示的实施例，也同样适用于不使用支承体5的半导体装置及其制造方法。

Claims (11)

1、一种半导体装置，其特征在于，具有：
第一配线，其隔着第一绝缘膜形成在半导体芯片的第一主面上；
第一开口部，其使所述第一绝缘膜从所述半导体芯片的第二主面露出；
第二开口部，其使所述第一配线的表面从所述半导体芯片的第二主面露出，并且具有比所述第一开口部的开口直径小的开口直径；
第二绝缘膜，其形成于所述第一及第二开口部的表面；
第二配线，其通过所述第一及第二开口部，与所述第一配线电连接。
2、如权利要求1所述的半导体装置，其特征在于，具有粘接在所述半导体芯片的第一主面上的支承体。
3、如权利要求1或2所述的半导体装置，其特征在于，所述第二绝缘膜为无机或有机绝缘膜、或者是将它们层积形成的结构。
4、如权利要求1或2所述的半导体装置，其特征在于，具有与所述第二配线连接的球状端子。
5、一种半导体装置的制造方法，其特征在于，具有：
准备介由第一绝缘膜而形成有第一配线的半导体衬底，从所述半导体衬底背面蚀刻该半导体衬底，形成使所述第一绝缘膜露出的第一开口的工序；
对从所述第一开口露出的所述第一绝缘膜进行蚀刻，形成使所述第一配线露出的第二开口的工序；
蚀刻所述半导体衬底，形成具有比所述第一开口的开口直径宽的开口直径的第三开口的工序；
介由所述第二及第三开口在包含所述第一配线的半导体衬底背面形成第二绝缘膜的工序；
对包覆所述第一配线的第二绝缘膜进行蚀刻的工序；
介由所述第二绝缘膜在第二及第三开口内形成与所述第一配线连接的第二配线的工序。
6、如权利要求5所述的半导体装置的制造方法，其特征在于，具有在所述半导体衬底上粘接支承体，以将所述第一配线之上包覆的工序。
7、如权利要求5或6所述的半导体装置的制造方法，其特征在于，形成所述第二绝缘膜的工序为形成无机或有机绝缘膜的工序，或者是将它们层积形成的工序。
8、如权利要求5或6所述的半导体装置的制造方法，其特征在于，蚀刻所述第二绝缘膜的工序是以抗蚀膜为掩模进行蚀刻的工序。
9、如权利要求5或6所述的半导体装置的制造方法，其特征在于，蚀刻所述第二绝缘膜的工序是不使用抗蚀膜为掩模的蚀刻工序。
10、如权利要求5或6所述的半导体装置的制造方法，其特征在于，具有形成与所述第二配线连接的球状端子的工序。
11、如权利要求5或6所述的半导体装置的制造方法，其特征在于，具有将所述半导体衬底分割成多个半导体芯片的工序。
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