CN1591830A - 利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法 - Google Patents
利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法 Download PDFInfo
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Abstract
本发明提供一种利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其是将高压金属氧化物半导体(High Voltage CMOS)结构的掺杂井区及N型和P型漂移区以逆向(Retrograde)离子植入方式,于场氧化隔离结构形成后再以高电压离子植入方式形成此些掺杂区。本发明所形成的高压CMOS系具有更好电性特性,且耐崩溃电压更高,驱动电流亦更大,并使整体元件面积缩小许多。
Description
技术领域
本发明涉及一种高压元件(High Voltage Device)的制造方法,特别涉及一种利用逆向(Retrograde)离子植入方式形成高压互补式金属氧化物半导体(CMOS)的方法。
背景技术
高压元件是应用于电子产品中需要以高电压进行操作的部份,通常在集成电路的架构中,有些产品在其输入/输出(I/O)区域中的控制元件会比在核心元件区域中的控制元件所需电压更大,此输入/输出区域必须具有较能耐更高电压的元件,以避免在高压的正常操作下,发生电流崩溃(breakdown)的现象,所以其结构与一般元件并不相同。
现有的高压互补式金属氧化物半导体元件(CMOS)的构造如第一图所示,在一P型半导体基底10中先形成一N型井(N-Well)12,然后在NMOS区域形成N型漂移(N-drift)区域14以及在PMOS区域形成P型漂移(P-drift)区域16;接着在该基底10上形成场氧化层18、栅极氧化层(gate oxide)20及多晶硅栅极22,最后再在该基底10内以离子植入法在NMOS区域中形成N+型离子掺杂区域24,并在PMOS区域中形成P+型离子掺杂区域26,以分别作为源极(source)及漏极(drain)。
上述现有的制程方式,其所形成的N型漂移区域14延信道表面处靠近图中A点的区域,其电力线分布(Electric Field)密度较高,电位较为拥挤(Potential Crowding),使得N型漂移区域14所形成的空乏区(Depletion Region)不足以抵抗高电压的电力线分布,进而容易产生提前崩溃(Breakdown)。而为了提高崩溃电压,传统的方法是降低N型漂移区域14的掺杂浓度,进而增加空乏区的宽度,以达到提高崩溃电压的目的。但是,N型漂移区域14的浓度降低,将提高信道(Channel)在此区域的电阻,其导通电阻(On-resistance)将提高,使得晶体管元件的电流驱动(Current Driving)能力亦相对降低。
发明内容
本发明所要要解决的技术问题是提供一种利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其所形成的高压互补式金属氧化物半导体系具有更好的电性特性,且其耐崩溃电压更高,电流驱动能力亦更大,以解决现有技术所存在的缺陷。
为了解决上述技术问题,本发明所采用的技术方案是在一半导体基底上形成有隔离结构及一牺牲氧化层;并利用逆向离子植入方式,以高电压离子植入形成重掺杂井区以及浅掺杂的N型漂移区域与P型漂移区域;再经过热制程处理,使掺杂离子驱入至基底中,而后移除该牺牲氧化层;接着在半导体基底上形成一栅极氧化层与多晶硅栅极结构;并于多晶硅栅极结构二侧的半导体基底中进行离子植入步骤,以分别在N型漂移区域与P型漂移区域内形成重N型掺杂区域及重P型掺杂区域,其作为源/漏极用。
本发明的优点是:形成的高压互补式金属氧化物半导体具有更好的电性特性,且其耐崩溃电压更高,电流驱动能力亦更大,其设计规格(design rule)可大大缩小,使整体元件面积可有效缩小许多。其可改善闭锁效应(latch-up effect)的产生。
下面通过具体实施例配合所附的图式详加说明,以更容易了解本发明的目的、技术内容、特点及其所达成的功效。
附图说明
图1是现有的高压互补式金属氧化物半导体元件的构造剖视图。
图2至图5是本发明制作高压互补式金属氧化物半导体的各步骤构造剖视图。
图号说明:
10 P型半导体基底 12 N型井
14 N型漂移区域 16 P型漂移区域
18 场氧化层 20 栅极氧化层
22 多晶硅栅极 24 N+型离子掺杂区域
26 P+型离子掺杂区域
30 P型半导体基底 32 场氧化隔离结构
34 牺牲氧化层 36 N型掺杂井区
38 N型漂移区域 40 P型漂移区域
42 栅极氧化层 44 多晶硅栅极结构
46 重N型掺杂区域 48 重P型掺杂区域
具体实施方式
本发明是以逆向(Retrograde)离子植入方式,在形成有隔离结构的半导体基底内利用高电压离子植入形成重掺杂井区以及淡掺杂的N型漂移区域(N-drift)与P型漂移区域(P-drift),其可分别作为高压互补式金属氧化物半导体(CMOS)的NMOS区域及PMOS区域,且所形成的高压互补式金属氧化物半导体系具有更好的电性特性,故可有效解决存在于现有技术中的各种缺陷。
图2至图5为本发明的较佳实施例在制作高压互补式金属氧化物半导体的各步骤构造剖视图,如图所示,本发明所揭露的方法包括下列步骤:首先,如图2所示,提供一P型半导体基底30,利用化学气相沉积技术在半导体基底30表面依序形成一薄氧化层(Thin oxide)、一氧化层及一图案化氮化硅层(图中未示),并以此图案化氮化硅层为光刻,蚀刻该氧化层而形成如图2所示的场氧化(Field Oxide)隔离结构32;随后蚀刻去除该氮化硅层及该薄氧化层,然后再重新成长一层如图所示的牺牲氧化层(Sacrificial Oxide)34。
接着,请参阅图3所示,利用逆向离子植入(retrograde ion implantation)方式,以400~800千电子伏特(KeV)左右能量的高压电,将磷等N型掺杂离子以5*1012~1*1014/平方公分(cm2)的浓度植入该半导体基底30中而形成重掺杂的N型掺杂井区36;并以200~600KeV左右的能量,将磷或砷等之N型掺杂离子以5*1012~1*1014/cm2的浓度植入半导体基底30中而形成一淡掺杂的N型漂移区域38;再以100~300KeV左右的能量,将硼等P型掺杂离子以1*1013~1*1014/cm2的浓度植入该半导体基底30的N型掺杂井区36中而形成淡掺杂的P型漂移区域40。
然后,再经过热制程处理,使掺杂离子驱入(drive-in)该半导体基底30中,以通过驱入步骤来调整浓度分布,并对离子撞击过的区域进行晶格结构的修补。而后并蚀刻去除该牺牲氧化层34。
如图4所示,在该半导体基底30表面先成长一栅极氧化层42,于其上沉积形成一多晶硅层,并利用光阻微影、蚀刻制程而分别于N型漂移区域38与该P型漂移区域40上方形成多晶硅栅极结构44。
于该多晶硅栅极结构44二侧的半导体基底30中进行离子植入步骤,而分别在半导体基底30及该N型漂移区域38与P型漂移区域40内形成如图5所示的重N型掺杂区域46及重P型掺杂区域48,其中,该重N型掺杂区域46系作为N型漂移区域38的源/漏极,以形成NMOS结构;而该重P型掺杂区域48系作为P型漂移区域40的源/漏极,以形成PMOS结构。
本发明所形成的高压互补式金属氧化物半导体(CMOS)结构如图5所示,其位于场氧化隔离结构32下方的信道(Channel)为N型漂移区域38或P型漂移区域40的高浓度点,而接近图中A点的位置为浓度最低。由于场氧化隔离结构32下方信道之浓度远大于一般现有的方法,且位于A点位置的浓度反而可比现有技术的方法为更低。因此,依本发明所形成的高压CMOS的崩溃(breakdown)电压可为较高,且电流驱动(current driving)能力也大为改善。
此外,利用本发明所制作出的高压互补式金属氧化物半导体的设计规格(design rule)可大大缩小;例如,用以隔绝NMOS与PMOS的场氧化隔离结构,如图5中的X2大约为5μm,其远小于如图1所示的现有技术中的X1需约15μm,因此,本发明可有效使整体元件面积缩小许多。再者,利用本发明的方法亦可改善闭锁效应(latch-up effect)产生的问题。
以上所述的实施例仅为说明本发明的技术思想及特点,其目的在于使本领域的普通技术人员能够了解本发明的内容并据以实施,因此不能仅以此来限定本发明的专利范围,即凡依本发明所揭示的精神所作的均等变化或修饰,仍应涵盖在本发明的专利范围内。
Claims (10)
1、一种利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其特征在于,包括下列步骤:
提供一半导体基底,其上可形成有隔离结构及一牺牲氧化层;
利用逆向离子植入方式,以高电压离子植入形成重掺杂井区,以及淡掺杂的N型漂移区域与P型漂移区域;
经热制程处理,使掺杂离子驱入该半导体基底中,而后移除该牺牲氧化层;
在该半导体基底上形成一栅极氧化层,并利用微影蚀刻制程形成多晶硅栅极结构;及
于该多晶硅栅极结构二侧的半导体基底中进行离子植入步骤,而分别在该N型漂移区域与该P型漂移区域内形成重N型掺杂区域及重P型掺杂区域,以作为源/漏极。
2、根据权利要求1所述的利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其特征在于,其中该半导体基底为P型半导体基底,该重掺杂井区则为N型掺杂井区。
3、根据权利要求1所述的利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其特征在于,其中该隔离结构为场氧化隔离结构。
4、根据权利要求1所述的利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其特征在于,其中该场氧化隔离结构是利用一图案化氮化硅层为元件,蚀刻一氧化层所形成的。
5、根据权利要求1所述的利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其特征在于,其中该重掺杂井区是以400~800千电子伏特(KeV)左右的能量,将掺杂离子以5*1012~1*1014/平方公分(cm2)的浓度植入该半导体基底中。
6、根据权利要求1所述的利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其特征在于,其中该掺杂离子为N型掺杂离子,尤其为磷离子。
7、根据权利要求1所述的利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其特征在于,其中该N型漂移区域是以200~600千电子伏特(KeV)左右的能量,将N型掺杂离子以5*1012~1*1014/平方公分(cm2)的浓度植入该半导体基底中。
8、根据权利要求7所述的利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其特征在于,其中该N型掺杂离子为磷离子或砷离子。
9、根据权利要求1所述的利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其特征在于,其中该P型漂移区域是以100~300千电子伏特(KeV)左右的能量,将P型掺杂离子以1*1013~1*1014/平方公分(cm2)的浓度植入该半导体基底中。
10、根据权利要求9所述的利用逆向离子植入方式形成高压互补式金属氧化物半导体的方法,其特征在于,其中该P型掺杂离子为硼离子。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102005371A (zh) * | 2009-08-28 | 2011-04-06 | 夏普株式会社 | 半导体装置的制造方法 |
CN102270580A (zh) * | 2010-06-04 | 2011-12-07 | 和舰科技(苏州)有限公司 | 一种制造高压nmos管的方法 |
CN102496575A (zh) * | 2011-12-23 | 2012-06-13 | 上海先进半导体制造股份有限公司 | 60v非对称高压pmos结构及其制造方法 |
CN116190319A (zh) * | 2022-12-28 | 2023-05-30 | 深圳市创芯微微电子有限公司 | 一种基于hvcmos平台的mos器件及其制造方法 |
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CN103972294A (zh) * | 2005-11-29 | 2014-08-06 | 旺宏电子股份有限公司 | 横向双重扩散式金属氧化物半导体晶体管及其制造方法 |
US7829928B2 (en) * | 2006-06-26 | 2010-11-09 | System General Corp. | Semiconductor structure of a high side driver and method for manufacturing the same |
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JP2978345B2 (ja) * | 1992-11-26 | 1999-11-15 | 三菱電機株式会社 | 半導体装置の製造方法 |
JP3586072B2 (ja) * | 1997-07-10 | 2004-11-10 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US6310366B1 (en) * | 1999-06-16 | 2001-10-30 | Micron Technology, Inc. | Retrograde well structure for a CMOS imager |
US6610585B1 (en) * | 2002-02-26 | 2003-08-26 | International Business Machines Corporation | Method for forming a retrograde implant |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102005371A (zh) * | 2009-08-28 | 2011-04-06 | 夏普株式会社 | 半导体装置的制造方法 |
CN102270580A (zh) * | 2010-06-04 | 2011-12-07 | 和舰科技(苏州)有限公司 | 一种制造高压nmos管的方法 |
CN102496575A (zh) * | 2011-12-23 | 2012-06-13 | 上海先进半导体制造股份有限公司 | 60v非对称高压pmos结构及其制造方法 |
CN116190319A (zh) * | 2022-12-28 | 2023-05-30 | 深圳市创芯微微电子有限公司 | 一种基于hvcmos平台的mos器件及其制造方法 |
CN116190319B (zh) * | 2022-12-28 | 2025-02-28 | 深圳市创芯微微电子有限公司 | 一种基于hvcmos平台的mos器件及其制造方法 |
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