CN1499622A - 引线框及制造方法以及树脂密封型半导体器件及制造方法 - Google Patents
引线框及制造方法以及树脂密封型半导体器件及制造方法 Download PDFInfo
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Abstract
本发明提供引线框及制造方法以及树脂密封型半导体器件及制造方法。树脂密封型半导体器件具备半导体芯片与述半导体芯片的电极组分别相连的多个内引线、以及密封上述半导体芯片和上述内引线的连接部的密封树脂。上述内引线在上述半导体芯片外周边的外侧的表面上,具有朝厚度方向突出的突出部,在上述突出部的侧部形成阶梯部。上述半导体芯片的电极组,通过导电性凸起与上述各内引线的上述突出部的内侧的内侧部分表面连接。上述密封树脂以密封上述半导体芯片以及上述导电性凸起、使上述突出部的表面露出的方式形成。可以缩小起到外部端子功能的突出部的表面尺寸,可以缩小外部端子间的节距。
Description
技术领域
本发明涉及一种使用引线框的树脂密封型半导体器件。特别涉及被称为SIP(密封级系统:System In Package)的树脂密封型半导体器件中,适合薄型化及元件高速化的结构,以及用于实现多个树脂密封型半导体器件的三维叠层用的结构。本发明还涉及该树脂密封型半导体器件所使用的引线框及该引线框的制造方法、以及树脂密封型半导体器件的制造方法。
背景技术
一直以来,作为小型、薄型的树脂密封型半导体器件,开发了一种仅单面被密封树脂密封的被称作QFN(Quad Flat Non-leadedPackage)的树脂密封型半导体器件。以下,对有关现有的QFN型树脂密封型半导体器件进行说明。
首先,说明有关树脂密封型半导体器件所使用的引线框(leadframe)。图6是表示现有引线框1的俯视图。该引线框1具有通过吊线部5对配置在框部2的开口区3的大致中央部位上的管芯垫(diepad)4进行支承的结构。吊线部5的一端与管芯垫4的各角部连接,另一端与框部2连接。另外,在框部2上形成多个内引线6,其前端与管芯垫4的各边相对配置。
接着,说明有关使用该引线框的现有树脂密封型半导体器件。图7A和图7B所示为现有的树脂密封型半导体器件。图7A是树脂密封型半导体器件的底面图,图7B是沿图7A的A-A1线的剖面图。半导体芯片7被粘接在管芯垫4上,引线框1的框部2(参照图6)被切断,从而使内引线6相互分离。半导体芯片7的电极8和内引线6的表面由金属细线9电连接。使管芯垫4的底面和内引线6的底面露出,从而半导体芯片7的外围区域被密封树脂10密封。内引线6的底面和侧面分别从外密封11的底面和侧面露出,以形成外部端子12。
接着,说明有关图7A和图7B所示的树脂密封型半导体器件的制造方法。图8A-图8E是通过与图7B一样沿图7A的A-A1线的剖面来表示相同制造方法的各工序的图。
首先,如图8A所示准备引线框1。该引线框1与图6所示的引线框相同,但省略了框部2(参照图6)的图示。示出了搭载半导体芯片的管芯垫4、及前端与管芯垫4的各边相对配列的多个内引线6。然后,如图8B所示,在引线框1的管芯垫4上,粘接搭载半导体芯片7。然后,如图8C所示,半导体芯片7和内引线6的表面由金属细线9电连接。
然后,如图8D所示,利用密封模具13将管芯垫4、内引线6的表面和半导体元件7的周边区域夹入,并利用密封树脂进行密封。然后,通过从密封模具中将由密封树脂10密封的外密封11取出,制成以内引线6的底面和外侧面作为外部端子12排列在外密封11的底面上的树脂密封型半导体器件(例如参见日本特开2000-307049号公报)。
但是,如上所述的现有树脂密封型半导体器件,由于其半导体芯片的电极和内引线由金属细线连接,所以整体的厚度变大而制约了薄型化。另外,由于没有考虑形成外部端子的内引线的露出面的尺寸,所以不是适合外部端子的尺寸的缩小化、外部端子间距离的狭小节距化的结构。
另外,在高速信号或高频信号工作的状况下,金属细线的信号损失成为问题,从而存在半导体芯片的功能不能充分发挥的问题。
另外,由于外部端子仅在树脂密封型半导体器件的底面露出,所以对多个树脂密封型半导体器件进行叠层也不能使外部端子相互电连接,存在三维安装实现困难的问题。
发明内容
本发明的引线框,具备框架、及从上述框架向内侧延伸的多个内引线,在上述内引线的外侧部分的表面设有朝厚度方向突出的突出部,在上述突出部的侧部形成阶梯部。
根据该引线框,在突出部的阶梯部的前端侧,突出部剖面的尺寸变小。因此,可以使起到外部端子功能的突出部的前端面面积变小,窄化各引线框突出部的前端面间的节距。
本发明的引线框的制造方法,其特征在于,形成具备框架、及从上述框架向内侧延伸的多个内引线的结构体,然后,对上述内引线表面的一部分进行半腐蚀或者冲压处理,而在上述内引线的表面形成突出部,然后,从上述突出部表面周围再进行半腐蚀或者冲压处理,而在上述突出部的侧部形成阶梯部。通过该方法,可以容易地在突出部形成阶梯部。
本发明的树脂密封型半导体器件,具备半导体芯片、沿半导体芯片的周边排列且与上述半导体芯片的电极组分别连接的多个内引线、及对上述半导体芯片和上述内引线的连接部进行密封的密封树脂,上述内引线的一部分从上述密封树脂露出而形成外部端子部。上述多个内引线具有在上述半导体芯片外周边的外侧表面朝厚度方向突出的突出部,在上述突出部的侧部形成阶梯部。上述半导体芯片的电极组,通过导电性凸起与上述各内引线的上述凸起部的内侧的内侧部分的表面连接。上述密封树脂被形成为对上述半导体芯片及上述导电性凸起进行密封,并使上述突出部的表面露出。
根据该结构,在内引线的突出部的阶梯部的前端侧,突出部剖面的尺寸变小。因此,可以使起到外部端子功能的突出部的前端面面积变小,窄化各内引线突出部的前端面间的节距。
本发明的树脂密封型半导体器件的制造方法,其所使用的引线框具有框架、及从上述框架向内侧延伸的多个内引线,在上述各内引线的外侧部分的表面设置朝厚度方向突出的突出部,在上述突出部的侧部形成阶梯部。另外,其具备以下工序:在上述内引线表面的上述突出部的内侧,形成第1导电性凸起的工序,在第1半导体芯片的表面叠层比上述第1半导体芯片还小的第2半导体芯片,通过第2导电性凸起使上述第1半导体芯片的第1电极组和上述第2半导体芯片的电极组进行电连接的工序,使上述第1半导体芯片的连接上述第2半导体芯片的区域的外侧形成的第2电极组,与上述第1导电性凸起进行电连接的工序,及通过密封树脂对上述第1以及第2半导体芯片的表面和包含上述第1以及第2导电性凸起的区域进行密封,而得到上述突出部的表面与上述密封树脂的外表面实质上在同一平面内、并从上述密封树脂露出的状态的工序。
本发明的其它树脂密封型半导体器件的制造方法,使用与上述制造方法同样的引线框。并且具备以下工序:在上述内引线表面的上述突出部的内侧,形成第1导电性凸起的工序,在第1半导体芯片的表面叠层比上述第1半导体芯片还小的第2半导体芯片,通过第2导电性凸起使上述第1半导体芯片的第1电极组和上述第2半导体芯片的电极组进行电连接的工序,使上述第1半导体芯片的连接上述第2半导体芯片的区域的外侧形成的第2电极组,与上述第1导电性凸起进行电连接的工序,及通过密封树脂对上述第1以及第2半导体芯片的表面和包含上述第1以及第2导电性凸起的区域进行密封的工序。
根据这些制造方法,可以使起到外部端子功能的内引线突出部的前端面的面积变小,窄化各引线突出部的前端面间的节距。
附图说明
图1A是表示本发明的一个实施例的引线框的平面图,图1B是沿图1A的B-B1线剖开的剖面图。图1C是图1A所示的引线框的改变结构的剖面图。
图2A是表示本发明的一个实施例的树脂密封型半导体器件的平面图,图2B是侧面图,图2C是背面图,图2D是沿图2A的C-C1线剖开的剖面图。
图3A是表示同一实施例的树脂密封型半导体器件改变结构的剖面图。图3B和图3C分别是沿图3A的D-D1、E-E1线剖开的剖面图。图3D是表示使同一实施例的树脂密封型半导体器件叠层后的状态的剖面图。
图4A~D是表示图2A~2D所示的树脂密封型半导体器件的制造方法的各个工序的剖面图。
图5A~E是表示同一树脂密封型半导体器件的其它制造方法的各个工序的剖面图。
图6是表示现有引线框的平面图。
图7A是表示现有树脂密封型半导体器件的平面图,图7B是沿图7A的A-A1线剖开的剖面图。
图8A~E是表示现有树脂密封型半导体器件的制造方法的各个工序的剖面图。
具体实施方式
在本发明的树脂密封型半导体器件中,可以设定不少于2阶的阶梯部。这样,在密封工序中,在模具和引线框之间存在树脂胶带时,密封树脂难以流入树脂胶带和引线框的突出部之间。其结果是降低密封树脂附着在突出部表面的可能性,确保突出部表面起到外部端子的功能。
在本发明的树脂密封型半导体器件中,上述半导体芯片可以作成包含第1半导体芯片、以及叠层在上述第1半导体芯片的表面上的尺寸比上述第1半导体芯片小的第2半导体芯片的结构。在该情况下,上述多个内引线的突出部位于上述第1半导体芯片外周边的外侧。上述第1半导体芯片的第1电极组,通过第1导电性凸起与上述各内引线的上述突出部的内侧的内侧部分表面连接。上述第2半导体芯片配置在由上述多个内引线的内端围成的区域内,通过第2导电性凸起与上述第1半导体芯片的第2电极组进行电连接。上述密封树脂密对上述第1以及第2半导体芯片的表面和上述第1以及第2导电性凸起进行密封。
另外,在本发明的树脂密封型半导体器件中,上述突出部的表面最好实质上与上述密封树脂的外表面在同一平面内。另外,上述第1半导体芯片的背面和上述密封树脂的外表面最好实质上在同一平面内。根据这些结构,可以使多个树脂密封型半导体器件更稳定地叠层。
另外,上述内引线最好朝其内端缓慢地向形成上述突出部的一面倾斜。这样,内引线外端侧的背面比内侧部分还突出,因此在密封工序容易露出,可以确保形成外部端子。另外,最好在上述突出部上形成球形电极。这样,可以提高与安装基板电连接的可靠性。另外,内引线的突出部表面的一部分上形成绝缘性薄膜,上述突出部的表面中、将形成了上述绝缘性薄膜的部分排除的部分起到外部端子的功能。这样,即使直接安装在电路板上也可以防止漏电。另外,即使在从电路板传来弯曲应力的情况,也可以由球形电极吸收该弯曲应力。
另外,也可以构成为叠层多个上述任何一种结构的树脂密封型半导体器件,相邻的一个上述树脂密封型半导体器件的内引线的背面和另外一个的上述树脂密封型半导体器件的突出部表面电连接的树脂密封型半导体器件。根据该结构,可以容易地叠层树脂密封型半导体器件,能够以小的安装面积实现多功能。这种情况,可以作成不少于3个的树脂密封型半导体器件的叠层的结构。
在本发明的树脂密封型半导体器件的制造方法中,在上述密封工序之后,可以切断从上述内引线的上述密封树脂露出的部分,使由树脂密封的结构体和上述框架分离。另外,最好至少在使树脂片与上述突出部紧密贴合的状态下供给密封树脂。这样,在密封工序,可以抑制在突出部的表面上附着密封树脂,确保露出突出部的表面。
以下就本发明的实施例,参照图纸具体地加以说明。首先,就引线框的结构加以说明。图1A是表示本实施例的引线框14的平面图,图1B是沿图1A的B-B1线剖开的剖面图。
引线框14由诸如铜材或者42合金等金属板构成。框架15的厚度为100~300μm,多个内引线16以朝内侧延伸的方式形成。各内引线16在其外侧的表面上设置突出部17。在此,内引线16的表面是与所搭载的半导体芯片相对的面,即形成与半导体芯片的电极进行电连接的导电性凸起的面。在突出部17的内侧,由薄壁的内侧部分16a形成内端部。在突出部17的侧部形成有阶梯部18,厚度约为框架15厚度的一半。可以适当地设定阶梯部18的厚度。另外,在本实施例中,例如可以设定引线框架14的厚度为150μm,设置不少于2阶的阶梯部18。
如图1C所示,各内引线16可以朝上倾斜,即在突出部突出一侧内侧部分16a的内端部。从而,该内侧部分16a的背面从内引线16的背面的位于外端面侧凹入。换而言之,内引线16的背面的位于外端面侧超出内侧部分16a的内端部突出。
接下来,就本实施例的引线框架14的制造方法概略地加以说明。首先,制作一样厚度的由框架以及从框架向内侧延伸的多个内引线构成的结构体。接下来,对内引线表面的一部分实施半腐蚀或者冲压处理,在内引线的表面形成突出部。接下来,从突出部表面周围再进行半腐蚀或者冲压处理,而在突出部的侧部设置阶梯部。
接下来,就本实施例的树脂密封型半导体器件加以说明。图2A是表示树脂密封型半导体器件的平面图,图2B是侧面图,图2C是底面图,图2D是沿图2A的C-C1线剖开的剖面图。该树脂型半导体器件是在图1A、图1B中所示的引线框上搭载第1半导体芯片19以及第2半导体芯片25的器件。
图2A所示是第1半导体芯片19的背面以及内引线16的突出部17的表面从密封树脂26露出的状态。图2B所示是内引线16的外端面从密封树脂26露出的状态。图2C所示是第2半导体芯片25的背面以及内引线16的背面从密封树脂26露出的状态。
如图2D所示,在第1半导体芯片19的周边部配置的第1电极20上,形成第1导电性凸起(bump)21。各内引线16的内侧部分16a向第1半导体芯片19周边的内侧延伸,第1导电性凸起21和内侧部分16a连接。各内引线16的阶梯部18以及突出部17配置在第1半导体芯片19的周边的外侧,在突出部17的表面设有由焊锡(焊料)等形成的球形电极22。外部电极22的前端比第1半导体芯片19的背面还突出。
在由多个内引线16的内端围成的区域内,配置比第1半导体芯片19的尺寸还小的第2半导体芯片25。在第1半导体芯片19的表面的第1电极20的内侧,形成与第2半导体芯片25相对的第2电极23。第1半导体芯片19的第2电极23和第2半导体芯片25的电极25a由第2导电性凸起24进行电连接。第1以及第2半导体芯片19、25的表面和第1以及第2导电性凸起21、24由密封树脂26密封。实施的密封使内引线16的突出部17的表面露出。突出部17的表面以及第1半导体芯片19的背面与密封树脂26的外表面大致在同一平面内。另外,内引线16的背面与密封树脂26的外表面大致在同一平面内。
在本实施例中,通过形成阶梯部18,前端侧的突出部17的剖面尺寸变小。因此,起到外部端子功能的突出部17的前端面面积变小,可以窄化各突出部17的前端面间的节距。
另外,通过在突出部17上设立球形电极22,对于搭载在电路板上的树脂密封型半导体器件,在从电路板传来弯曲应力的情况下,球形电极22也可以吸收该弯曲应力。
如图1C所示,内引线16的内侧部分16a朝向其前端部向突出部17的突出一侧倾斜。因此,内引线16的外端面侧的背面比内侧部分16a的背面还突出,在密封工序,容易从密封树脂26的外表面露出,可以确保和电路板等的电连接。另外,如图3A和图3C所示,在内引线16的突出部17的表面的一部分形成绝缘性薄膜33。图3A是表示一实施例的树脂密封型半导体器件的剖面图。图3B和图3C分别是沿图3A的D-D1、E-E1线剖开的剖面图。如图3A和图3C所示,该绝缘薄膜33具有开口33a。在突出部17的表面,可以将形成了绝缘性薄膜33的开口33a的部分排除的部分作为外部端子。这样,即使直接安装在电路板上也可以防止漏电。而且,在与内引线16的第1导电性凸起21接触的部分,也可以在内引线16的表面形成小的凸部。通过凸部嵌入第1导电性凸起21而连接,可以确保第1导电性凸起21和内引线6在稳定的连接。而且,凸部也可以是在其前端有凹部的形状。
接下来,就叠层多个上述结构的树脂密封型半导体器件的情况加以说明。图3D是表示叠层多个树脂密封型半导体器件27~30,并且叠层后的上下树脂密封型半导体器件相互进行电连接的状态的剖面图。
下侧的树脂密封型半导体器件29的内引线16的突出部17的表面和上侧的树脂密封型半导体器件28的内引线16的背面,通过由焊锡构成的球形电极22连接着。这样,根据本实施例,可以叠层多个树脂密封型半导体器件,并且相互之间可以容易地进行电连接。这样,可以是1个树脂密封型半导体器件的安装面积,同时可以实现多功能高密度的安装型树脂密封型半导体器件。可以任意选择叠层的树脂密封型半导体器件的个数。
接下来,就上述结构的树脂密封型半导体器件的制造方法加以说明。首先,就本实施例的第1制造方法并参照图4A~4D加以说明。
首先,如图4A所示准备图1所示的引线框14。然后,如图4B所示,在内引线16的内侧部分16a的表面形成第1导电性凸起21。另外,使第1半导体芯片19和第2半导体芯片25重叠,并通过第2导电性凸起24使第1半导体19的第2电极23和第2半导体芯片25的电极25a进行电连接。接下来,使第1半导体芯片19和第2半导体芯片25的叠层体如图所示叠层在引线框14上,并且使第1半导体芯片19的第1电极20和在内引线16上形成的第1导电性凸起21进行电连接。
接下来,如图4C所示,用密封模具31夹住引线框14、第1以及第2半导体芯片19、25,由密封树脂26(参照图4D)密封第1及第2半导体芯片19、25的表面、第1及第2导电性凸起21、24。然后,如图4D所示,切断从内引线16的密封树脂露出的部分(图未示出),使树脂密封体和框架分离。
在图4C的密封工序中,如图4D所示,使突出部17的表面从密封树脂26中露出,以便与密封树脂26的外表面大致形成同一平面。此时,在第1半导体芯片19的背面以及引线框14的突出部17的表面上,在使树脂片32紧密贴合的状态下,将密封树脂26注入密封模具31内。这样,可以防止在突出部17的表面形成密封树脂,可以在突出部17和安装基板的布线电极之间确保充分的电连接。
接下来,就树脂密封型半导体器件的第2制造方法,参照图5A~5E加以说明。首先,如图5A所示,准备如图1所示的引线框14。然后,如图5B所示,通过第1导电性凸起21使第1半导体芯片19的第1电极20和内引线16的内侧部分16a进行电连接。接下来,如图5C所示,通过第2导电性凸起24使第1半导体芯片19的第2电极23和第2半导体芯片25的电极25a进行电连接。
接下来,如图5D所示,用密封模具31以及密封树脂32,通过密封树脂26(参照图5E)密封第1以及第2半导体芯片19、25的表面和第1以及第2导电性凸起21、24。然后,如图5E所示,切断从引线框16的密封树脂露出的部分(图未示出),使树脂密封体和框架分离。在图5D的密封工序中,如图5E所示,使突出部17的表面从密封树脂26中露出,以便使其与密封树脂26的外表面大致成同一平面。
根据本实施例的制造方法,可以容易地制造出如上所述的0.8mm以下的薄的树脂密封型半导体器件。因此,例如,在安装基板上进行两面安装的状态下,可以内置在规格化的薄形PC卡中。
Claims (19)
1.一种引线框,具备框架、及从上述框架向内侧延伸的多个内引线,在上述内引线的外侧部分的表面设有朝厚度方向突出的突出部,在上述突出部的侧部形成阶梯部。
2.如权利要求1所记载的引线框,其特征在于,上述阶梯部设置不少于2阶。
3.一种引线框的制造方法,形成具备框架、及从上述框架向内侧延伸的多个内引线的结构体,然后,对上述内引线表面的一部分进行半腐蚀或者冲压处理,而在上述内引线的表面形成突出部,然后,从上述突出部表面周围再进行半腐蚀或者冲压处理,而在上述突出部的侧部形成阶梯部。
4.一种树脂密封型半导体器件,具备半导体芯片、沿半导体芯片的周边排列且与上述半导体芯片的电极组分别连接的多个内引线、及对上述半导体芯片和上述内引线的连接部进行密封的密封树脂,上述内引线的一部分从上述密封树脂露出而形成外部端子部,其特征在于,
上述多个内引线具有在上述半导体芯片外周边的外侧表面朝厚度方向突出的突出部,在上述突出部的侧部形成阶梯部,
上述半导体芯片的电极组,通过导电性凸起与上述各内引线的上述凸起部的内侧的内侧部分的表面连接,
上述密封树脂被形成为对上述半导体芯片及上述导电性凸起进行密封,并使上述突出部的表面露出。
5.如权利要求4所记载的树脂密封型半导体器件,其特征在于,上述半导体芯片包含第1半导体芯片、叠层在上述第1半导体芯片的表面并比上述第1半导体芯片尺寸小的第2半导体芯片,
上述多个内引线的突出部位于上述第1半导体芯片外周边的外侧,
上述第1半导体芯片的第1电极组,通过第1导电性凸起与上述各内引线的上述凸起部的内侧的内侧部分的表面连接,
上述第2半导体芯片布置在由上述多个内引线的内端围成的区域内,通过第2导电性凸起与上述第1半导体芯片的第2电极组电连接,
上述密封树脂对上述第1以及第2半导体芯片的表面和上述第1以及第2导电性凸起进行密封。
6.如权利要求4所记载的树脂密封型半导体器件,其特征在于,上述突出部的表面实质上与上述密封树脂的外表面在同一平面内。
7.如权利要求4所记载的树脂密封型半导体器件,其特征在于,上述第1半导体芯片的背面和上述密封树脂的外表面实质上在同一平面内。
8.如权利要求4所记载的树脂密封型半导体器件,其特征在于,上述内引线的背面与上述密封树脂的外表面实质上在同一平面上。
9.如权利要求4所记载的树脂密封型半导体器件,其特征在于,上述内引线朝向其内端缓慢地向形成上述凸起部的一面侧倾斜。
10.如权利要求4所记载的树脂密封型半导体器件,其特征在于,在上述突出部上形成球形电极。
11.如权利要求4所记载的树脂密封型半导体器件,其特征在于,在内引线的突出部表面的一部分上形成绝缘性薄膜,上述突出部的表面中、将形成了上述绝缘性薄膜的部分排除的部分起到外部端子的功能。
12.一种树脂密封型半导体器件,叠层多个权利要求4所记载的树脂密封型半导体器件,相邻的一个上述树脂密封型半导体器件的内引线的背面和另外一个上述树脂密封型半导体器件的突出部的表面进行电连接。
13.如权利要求12所记载的树脂密封型半导体器件,其特征在于,上述树脂密封型半导体器件叠层3个以上。
14.一种树脂密封型半导体器件的制造方法,其所使用的引线框具有框架、及从上述框架向内侧延伸的多个内引线,在上述各内引线的外侧部分的表面设置朝厚度方向突出的突出部,在上述突出部的侧部形成阶梯部,其具备以下工序:
在上述内引线表面的上述突出部的内侧,形成第1导电性凸起的工序,
在第1半导体芯片的表面叠层比上述第1半导体芯片还小的第2半导体芯片,通过第2导电性凸起使上述第1半导体芯片的第1电极组和上述第2半导体芯片的电极组进行电连接的工序,
使上述第1半导体芯片的连接上述第2半导体芯片的区域的外侧形成的第2电极组,与上述第1导电性凸起进行电连接的工序,及
通过密封树脂对上述第1以及第2半导体芯片的表面和包含上述第1以及第2导电性凸起的区域进行密封,而得到上述突出部的表面与上述密封树脂的外表面实质上在同一平面内、并从上述密封树脂露出的状态的工序。
15.如权利要求14所记载的树脂密封型半导体器件的制造方法,其特征在于,在上述密封工序之后,切断从上述内引线的上述密封树脂露出的部分,而使由树脂密封的结构体和上述框架分离。
16.如权利要求14所记载的树脂密封型半导体器件的制造方法,其特征在于,在上述密封工序,至少在使树脂片与上述突出部紧密贴合的状态下供给密封树脂。
17.一种树脂密封型半导体器件的制造方法,其所使用的引线框具有框架、及从上述框架向内侧延伸的多个内引线,在上述各内引线的外侧部分的表面设置朝厚度方向突出的突出部,在上述突出部的侧部形成阶梯部,其具备以下工序:
在上述内引线表面的上述突出部的内侧,形成第1导电性凸起的工序,
在第1半导体芯片的表面叠层比上述第1半导体芯片还小的第2半导体芯片,通过第2导电性凸起使上述第1半导体芯片的第1电极组和上述第2半导体芯片的电极组进行电连接的工序,
使上述第1半导体芯片的连接上述第2半导体芯片的区域的外侧形成的第2电极组,与上述第1导电性凸起进行电连接的工序,及
通过密封树脂对上述第1以及第2半导体芯片的表面和包含上述第1以及第2导电性凸起的区域进行密封的工序。
18.如权利要求17所记载的树脂密封型半导体器件的制造方法,其特征在于,在上述密封工序之后,切断从上述内引线的上述密封树脂露出的部分,而使由树脂密封的结构体和上述框架分离。
19.如权利要求17所记载的树脂密封型半导体器件的制造方法,其特征在于,在上述密封工序,在上述密封工序,至少在使树脂片与上述突出部紧密贴合的状态下供给密封树脂。
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CN106206526A (zh) * | 2015-04-02 | 2016-12-07 | 南茂科技股份有限公司 | 芯片封装结构及堆叠式芯片封装结构 |
CN109564879A (zh) * | 2016-07-28 | 2019-04-02 | 株式会社东海理化电机制作所 | 半导体装置的制造方法 |
CN109686697A (zh) * | 2018-12-24 | 2019-04-26 | 中国电子科技集团公司第五十八研究所 | 一种多芯片扇出型结构的封装方法及其结构 |
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US7405104B2 (en) | 2008-07-29 |
JP3736516B2 (ja) | 2006-01-18 |
US20040089921A1 (en) | 2004-05-13 |
CN100414696C (zh) | 2008-08-27 |
JP2004153220A (ja) | 2004-05-27 |
TW200410386A (en) | 2004-06-16 |
US20060163703A1 (en) | 2006-07-27 |
US7049684B2 (en) | 2006-05-23 |
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