CN1484319A - High temperature resistant solid piezoresistive flat film force sensitive chip and manufacturing method thereof - Google Patents

Abstract

The invention provides a high-temperature-resistant solid-state piezoresistive flat-film force-sensitive chip and a manufacturing method thereof. A silicon dioxide insulating layer is injected under the silicon chip through the SIMOX process, and four resistors R ₁ , R ₂ , R ₃ and R ₄ , get a "relief" resistance measurement circuit protruding from the silicon surface of the silicon dioxide surface, and connect the resistance strips to form a Wheatstone measurement circuit through titanium-platinum-gold beam lead technology; the chip's The silicon dioxide insulating layer isolates the upper layer of monocrystalline silicon Wheatstone measurement circuit from the base silicon, avoiding the leakage current between the measurement circuit layer and the silicon base due to the increase in ambient temperature, and improving the high temperature resistance performance. The temperature range is -40 ~ 350 ℃, and the titanium-platinum-gold beam lead technology solves the high-temperature lead technology problem of force-sensitive chips. The chip can be applied to sensors for force, pressure, displacement, acceleration, torque and flow velocity in high temperature environments.

Description

High temperature resistant solid piezoresistive flat film force sensitive chip and manufacturing method thereof

technical field

The invention relates to a high-temperature-resistant sensor measuring chip and a manufacturing method thereof, in particular to a solid-state piezoresistive flat film force-sensing chip for a force-sensitive sensor and a manufacturing method thereof.

Background technique

At present, the measuring elements used in force sensitive sensors include: single metal strain gauge, bridge metal strain gauge, silicon piezoresistive bridge strain gauge and bulk silicon solid piezoresistive chip.

When the existing sensor uses a single metal strain gauge as a measuring element, it often needs to be matched with other single strain gauges or peripheral circuits to form a measuring unit, so there is inconsistency, which leads to excessive zero output, and its measurement accuracy and Less sensitive.

The bridge metal strain gauge is a kind of strain gauge that uses four single metal strain gauges as four resistance bars on the Wheatstone bridge. Due to the metal strain effect, it has large volume, low measurement sensitivity, and large zero error. And other shortcomings, it cannot detect some tiny components and weak strains.

The four resistive strips of the Wheatstone measurement bridge of the traditional bulk silicon pressure sensor chip use the silicon planar ion implantation process or the silicon planar diffusion process, and use the _SiO2 on the surface of the silicon wafer as an implantation or diffusion mask to dope The elements are implanted and diffused into the silicon wafer from the _SiO2 mask window, and a PN junction is formed between the upper P-type semiconductor resistance strip and the base N-type silicon. The sensor technology of this PN junction structure is simple and suitable for working at normal temperature, but when the temperature rises above 120°C, the leakage current of the PN junction is very large, which makes this kind of force sensitive chip unable to work.

Contents of the invention

The purpose of the present invention is to provide a measurement chip for high temperature resistant solid-state piezoresistive flat-film force-sensitive sensor and its manufacturing method, so as to solve the problem of excessive volume, low sensitivity, large zero position error and silicon piezoresistive pressure of traditional metal strain gauges. The bridge strain gauge has the disadvantages of large zero error and large temperature drift.

In order to achieve the above object, the present invention provides a high-temperature-resistant silicon strain solid-state piezoresistive flat-film force-sensitive chip and a manufacturing method thereof. 1. Add a 1.2-2 μm silicon measurement circuit layer on the silicon dioxide isolation layer, and add a 0.1-0.2 μm silicon nitride stress matching layer on the silicon measurement circuit layer. In the production process, a certain thickness of isolation layer (SOI) is formed at a certain depth under the surface of the silicon chip by using high-energy oxygen ion implantation technology (SIMOX), and a certain thickness of monocrystalline silicon is epitaxy on the surface of the silicon chip by vapor deposition (CVD) technology. , using low-pressure vapor deposition (LPCVD) technology to epitaxially layer a layer of stress-matching silicon nitride on the deposited single-crystal silicon layer, on the chip surface (001) crystal plane along the [110] crystal direction and [1 10] The four resistors R ₁ , R ₂ , R ₃ and R ₄ of the Wheatstone bridge are lithographically etched, and then the silicon nitride and single crystal silicon other than the resistor strip pattern are etched away by plasma etching (RIE) technology , to obtain the measurement circuit of the resistive strip protruding from the surface of the chip. Connect the engraved Wheatstone bridge four resistors R ₁ , R ₂ , R ₃ and R ₄ through the titanium-platinum-gold beam lead method to form a Wheatstone measurement circuit, and then thin the backside of the sensor chip , and finally obtained the designed SOI high-temperature resistant solid-state piezoresistive flat-film force-sensing chip through dicing and slicing.

The uniform and consistent silicon dioxide insulating layer formed by SIMOX technology isolates the upper single crystal silicon Wheatstone measurement circuit from the base silicon, avoiding the leakage caused by the rise of ambient temperature between the measurement circuit layer and the silicon base current. Titanium-platinum-gold beam lead technology is adopted, that is, the metal in contact with the silicon resistance strip is titanium, the metal in the middle is platinum, and the metal of the outer beam is gold, and the titanium-platinum-gold beam type is adopted.

The lead solves the high temperature lead technical problem of the force-sensitive chip, so the sensor packaged by the SOI high-temperature-resistant solid-state piezoresistive flat-film force-sensitive chip has the characteristics of high temperature resistance. The advantage of this chip is that it can meet the measurement requirements in high temperature environments while ensuring high measurement sensitivity.

Description of drawings

Fig. 1 shows silicon isolation SOI micro-strain solid-state piezoresistive sensor manufacturing method of the present invention

Fig. 2 shows the structural diagram of the force sensitive chip of the present invention,

Wherein Fig. 2 (a) is the circuit structure diagram of force sensitive chip;

Figure 2(b) is the "relief" resistance strip measurement circuit protruding from the silicon surface;

Fig. 3 represents the specific application range and the mode of the present invention,

Figure 3(a) shows that the force-sensitive chip is used on the elastic beam;

Figure 3(b) shows the force-sensitive chip acting on the elastic element.

Detailed ways

The present invention is illustrated by examples with reference to the accompanying drawings, and details the implementation of the present invention.

With reference to Fig. 1, the present invention is to add the silicon dioxide isolation layer 2 of 0.3 μm～0.4 μm on silicon substrate 1, add 1.2 μm～2 μm silicon measurement circuit layer 3 on silicon dioxide isolation layer 2, and measure in silicon The circuit layer 3 is formed by adding a 0.1 μm-0.2 μm silicon nitride stress matching layer 4 .

The present invention includes arranging four resistance strips on the silicon dioxide insulating layer 2 of a silicon film of a (001) crystal plane, wherein the resistance strips _R1 and _R4 are arranged along the silicon film [110] crystal direction, and the resistance strip _R2 Arranged parallel to R ₃ along the [1 10] crystal direction, the Wheatstone bridge structure is butterfly-shaped. The width of the resistance strip is 10 μm-20 μm, and the length of the resistance strip is 600 μm-1200 μm.

Resistance strips R ₁ and R ₂ are connected through a common pressure welding block 6, resistance strips R ₃ and R ₄ are connected through a common pressure welding block 7; pressure welding blocks 5, 8, 9, 10 are respectively connected with resistance strip R ₁ , R ₄ , R ₃ and the other end of R ₂ are connected, and the function of the pressure soldering block is to realize the wiring between the chip and the chip. When the Wheatstone measurement circuit is composed of resistance strips R ₁ , R ₂ , R ₃ and R ₄ , the pressure welding blocks 5 and 9 are shorted together to the positive pole of the power supply 5V, and the pressure welding blocks 4 and 10 are shorted together with the power supply ground Connection, welding blocks 6 and 7 are the output ends of the bridge.

With reference to Fig. 2, illustrate the manufacture method of high temperature resistant solid-state piezoresistive type flat film force sensitive chip of the present invention

1) On the N-type (001) single-crystal silicon wafer, use high-energy oxygen ion implantation (SIMOX) technology to form a silicon dioxide isolation layer with a thickness of about 0.3 μm to 0.4 μm below the silicon surface of 0.1 μm to 0.2 μm;

2) Deposit a single crystal silicon measurement circuit layer with a thickness of about 1.2 μm to 2 μm on the silicon surface of the silicon dioxide isolation layer by vapor deposition technology;

3) Deposit a layer of silicon nitride with a stress matching layer of 0.1 μm to 0.2 μm by low-pressure vapor deposition (LPCVD);

4) On the (001) crystal plane, four resistors R ₁ , R ₂ , R ₃ and R ₄ of the Wheatstone bridge are photocut along the [110] crystal direction and [1 10] crystal direction. Etch (RIE) technology to carve away the silicon nitride and single crystal silicon other than the resistance strip pattern, and obtain the "relief type" resistance strip measurement circuit protruding from the silicon surface;

5), through the titanium-platinum-gold beam lead process, the four resistance bars are connected to form a Wheatstone measurement circuit,

6) In order to improve the measurement sensitivity of the sensor chip, the back of the sensor is thinned to 0.18-0.2mm, and the designed SOI high-temperature-resistant solid-state piezoresistive flat-film force-sensing chip is obtained after dicing .

Due to the formation of a uniform insulating layer of silicon dioxide through the SIMOX process, the upper layer of single crystal silicon Wheatstone measurement circuit is isolated from the substrate silicon, avoiding the leakage caused by the increase of ambient temperature between the measurement circuit layer and the silicon substrate. current. In order to ensure a good ohmic contact between the pad and the resistance strip and the reliability of the outer lead of the sensor chip in a high temperature environment, the pad adopts the titanium-platinum-gold beam lead technology, that is, the metal in contact with the silicon resistance strip Titanium, titanium and silicon have very small contact resistance, easy to form a good ohmic contact; the intermediate diffusion barrier metal is platinum, which has good corrosion resistance; the outer beam metal is gold, because gold beams are easy to bond and easy to manufacture , and has high corrosion resistance, the thickness ratio of titanium-platinum-gold is 500:500:5000 (unit ), the use of titanium-platinum-gold beam leads solves the technical problem of high-temperature lead wires for force-sensitive chips, so The sensor packaged by SOI high temperature resistant solid piezoresistive flat film force sensitive chip has the characteristics of high temperature resistance. The advantage of the solid-state piezoresistive flat-membrane force-sensing chip is that it can meet the measurement requirements in high-temperature environments while ensuring high sensitivity during measurement.

Using this force-sensitive chip can produce a variety of sensors with different mechanisms of action, such as tension, tension, displacement, torque, pressure and other sensors. The convenient and accurate detection of the measured body must rely on certain elastic elements and circuit forms. When using flat film force-sensitive chips to make sensors such as tension, tension, displacement, torque, and pressure, SOI high-temperature resistant solid-state piezoresistors are usually required. The flat-film force-sensitive chip and the metal elastic element are consolidated together by glass frit sintering and other processes. The metal elastic element requires its thermal expansion coefficient to be as consistent as possible with that of silicon to reduce the influence of thermal mismatch stress. Silicon film The force on the chip is along the crystal direction [110] or [1 10], that is, the two-arm resistors R ₁ and R ₄ of the Wheatstone bridge on the working crystal plane of the SOI silicon diaphragm (001) are placed on the [110] crystal direction, and the other two arm resistors R ₂ and R ₃ are placed in the [1 10] crystal direction.

With reference to Fig. 3 (a), when measuring force, displacement, acceleration, force-sensitive chip 11 of the present invention is posted on an end of cantilever beam 12, and external force, displacement or acceleration act on the other end of sensor cantilever beam 12, cause cantilever beam The deformation of the cantilever beam produces a certain strain on the surface of the cantilever beam. The SOI sensitive element 11 can convert this strain into a certain voltage signal under the excitation of a constant power supply to achieve the purpose of measuring force, displacement and acceleration.

Referring to Figure 3(b), when measuring tension and tension, the measured tension and tension act on the elastic element 13, causing the elastic element 13 to deform and produce corresponding strain on the surface of the elastic element. SOI high temperature resistant solid piezoresistive flat membrane The force-sensitive chip 11 can convert the strain into a corresponding voltage signal, so as to achieve the purpose of measuring tension and tension.

The positive and negative changes of the resistance change rate ΔR/R of the SOI high-temperature-resistant solid-state piezoresistive flat-film force-sensing chip are realized by the positive and negative changes of the stress difference. For R ₁ and R ₄ , the longitudinal stress σ _l = σ _y , the transverse stress σ _t = σ _x ; for R ₂ and R ₃ , the longitudinal stress σ _l = σ _x , and the transverse stress σ _t = σ _y . The longitudinal piezoresistive coefficient π _l ＝1/2π ₄₄ , the transverse piezoresistive coefficient π _t ＝-1/2π ₄₄ , when the strain occurs, the change rates of the resistance values of the Wheatstone bridges are respectively:

$\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&pi;</span>}}_{\mathrm{<span\; class="notranslate">\; 44</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; \&sigma;</span>}}_{\mathrm{<span\; class="notranslate">\; the\; y</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; \&sigma;</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

$\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&pi;</span>}}_{\mathrm{<span\; class="notranslate">\; 44</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; \&sigma;</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; \&sigma;</span>}}_{\mathrm{<span\; class="notranslate">\; the\; y</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Among them: σ _y , σ _x are the longitudinal and transverse stresses at the measuring point of the elastic element, respectively. The Wheatstone bridge composed of four "relief" resistors protruding from the silicon surface can sensitively reflect the resistance change caused by stress; it can also effectively eliminate the influence of the inhomogeneity of the diffusion resistance itself and the temperature coefficient of resistance .

The following are the results obtained after the implementation of the present invention: Outline dimensions of SOI high-temperature-resistant solid-state piezoresistive flat-film force-sensitive chip: 2.0mm×2.0mm×0.18mm; sensitivity: ≥0.1mv/με; strain limit: ≥3000με ;Single resistance bar resistance: 1200Ω; Power supply: 5VDC; Working temperature: -40～350℃; Fatigue life: ^≥107 times.

Claims (6)

1, the quick chip of a kind of high temperature resistant solid-state pressure resistance type plane film force, this chip includes silicon base [1], it is characterized in that going up the silicon dioxide separator [2] that adds 0.3 μ m～0.4 μ m in silicon base [1], on [2] absciss layer, add 1.2 μ m～2 μ m silica measurement circuit layers [3] at silicon dioxide, and go up adding 0.1 μ m～0.2 μ m silicon nitride stress matching layer [4] at silica measurement circuit layer [3].

2, the quick chip of high temperature resistant solid-state pressure resistance type plane film force according to claim 1 is characterized in that going up the silicon dioxide separator [2] that adds 0.4 μ m in silicon base [1].

3, the quick chip of high temperature resistant solid-state pressure resistance type plane film force according to claim 1 is characterized in that adding 2 μ m silica measurement circuit layers [3] at silicon dioxide separator [2].

4, the quick chip of high temperature resistant solid-state pressure resistance type plane film force according to claim 1 is characterized in that going up adding 0.1 μ m silicon nitride stress matching layer [4] at silica measurement circuit layer [3].

5, the manufacture method of the quick chip of a kind of high temperature resistant solid-state pressure resistance type plane film force, its feature may further comprise the steps:

A), on N type (001) monocrystalline silicon piece, under the 0.1 μ m～0.2 μ m of silicon face, form the silicon dioxide separator [2] of thick 0.3 μ m～0.4 μ m with the energetic oxygen ions injection method;

B), being about the thick monocrystalline silicon of 1.2 μ m～2 μ m at silicon face with the vapor phase deposition technique epitaxial thickness surveys

Amount circuit layer [3];

C), use one deck silicon nitride stress matching layer [4] of low-pressure vapor phase deposition technology extension 0.1 μ m～0.2 μ m;

D), make four resistance R of Wheatstone bridge by lithography along [110] crystal orientation and [1 10] crystal orientation at (001) crystal face ₁, R ₂, R ₃And R ₄, using plasma etching (RIE) technology is carved silicon nitride and the monocrystalline silicon beyond the resistor stripe figure;

E), use titanium-platinum-Jin beam lead technique with four resistance R ₁, R ₂, R ₃And R ₄Couple together;

F), with the thinning back side of chip to 0.18mm～0.2mm, be diced into single chip then.

6, the manufacture method of the quick chip of high temperature resistant solid-state pressure resistance type plane film force as claimed in claim 5 is characterized in that the said measuring circuit that protrudes from the sculptured resistor stripe on silicon dioxide insulating layer [2] surface is butterfly-shaped being arranged on the chip.

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