CN1330152C - Apparatus and method for clock recovery for time division multiplexing business - Google Patents
Apparatus and method for clock recovery for time division multiplexing business Download PDFInfo
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- CN1330152C CN1330152C CNB03149983XA CN03149983A CN1330152C CN 1330152 C CN1330152 C CN 1330152C CN B03149983X A CNB03149983X A CN B03149983XA CN 03149983 A CN03149983 A CN 03149983A CN 1330152 C CN1330152 C CN 1330152C
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Abstract
The present invention provides a method and a device for the clock recovery of TDM services in an IP network. The method comprises steps: shaping the flow of received IP data packets, and outputting a writing signal; calculating the data size buffered by FIFO according to the writing signal and a reading clock output by a digital oscillator; calculating a filtering parameter according to the writing signal and the calculated buffered data size; calculating a recovery reading clock according to the filtering parameter. In the present invention, on the basis of the existing clock recovery methods, flow shaping is carried out, and a two stage clock recovery method in which coarse adjustment and fine adjustment are implemented in a filter is used; thereby, the jitter problem of clock recovery can be preferably solved, and the present invention has the advantages of simple realization, wide adaptability range, and favorable effects of clock recovery.
Description
Invention field
The present invention relates to the transfer of data of IP (Internet protocol) network, the method for carrying out clock recovery when particularly in IP network, transmitting TDM (time division multiplexing) business.
Background technology
Carrying out the speech business transmission by IP network has been adopted more and more at large technology.As shown in Figure 1, ordinary telephone set is received PSTN (PSTN) network, receives TDMoIP (time division multiplexing on the IP) equipment by the E1 trunk line then, and the TDM business datum is converted to the IP bag, delivers on the IP network and transmits.At the other end of IP network, by TDMoIP equipment, the IP bag is reduced to the TDM business datum, deliver to another telephone set through PSTN then.
In the scheme of employing IP network transmitting voice service shown in Figure 1, because IP network can not provide the network clocking of an overall situation, the TDMoIP equipment clock at IP network two ends might be inconsistent.The TDM business is very high to clock request, if the inconsistent words of the clock of sending ending equipment and receiving device, long-play can cause more grave error of error code, slip or other, and this is unallowed to the TDM business.In order to realize the transmission reliably on IP network of TDM business, the clock recovery of TDM business on IP network is the technology of a key.
In the prior art, the clock recovery method of TDM business on IP network generally is the clock that recovers transmitting terminal at the receiving terminal of network according to the speed of the IP bag that receives.Fig. 2 has shown the general composition of the clock recovery device of prior art.This device mainly comprises phase discriminator, filter and digital oscillator.
Phase discriminator mainly according to data cached FIFO buffer (fifo buffer) read clock, write signal, calculate data in buffer quantity in the FIFO buffer.
Filter compares according to the capacity (being generally capacity one half value of FIFO buffer) of FIFO buffer data in buffer quantity and FIFO buffer itself, according to both differences, according to certain functional relation, exports a filtering parameter.
Digital oscillator according to filtering parameter, recovers the clock of transmitting terminal under the effect of reference clock.
Yet because that IP network transmission data have is very strong sudden, promptly receiving terminal may receive a plurality of packets sometimes, does not have packet to receive sometimes again, will cause receiving terminal clock recovered jitter very big like this.
For fear of this situation occurring, generally in the filter of said apparatus, to adopt the filtering algorithm of more complicated, the Packet Filtering of burst is fallen, perhaps the packet that should send adds.Because the service conditions more complicated of IP network is difficult to set up a proper model, the parameter regulation of filter is got up also very difficult.On the other hand, because the polytropy of IP network, the parameter of a network model not necessarily is fit to the another one network, and therefore this employing filtering algorithm is avoided the receiving terminal recovered clock because transfer of data sudden produces the method for shaking poor aspect the adaptability.
Summary of the invention
The above-mentioned defective of existing in prior technology at the clock recovery of TDM business in IP network, the present invention proposes a kind of new devices and methods therefor that TDM business in the IP network is carried out clock recovery, overcoming the defective of prior art, and have and realize that fairly simple, clock recovery effect better and the big advantage of clock recovery scope.
In order to realize above-mentioned purpose of the present invention, the invention provides a kind of device that TDM business in the IP network is carried out clock recovery, this device comprises: phase discriminator, filter and digital oscillator.It is characterized in that, also comprise a flow apparatus for shaping, be used for the IP packet that receives is carried out traffic shaping; And wherein said filter is the secondary filter, is used for calculating and export filtering parameter according to the output signal of traffic shaping device and the output signal of phase discriminator; Described digital oscillator is used for according to described filtering parameter and reference clock, obtains the clock of reading that recovers.
In one embodiment of the present invention, described traffic shaping device comprises: frequency divider is used for reference clock is carried out frequency division; The token counts device is used for according to the reference clock behind the frequency divider frequency division, increases token number and when data of the every transmission of receiving terminal FIFO buffer, makes the token count value subtract one; Control device, the data of controlling described receiving terminal FIFO buffer according to the token counts value send.
The present invention also provides a kind of method that TDM business in the IP network is carried out clock recovery in addition, and this method comprises: 1) the IP packet that receives is carried out exporting write signal behind the traffic shaping; 2) according to the clock of reading of this write signal and digital oscillator output, obtain FIFO buffer (fifo buffer) institute data in buffer amount; 3) according to described write signal and the described buffer data size calculation of filtered parameter of obtaining; 4) described filtering parameter is sent to digital oscillator, obtain the clock of reading of recovery.
In an embodiment of the present invention, described traffic shaping adopts single token bucket algorithm to realize.This list token bucket algorithm is: 1-1) reference clock is carried out frequency division, write token with the uniform rate that is slightly larger than the transmitting terminal data rate in leaking bucket; If 1-2) in the leakage bucket token is arranged, then be sent in the reception data of buffer memory in the FIFO buffer, and the token that leaks in the bucket is counted; When 1-3) not having token in leaking bucket, the FIFO buffer stops to send data.
In an embodiment of the present invention, described FIFO buffer data in buffer amount is obtained in the following way: 2-1) read the read signal that clock is converted to the FIFO buffer with described, input in the phase discriminator with write signal; 2-2) reading, writing address of FIFO buffer being delivered to address comparator compares; 2-3) under the control of timer, regularly export the data cached quantity of FIFO buffer.
In one embodiment of the invention, filtering parameter is obtained in the following way: 3-1) calculate the average and fine setting parameter Δ K of coarse adjustment parameter K; 3-2) average and fine setting parameter Δ K addition with the coarse adjustment parameter K.Wherein, the coarse adjustment parameter K on average is by calculating rate of received data in one period scheduled time (for example with second level be unit), and is weighted on average with the data rate of previous calculating and obtains.The fine setting parameter then is to determine like this: determine FIFO buffer data in buffer amount in the time period shorter than the sampling time used for coarse adjustment calculation of parameter rate of received data, if FIFO buffer data in buffer amount surpasses a half of FIFO buffer buffer memory, strengthen the transmission rate of FIFO buffer.If receiving terminal FIFO buffer data in buffer less than a half of FIFO buffer buffer memory, reduces the transmission rate of FIFO buffer.
The present invention is by on the basis of existing clock recovery method, the two-stage clock recovery method that adopts traffic shaping and in filter, carry out coarse adjustment+fine setting, jitter problem that can fine solution clock recovery, and the present invention realizes simply, the adaptability scope is wide, can obtain good clock recovery effect.
Description of drawings
By detailed explanatory note and in conjunction with the following drawings, above-mentioned purpose of the present invention, feature and the advantage easy to understand more that will become, wherein:
Fig. 1 is the network model schematic diagram of explanation TDM business by the IP network transmission;
Fig. 2 is the schematic diagram of the clock recovery technology of explanation prior art;
Fig. 3 is the schematic diagram that clock recovery device according to one embodiment of the present invention is described;
Fig. 4 is the schematic diagram that single token bucket algorithm that traffic shaping adopted according to one embodiment of the present invention is described;
Fig. 5 is the schematic diagram of the phase discriminator operation principle that illustrates according to one embodiment of the present invention to be adopted;
Fig. 6 is the schematic diagram of the operation principle of the explanation filter that one embodiment of this invention adopted;
Fig. 7 is the principle schematic of the explanation digital oscillator that one embodiment of this invention adopted.
Embodiment
Below in conjunction with description of drawings the preferred embodiments of the invention.
Fig. 3 is the schematic diagram that clock recovery device according to one embodiment of the present invention is described.As shown in Figure 3, the present invention improves existing clock recovery technology from two aspects: 1, before phase discriminator, increase traffic shaping and handle, the reception data of FIFO buffer are carried out exporting write signal again to phase discriminator after traffic shaping is handled.2, filter has adopted the secondary filtering method.
In this embodiment of the present invention, the traffic shaping device can comprise: frequency divider is used for reference clock is carried out frequency division; The token counts device is used for according to the reference clock behind the frequency divider frequency division, increases token number, and when data of the every transmission of receiving terminal FIFO buffer, makes the token count value subtract one; Control device, the data of controlling described receiving terminal FIFO buffer according to the token counts value send.
The purpose that the IP packet that the FIFO buffer is received carries out traffic shaping is that the clock recovery method that will solve prior art can not be tackled the paroxysmal problem of IP network packet well.In an embodiment of the present invention, traffic shaping has adopted a kind of single token bucket algorithm.Fig. 4 has schematically shown this algorithm.
In this single token bucket algorithm, earlier reference clock to be carried out frequency division, in leaking bucket, write token to be implemented under the uniform speed.This token writing rate is larger than the data rate of transmitting terminal.Can suitably be configured by the divide ratio of adjusting reference clock this speed.
The data that receive at first to be write carry out buffer memory in the FIFO buffer.At this moment, if leak in the bucket token is arranged, the FIFO buffer just sends data.Data of the every transmission of FIFO buffer, the token in the leakage bucket is " missing " one (promptly the count value to token counter subtracts one) just.Do not have token if leak in the bucket, just stop to send data.By this method, the data that receive of FIFO buffer just send to phase discriminator more equably.Thereby can overcome the sudden influence of IP network packet to a certain extent to the clock recovery device subsequent operation.
In the present invention, phase discriminator and digital oscillator still adopt phase discriminator and digital oscillator conventional in the prior art.Operation principle below in conjunction with Fig. 5 brief description phase discriminator.
As shown in Figure 5, reading clock generally is that frequency is the clock signal about 2M, and the signal that it is read from the FIFO buffer is to be unit with bit (bit), and the write signal that at every turn writes the FIFO buffer is to be unit with byte (Byte).So at first the clock of reading that digital oscillator will be recovered is the read signal of FIFO buffer by the clock detection cell translation, inputs in the FIFO buffer again.Then the reading, writing address of FIFO buffer is delivered to address comparator, obtain FIFO buffer buffer data size according to the comparative result of FIFO buffer reading, writing address.Address comparator is periodically exported the FIFO buffer buffer data size of being obtained under the control of timer.
Digital oscillator is the tranmitting data register that recovers the IP network transmitting terminal of the filtering parameter according to filter output, and obviously filter is the key of clock recovery, and the quality of Design of Filter has directly determined the performance of clock recovery.As previously mentioned, the filter of prior art is the problem that overcomes the sudden recovered clock shake that brings of IP network packet, often will adopt complicated filtering algorithm.Relatively more difficult in the adjustment of filtering parameter, and performance is also relatively poor aspect the multiple IP network of adaptation.Therefore, another key character of the present invention is exactly to design a kind of new filtering method.Fig. 6 is the schematic diagram of this filtering method.As can be seen, with to export the method for filtering parameter according to difference between the capacity of FIFO buffer data in buffer amount and FIFO buffer itself in the filter of prior art different, the filter that adopts filtering method of the present invention is according to FIFO buffer write signal and the data cached quantity of FIFO buffer, calculates filtering parameter K.
According to filter employing of the present invention is two-stage clock control method, the i.e. mode of coarse adjustment+fine setting.As previously mentioned, IP network transmission data exist sudden, and therefore data average discharge in a long time more can reflect the data rate of transmitting terminal truly than data traffic at short notice.Coarse adjustment among the present invention just is being based on this principle, the method for coarse adjustment be long period of time (with second level be unit) in calculate to arrive the data rate of IP network receiving terminal, and and the data rate that calculated in the past be weighted on average.So both can guarantee the flatness of recovered clock, shake not too largely, can utilize historical data again, increase the time of calculating average speed, make that the speed of the result of calculation of average speed and transmitting terminal was more approaching.
The method of fine setting of the present invention is on the basis of coarse adjustment, how much comes to regulate among a small circle the speed that the FIFO buffer sends data according to receiving terminal FIFO buffer data in buffer.The response speed of fine setting is very fast, and the time of sampling is the ms level.If receiving terminal FIFO buffer data in buffer surpasses a half of FIFO buffer buffer memory, strengthen the transmission rate of FIFO buffer.If receiving terminal FIFO buffer data in buffer less than a half of FIFO buffer buffer memory, then reduces the transmission rate of FIFO buffer.
The following describes the computational methods of filter output parameter according to an embodiment of the invention.This method is with following formula calculating filter output parameter K:
K=K
On average+ Δ K------(1)
Wherein: K
On average: the coarse adjustment filter parameter;
Δ K: fine setting filter parameter;
In order to make the clock rate shake that recovers to handle be unlikely to too big, calculating K
On averageThe time used previous K
On averageValue, and shared weight is bigger, K
On averageConcrete computing formula as follows:
Wherein: B: the total amount of byte of in the Δ t time, passing through the FIFO buffer;
Δ t: timing statistics.
K of every Δ t Time Calculation
On averageValue.
Δ K mainly plays the fine setting effect.As previously mentioned, because the IP network data service is sudden, (be K if adopt long-time single-rate
On average) send data, can cause receiving terminal FIFO buffer to overflow or hungry to death, error code or other mistakes can appear like this, and this is unallowed to the TDM business.
The computational methods of Δ K are as follows:
ΔK＝f(ΔD) ------(3)
Δ D=D
Buffer memory-D
Fifo half------(4)
Half difference of the degree of depth (being buffer capacity) of the byte number of Δ D:FIFO buffer buffer memory and FIFO buffer;
D
Buffer memory: the data cached quantity of FIFO buffer of phase discriminator output;
D
Fifo half: half of the FIFO buffer degree of depth;
In the formula, f (Δ D) has adopted piecewise function;
As previously mentioned, employed digital oscillator is conventional device among the present invention.Below in conjunction with Fig. 7 brief description, as shown in Figure 7, this digital oscillator is made up of a N bit adder and N bit trigger.Filtering parameter K (=K by filter output
On average+ Δ K) and the accumulation result SUM[N:0 of N bit trigger output] input in the adder and sue for peace, the peak SUM[N of N bit trigger output] be the clock of reading that recovers.
To fall into claim of the present invention institute restricted portion at the various remodeling that do not depart from inventive concept to technical solution of the present invention.
Claims (10)
1. the TDM business in the IP network is carried out the device of clock recovery, this device comprises phase discriminator, filter and digital oscillator, it is characterized in that,
Also comprise a flow apparatus for shaping, be used for the IP packet that receives is carried out traffic shaping, and send the signal behind traffic shaping to described phase discriminator and filter;
Wherein said filter is the secondary filter, is used for calculating and export filtering parameter according to the output signal of traffic shaping device and the output signal of phase discriminator;
Described digital oscillator is used for according to described filtering parameter and reference clock, obtains the clock of reading that recovers.
2. device according to claim 1 is characterized in that, described traffic shaping device comprises:
Frequency divider is used for reference clock is carried out frequency division;
The token counts device is used for according to the reference clock behind the frequency divider frequency division, increases token number and when data of the every transmission of receiving terminal fifo buffer FIFO, makes the token count value subtract one;
Control device, the data of controlling described receiving terminal FIFO buffer according to the token counts value send.
3. method that the TDM business in the IP network is carried out clock recovery, this method comprises:
1) the IP packet that receives is carried out exporting write signal behind the traffic shaping;
2) according to the clock of reading of this write signal and digital oscillator output, obtain FIFO buffer institute data in buffer amount;
3) according to described write signal and the described FIFO buffer buffer data size calculation of filtered parameter of obtaining;
4) described filtering parameter is sent to digital oscillator, obtain the clock of reading of recovery.
4. method according to claim 3 is characterized in that, described traffic shaping adopts single token bucket algorithm to realize that this algorithm comprises:
1-1) reference clock is carried out frequency division, in leaking bucket, write token with the uniform rate that is slightly larger than the transmitting terminal data rate;
If 1-2) in the leakage bucket token is arranged, then be sent in the reception data of buffer memory in the FIFO buffer, and the token that leaks in the bucket is counted;
When 1-3) not having token in leaking bucket, the FIFO buffer stops to send data.
5. method according to claim 3 is characterized in that, described FIFO buffer data in buffer amount is obtained in the following way:
2-1) read the read signal that clock is converted to the FIFO buffer, input in the phase discriminator with write signal with described;
2-2) reading, writing address of described FIFO buffer being delivered to address comparator compares;
2-3) under the control of timer, regularly export the data cached quantity of described FIFO buffer.
6. method according to claim 3 is characterized in that, described filtering parameter is obtained in the following way:
3-1) calculate the coarse adjustment parameter K
On averageWith fine setting parameter Δ K;
3-2) with described coarse adjustment parameter K
On averageWith fine setting parameter Δ K addition.
7. method according to claim 6, it is characterized in that, described coarse adjustment parameter K on average is by calculating rate of received data in one period scheduled time, and is weighted on average with the data rate of previous calculating and obtains, and the order of magnitude of wherein said one period scheduled time is second.
8. according to claim 6 or 7 described methods, it is characterized in that the average computing formula of described coarse adjustment parameter K is:
Wherein, B: the total amount of byte of in the Δ t time, passing through the FIFO buffer;
Δ t: timing statistics.
9. method according to claim 6, it is characterized in that, described fine setting parameter is to determine like this: determine FIFO buffer data in buffer amount in one period scheduled time, if FIFO buffer data in buffer amount surpasses a half of FIFO buffer buffer memory, strengthen the transmission rate of FIFO buffer, if receiving terminal FIFO buffer data in buffer less than a half of FIFO buffer buffer memory, reduces the transmission rate of FIFO buffer; The order of magnitude of wherein said one period scheduled time is a millisecond.
10. method according to claim 9 is characterized in that, described fine setting CALCULATION OF PARAMETERS formula is as follows:
Wherein: Δ D=D
Buffer memory-D
Fifo half
Half difference of the byte number of Δ D:FIFO buffer buffer memory and the degree of depth of FIFO buffer;
D
Buffer memory: the data cached quantity of FIFO buffer of phase discriminator output;
D
Fifo half: half of the FIFO buffer degree of depth.
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| CNB03149983XA CN1330152C (en) | 2003-08-01 | 2003-08-01 | Apparatus and method for clock recovery for time division multiplexing business |
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| CNB03149983XA CN1330152C (en) | 2003-08-01 | 2003-08-01 | Apparatus and method for clock recovery for time division multiplexing business |
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| CN1330152C true CN1330152C (en) | 2007-08-01 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101674174B (en) * | 2008-09-12 | 2013-06-05 | 华为技术有限公司 | Method and equipment for increasing clock stability |
| CN101599806B (en) * | 2009-06-25 | 2012-07-04 | 杭州再灵电子科技有限公司 | Precise clock recovery method using clock predicting technique |
| CN102301639B (en) * | 2011-07-20 | 2014-07-30 | 华为技术有限公司 | Method and device for correcting clock jitter |
| WO2012083709A1 (en) * | 2011-08-19 | 2012-06-28 | 华为技术有限公司 | Phase discriminator implementation circuit and phase discriminator clock generation method |
| CN102833063B (en) * | 2012-08-24 | 2015-08-19 | 烽火通信科技股份有限公司 | The implementation method of client traffic Clock Extraction in a kind of OTN network |
| CN109286482B (en) * | 2017-07-19 | 2021-12-28 | 深圳市中兴微电子技术有限公司 | Method and device for realizing clock recovery |
| CN112491528A (en) * | 2020-11-20 | 2021-03-12 | 武汉光迅信息技术有限公司 | Method and device for synchronous recovery of communication clock |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1275835A (en) * | 1999-05-26 | 2000-12-06 | 三星电子株式会社 | Circuit and method for restoring digital clock signal |
| US6272103B1 (en) * | 1998-10-28 | 2001-08-07 | Hewlett-Packard Co | Signal attenuation using a filter-limiter connection with a threshold setting network |
| CN1308802A (en) * | 1998-06-30 | 2001-08-15 | 因芬尼昂技术股份公司 | Method for digital timing recovery and selective filtering |
| CN1423490A (en) * | 2001-12-04 | 2003-06-11 | 深圳市中兴通讯股份有限公司上海第二研究所 | Method and apparatus for transmitting network synchronous clock in point to multi-point wireless system |
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2003
- 2003-08-01 CN CNB03149983XA patent/CN1330152C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1308802A (en) * | 1998-06-30 | 2001-08-15 | 因芬尼昂技术股份公司 | Method for digital timing recovery and selective filtering |
| US6272103B1 (en) * | 1998-10-28 | 2001-08-07 | Hewlett-Packard Co | Signal attenuation using a filter-limiter connection with a threshold setting network |
| CN1275835A (en) * | 1999-05-26 | 2000-12-06 | 三星电子株式会社 | Circuit and method for restoring digital clock signal |
| CN1423490A (en) * | 2001-12-04 | 2003-06-11 | 深圳市中兴通讯股份有限公司上海第二研究所 | Method and apparatus for transmitting network synchronous clock in point to multi-point wireless system |
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