CN103795521A - Clock recovery method and device for transmitting EI signals based on Ethernet - Google Patents
Clock recovery method and device for transmitting EI signals based on Ethernet Download PDFInfo
- Publication number
- CN103795521A CN103795521A CN201410039177.2A CN201410039177A CN103795521A CN 103795521 A CN103795521 A CN 103795521A CN 201410039177 A CN201410039177 A CN 201410039177A CN 103795521 A CN103795521 A CN 103795521A
- Authority
- CN
- China
- Prior art keywords
- clock
- phase
- output
- locked loop
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention relates to a clock recovery method for transmitting EI signals based on the Ethernet. The clock recovery method includes the steps that an EI data package coming from the Ethernet is stored in an FIFO memorizer and buffered, the data package is read through a tooth missing clock CLKG, and EI data of clock tooth missing are output by the FIFO memorizer; the EI data of clock tooth missing are stored in an elastic memorizer, a phase-locked loop outputs synchronizing signals to the elastic memorizer, meanwhile output of the phase-locked loop is input as feedback, the phase-locked loop controls the output clock frequency of the elastic memorizer by monitoring difference between a reading pointer and a writing pointer of the elastic memorizer, if the difference between the reading pointer and the writing pointer is larger than a set value, the clock frequency of the output of the phase-locked loop is reduced, otherwise, the clock frequency of the output of the phase-locked loop is increased, and the elastic memorizer outputs the EI data with clock smoothed. The invention further discloses a clock recovery device for transmitting the EI signals based on the Ethernet. A clock is recovered with two-level buffering adjustment to reduce phase position diffuse movement, smooth missed teeth and recover the clock meeting the related ITU-TG. 823 requirements; a good diffuse movement performance index can be achieved without changing a frame structure.
Description
Technical field
The present invention relates to Communication and Information Systems network transmission technology field, especially a kind of clock recovery method and device that transmits E1 signal based on Ethernet.
Background technology
In IP-based New Generation of Communication, in order to realize multi-service transmission, at transmitting terminal, real time business (TDM) processing of pack, make its packet that becomes Ethernet bag, then transmit; At receiving terminal, in order to recover original TDM business, data are added up and jitter elimination, thus the timing information of acquisition code stream.Due in TDMoIP system, the signal that need to send at transmitting terminal is the E1 signal of standard, in order to transmit in Ethernet, E1 signal is split, encapsulated, make its Ethernet bag that becomes fixed size, the timing information in E1 signal originally is all lost, in the signal of receiving at receiving terminal, do not contain any timing information, the shake of data also becomes random, and this just need to carry out special processing at receiving terminal, could recover the clock of E1 signal.
When general multiplexing equipment receives data bit flow, on phase-locked loop with one, second-order low-pass filter gives smoothly to obtain clock recovery up to specification.But the shortcoming of the clock phase detector that this phase-locked loop uses is exactly that resolution can only reach a bit, in the time that recovered clock very approaches actual value, differ and will be accumulated to a bit, need for a long time, this will produce unrestrained moving, and is difficult to meet the unrestrained specification requirement that moves.Due to the characteristic of Ethernet, the time of packet arrival destination has the variation of randomness, even may substitute in addition.And bag data belong to large block bursty data, a bag is come, be exactly hundreds of is even gone up kilobytes and come, the write pointer of elastic store changes and belongs to great-jump-forward, this situation, the detection filter that phase place changes, cannot complete from detecting the general low-pass filtering mode of the poor process of pointer.
Summary of the invention
Primary and foremost purpose of the present invention is to provide a kind of and is being issued to the better unrestrained clock recovery method based on Ethernet transmission E1 signal that moves performance index without the situation of change frame structure.
For achieving the above object, the present invention has adopted following technical scheme: a kind of clock recovery method that transmits E1 signal based on Ethernet, and the method comprises the step of following order:
(1) first order coarse adjustment: clock CLK
hafter pinching sunken processing, obtain hypodontia clock CLK
g, deposit the E1 packet from Ethernet in FIFO memorizer buffer, and with hypodontia clock CLK
gread the E1 data of FIFO memory output clock hypodontia;
(2) second level fine tuning: deposit the E1 data of clock hypodontia in elastic store, hypodontia clock CLK
gas the input of phase-locked loop, phase-locked loop output synchronizing signal is to elastic store, the output of phase-locked loop is as its feed back input simultaneously, phase-locked loop is by monitoring poor its output clock frequency of mode control of elastic store reading and writing pointer, if the poor set point that is greater than of reading and writing pointer reduces the clock frequency that phase-locked loop is exported, otherwise, increase the clock frequency of phase-locked loop output, final, the E1 data that elastic store output clock is level and smooth.
Described clock CLK
hfrequency be 2.048MHz+100ppm.
To clock CLK
hpinch to fall into and process the hypodontia clock CLK making after adjustment
gthe E1 clock that can follow the tracks of input, concrete grammar is:
(1) receiving terminal exceedes 3ms and does not receive packet, forces to pinch clock CLK
ha pulse;
(2) pinch fall into interval greater than equaling 2.5ms, pinch fall into opportunity in the moment that harvests a bag, judge whether the data in FIFO memory are " sky ", as be " sky ", pinch CLK
ha pulse, the data in described FIFO memory refer to that for " sky " FIFO memory storage space reaches the lower threshold of setting.
The computing formula of described FIFO memory storage space lower limit is as follows:
If ethernet line transmission speed is V
e, unit is Mbps, in the time of its long data bag 1518 bytes transmission E1 data, FIFO memory should not overflow, and extrapolates accordingly FIFO memory lower limit memory capacity C
f:
C
f=1518*2.048/ V
ebyte.
Another object of the present invention is to provide a kind of clock recovery device that transmits E1 signal based on Ethernet, comprise FIFO memory, its one end input receives the E1 packet from Ethernet, and other end input receives hypodontia clock CLK
g, its output is connected with the input of elastic store, and elastic store output read-write pointer difference signal is to phase-locked loop, and the input of phase-locked loop receives hypodontia clock CLK
g, the output of phase-locked loop is as its feed back input, and the output of phase-locked loop is connected with the input of elastic store, and the output of elastic store is as device output.
Hypodontia clock CLK
gby clock CLK
hobtain through pinching sunken treatment circuit.
As shown from the above technical solution, the present invention regulates recovered clock with two-stage buffering, and the first order is coarse adjustment, and former packet is through FIFO memorizer buffer, by the read signal clock CLK of 2.048MHz+100ppm
hread, indicate CLK by the data " sky " that detect FIFO memory
hpulse is pinched sunken, produces hypodontia clock CLK
g; The second level is fine tuning, by hypodontia clock CLK
ge1 data deposit elastic store in, the continuous clock being produced by phase-locked loop is read, by monitoring the poor control phase-locked loop of reading and writing pointer, be greater than set point and do frequency reduction of speed, be less than set point and do frequency acceleration, to reduce, phase place is unrestrained moves, level and smooth hypodontia, recover and meet the G.823 clock of related request of ITU-T, just can reach the unrestrained performance index of moving preferably without change frame structure.
Accompanying drawing explanation
Fig. 1 is method flow diagram of the present invention;
Fig. 2 is the effect schematic diagram that transmits E1 signal and Ethernet data by the SDSL of 2.304Mbps.
Embodiment
A clock recovery method that transmits E1 signal based on Ethernet, the method comprises the step of following order: (1) first order coarse adjustment: clock CLK
hafter pinching sunken processing, obtain hypodontia clock CLK
g, deposit the E1 packet from Ethernet in FIFO memory 1 and cushion, and with hypodontia clock CLK
gread the E1 data of FIFO memory 1 output clock hypodontia; (2) second level fine tuning: deposit the E1 data of clock hypodontia in elastic store 2, hypodontia clock CLK
gas the input of phase-locked loop 3, phase-locked loop 3 is exported synchronizing signal to elastic store 2, the output of phase-locked loop 3 is as its feed back input simultaneously, phase-locked loop 3 is by monitoring poor its output clock frequency of mode control of elastic store 2 reading and writing pointers, if the poor set point that is greater than of reading and writing pointer reduces the clock frequency that phase-locked loop 3 is exported, otherwise, increase the clock frequency that phase-locked loop 3 is exported, final, the E1 data that elastic store 2 output clocks are level and smooth.As shown in Figure 1.Set point is one of parameter of phase-locked loop 3, utilizes ppu to set phase-locked loop 3 parameter registers.
Described clock CLK
hfrequency be 2.048MHz+100ppm, as shown in Figure 1, clock CLK
hthe system of selection of frequency: 1) be not less than the E1 signal rate upper limit, i.e. 2.048MHz+50ppm; 2) consider clock CLK
hitself may have the deviation of 50ppm, be therefore 2.048MHz+100ppm.
Continuous maximum rate is the E1 data of 2.048MHz+50ppm, is packaged into random Ethernet data bag at transmitting terminal, is sent to receiving terminal.First these packets deposit enough large FIFO memory 1 in, and with the clock CLK of a 2.048MHz+100ppm
hread, for guarantee one-level adjust after clock can follow the tracks of input E1 signal clock, need to be to clock CLK
hpulse pinch fall into process.To clock CLK
hpinch to fall into and process the hypodontia clock CLK making after adjustment
gthe E1 clock that can follow the tracks of input, concrete grammar is: (1) receiving terminal exceedes 3ms and do not receive packet, forces to pinch clock CLK
ha pulse; (2) pinch fall into interval greater than equaling 2.5ms, pinch fall into opportunity in the moment that harvests a bag, judge whether the data in FIFO memory 1 are " sky ", as be " sky ", pinch CLK
ha pulse, the data in described FIFO memory 1 refer to that for " sky " FIFO memory 1 memory space reaches the lower threshold of setting.
The computing formula of described FIFO memory 1 memory space lower limit is as follows: if ethernet line transmission speed is V
e, unit is Mbps, in the time of its long data bag 1518 bytes transmission E1 data, FIFO memory 1 should not overflow, and extrapolates accordingly FIFO memory 1 lower limit memory capacity C
f:
C
f=1518*2.048/ V
ebyte.
As shown in Figure 1, this device comprises FIFO memory 1, and its one end input receives the E1 packet from Ethernet, and other end input receives hypodontia clock CLK
g, its output is connected with the input of elastic store 2, and elastic store 2 output read-write pointer difference signals are to phase-locked loop 3, and the input of phase-locked loop 3 receives hypodontia clock CLK
g, the output of phase-locked loop 3 is as its feed back input, and the output of phase-locked loop 3 is connected with the input of elastic store 2, and the output of elastic store 2 is as device output.Hypodontia clock CLK
gby clock CLK
hobtain through pinching sunken treatment circuit.
Due to the characteristic of Ethernet, the time of E1 packet arrival destination has the variation of randomness, even may substitute.In addition, the data of packet belong to large block bursty data, and a packet is come, and are exactly that hundreds of is even gone up kilobytes, and the write pointer of elastic store 2 changes and to belong to great-jump-forward.Under these circumstances, cannot complete the poor detection of pointer by general low-pass filtering mode.Even if ignore the situation of substitute, Etherloop transmission has QoS to guarantee bandwidth, and the time behavior mutagenic factor that packet arrives receiving terminal through Etherloop still exists.
The first half of Fig. 2, the part " expiring " more than baseline from FIFO can be found out, an E1 bag, transmit the Ethernet data bag of E1 signal, 256 bytes, the ordinary circumstance E1 Inter-arrival Time time should count between μ s in 1.0 ms +/-, and transmit leg inserts multiplexing Ethernet data bag (1518 byte) after having given several E1 bags, must wait for that this bag has passed (about 6ms) and could transmit E1 bag again.The E1 data acquisition conveyer of buffer memory can time, can digest at full speed the interval that accumulation buffer memory (the about 0.89ms of inter-packet gap) returns normal approximately 1.0 ms afterwards with 2.304Mbps and transmit.
The FIFO memory buffer that receives E1 bag will have enough capacity, is specifically calculated as follows:
C
f=1518*2.048/ V
e=1518*2.048/2.304=1350 byte
Therefore, the rear FIFO memory 1 of start will wait to fill up more than 1350 bytes and could start and read.
The latter half of Fig. 2 has provided the top envelope curve of FIFO pointer and FIFO " expires ", relation between " sky " baseline.The gap that the top dotted line envelope connecting into of pointer " is expired " baseline with FIFO is proportional to actual signal speed and reads clock CLK
hspeed difference, consequent hypodontia clock exists larger unrestrained moving.Therefore, must be through level 2 buffering and the chock smotthing being formed by elastic store 2 and phase-locked loop 3, to reduce, phase place is unrestrained moves, and level and smooth hypodontia, could finally obtain recovered clock up to specification.
In sum, the present invention regulates recovered clock with two-stage buffering, and the first order is coarse adjustment, and former packet cushions through FIFO memory 1, by the read signal clock CLK of 2.048MHz+100ppm
hread, indicate CLK by the data " sky " that detect FIFO memory 1
hpulse is pinched sunken, produces hypodontia clock CLK
g; The second level is fine tuning, by hypodontia clock CLK
ge1 data deposit elastic store 2 in, the continuous clock being produced by phase-locked loop 3 is read, by monitoring the poor control phase-locked loop 3 of reading and writing pointer, be greater than set point and do frequency reduction of speed, be less than set point and do frequency acceleration, to reduce, phase place is unrestrained moves, level and smooth hypodontia, recover and meet the G.823 clock of related request of ITU-T, just can reach the unrestrained performance index of moving preferably without change frame structure.
Claims (6)
1. a clock recovery method that transmits E1 signal based on Ethernet, the method comprises the step of following order:
(1) first order coarse adjustment: clock CLK
hafter pinching sunken processing, obtain hypodontia clock CLK
g, deposit the E1 packet from Ethernet in FIFO memorizer buffer, and with hypodontia clock CLK
gread the E1 data of FIFO memory output clock hypodontia;
(2) second level fine tuning: deposit the E1 data of clock hypodontia in elastic store, hypodontia clock CLK
gas the input of phase-locked loop, phase-locked loop output synchronizing signal is to elastic store, the output of phase-locked loop is as its feed back input simultaneously, phase-locked loop is by monitoring poor its output clock frequency of mode control of elastic store reading and writing pointer, if the poor set point that is greater than of reading and writing pointer reduces the clock frequency that phase-locked loop is exported, otherwise, increase the clock frequency of phase-locked loop output, final, the E1 data that elastic store output clock is level and smooth.
2. the clock recovery method that transmits E1 signal based on Ethernet according to claim 1, is characterized in that: described clock CLK
hfrequency be 2.048MHz+100ppm.
3. the clock recovery method that transmits E1 signal based on Ethernet according to claim 1, is characterized in that: to clock CLK
hpinch to fall into and process the hypodontia clock CLK making after adjustment
gthe E1 clock that can follow the tracks of input, concrete grammar is:
(1) receiving terminal exceedes 3ms and does not receive packet, forces to pinch clock CLK
ha pulse;
(2) pinch fall into interval greater than equaling 2.5ms, pinch fall into opportunity in the moment that harvests a bag, judge whether the data in FIFO memory are " sky ", as be " sky ", pinch CLK
ha pulse, the data in described FIFO memory refer to that for " sky " FIFO memory storage space reaches the lower threshold of setting.
4. the clock recovery method that transmits E1 signal based on Ethernet according to claim 3, is characterized in that: the computing formula of described FIFO memory storage space lower limit is as follows:
If ethernet line transmission speed is V
e, unit is Mbps, in the time of its long data bag 1518 bytes transmission E1 data, FIFO memory should not overflow, and extrapolates accordingly FIFO memory lower limit memory capacity C
f:
C
f=1518*2.048/ V
ebyte.
5. implement the claims in 1 to 4 the device of clock recovery method described in any one, it is characterized in that: comprise FIFO memory, its one end input receives the E1 packet from Ethernet, and other end input receives hypodontia clock CLK
g, its output is connected with the input of elastic store, and elastic store output read-write pointer difference signal is to phase-locked loop, and the input of phase-locked loop receives hypodontia clock CLK
g, the output of phase-locked loop is as its feed back input, and the output of phase-locked loop is connected with the input of elastic store, and the output of elastic store is as device output.
6. device according to claim 5, is characterized in that: hypodontia clock CLK
gby clock CLK
hobtain through pinching sunken treatment circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410039177.2A CN103795521B (en) | 2014-01-27 | 2014-01-27 | Clock recovery method and device for transmitting EI signals based on Ethernet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410039177.2A CN103795521B (en) | 2014-01-27 | 2014-01-27 | Clock recovery method and device for transmitting EI signals based on Ethernet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103795521A true CN103795521A (en) | 2014-05-14 |
| CN103795521B CN103795521B (en) | 2017-01-25 |
Family
ID=50670857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410039177.2A Active CN103795521B (en) | 2014-01-27 | 2014-01-27 | Clock recovery method and device for transmitting EI signals based on Ethernet |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103795521B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106612114A (en) * | 2015-10-21 | 2017-05-03 | 扬智科技股份有限公司 | Clock recovery device and clock recovery method |
| EP3195133A1 (en) * | 2014-09-15 | 2017-07-26 | Xilinx, Inc. | Lane-to-lane-de-skew for transmitters |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0876016A1 (en) * | 1997-05-02 | 1998-11-04 | Lsi Logic Corporation | Adaptive digital clock recovery |
| CN1301100A (en) * | 1999-12-17 | 2001-06-27 | 米特尔公司 | Clock resetting phase-locked loops |
-
2014
- 2014-01-27 CN CN201410039177.2A patent/CN103795521B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0876016A1 (en) * | 1997-05-02 | 1998-11-04 | Lsi Logic Corporation | Adaptive digital clock recovery |
| CN1301100A (en) * | 1999-12-17 | 2001-06-27 | 米特尔公司 | Clock resetting phase-locked loops |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3195133A1 (en) * | 2014-09-15 | 2017-07-26 | Xilinx, Inc. | Lane-to-lane-de-skew for transmitters |
| CN106612114A (en) * | 2015-10-21 | 2017-05-03 | 扬智科技股份有限公司 | Clock recovery device and clock recovery method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103795521B (en) | 2017-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101707506B (en) | Business clock transparent transmission method and system in optical transport network | |
| CN101820324B (en) | Synchronous transmission method and system for asynchronous data | |
| JP2861515B2 (en) | Clock synchronizer and clock synchronizer between transmission and reception in packet network | |
| CN101299647B (en) | Apparatus and method for implementing nondestructive switch of SDH service | |
| CN101207452B (en) | Sending device and receiving device | |
| KR100715736B1 (en) | Adaptive clock recovery | |
| US20070214291A1 (en) | Elasticity buffer for streaming data | |
| US5594763A (en) | Fast synchronizing digital phase-locked loop for recovering clock information from encoded data | |
| CN102769455B (en) | High speed input/output interface and receiving circuit thereof | |
| CN101233706A (en) | Data stream synchronization | |
| WO2007077739A1 (en) | Transmission device and reception device | |
| CN101803254A (en) | Reverse timestamp method and network node for clock recovery | |
| CN105337914B (en) | A kind of asynchronous serial communication method of reseptance and protective device based on 1B4B codings | |
| CN103795521A (en) | Clock recovery method and device for transmitting EI signals based on Ethernet | |
| US9356770B2 (en) | Oversampling CDR which compensates frequency difference without elasticity buffer | |
| US7424076B2 (en) | System and method for providing synchronization information to a receiver | |
| CN101621346B (en) | Source synchronous receiving device with adaptive feedback and source synchronizing method | |
| CN103414452B (en) | Clock data recovery device and electronic equipment | |
| CN1852087B (en) | Clock Synchronization Method and Implementation Device in Packet Switching Network | |
| US9112625B2 (en) | Method and apparatus for emulating stream clock signal in asynchronous data transmission | |
| CN202841098U (en) | High-speed input/output interface and receiving circuit thereof | |
| CN1316762C (en) | Circuit and method for receiving data | |
| JP3909029B2 (en) | Terminal synchronization method and terminal synchronization circuit | |
| US8363764B2 (en) | Method and device for reconstructing a data clock from asynchronously transmitted data packets | |
| CN118625890B (en) | Clock recovery system and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210118 Address after: 201600 room 539, building 1, 777 sizhuan Road, Sijing Town, Songjiang District, Shanghai Patentee after: Keda Zhizao (Shanghai) equipment Technology Co.,Ltd. Address before: No. 612, Huangshan Road, high tech Zone, Hefei City, Anhui Province, 230088 Patentee before: HKUST INTELLIGENT (HEFEI) Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230525 Address after: 215163 No.110 kejing Road, high tech Zone, Suzhou City, Jiangsu Province Patentee after: HUAXIAO PRECISION (SUZHOU) Co.,Ltd. Address before: 201600 room 539, building 1, 777 sizhuan Road, Sijing Town, Songjiang District, Shanghai Patentee before: Keda Zhizao (Shanghai) equipment Technology Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20140514 Assignee: Syntronic (Beijing) R&D Center Co.,Ltd. Assignor: HUAXIAO PRECISION (SUZHOU) Co.,Ltd. Contract record no.: X2023980045859 Denomination of invention: A Clock Recovery Method and Device for Transferring E1 Signal Based on Ethernet Granted publication date: 20170125 License type: Exclusive License Record date: 20231107 |
|
| EE01 | Entry into force of recordation of patent licensing contract |