CN109286482B - Method and device for realizing clock recovery - Google Patents

Abstract

A method and device for realizing clock recovery, comprising: calculating the amount of input data according to the time error of the input data; calculating the amount of output data using the frequency of the recovered clock; Data volume difference; update the frequency of the recovered clock according to the obtained first data volume difference. According to the amount of input data and the amount of output data obtained by calculation, the embodiment of the present invention shortens the time for obtaining the recovered clock and reduces the consumption of cache resources; further, the embodiment of the present invention is based on the amount of actual input data and the amount of actual output data. The calculation of the second data volume difference adjusts the input data volume obtained by calculation, thereby improving the precision of the recovered clock obtained by calculation.

Description

A method and apparatus for realizing clock recovery

technical field

This article relates to, but is not limited to, data transmission technology, especially a method and apparatus for realizing clock recovery.

Background technique

In the development of transmission technology, optical fiber has proved to be an indispensable medium. The development of optical transmission has basically gone through the following stages: space division multiplexing (SDM) stage, time division multiplexing (TDM) stage and wavelength division multiplexing (WDM) stage.

At present, the wired transmission is still dominated by the WDM system. With the development of communication technology, the commercial 40 gigabit (G) wavelength division transmission has gradually evolved to 100G and 400G transmission; the data transmission distance is also constantly expanding. The WDM system will use the digital signal processing (DSP) method in the transmission process, which is called 100G DSP processing in this paper.

100G DSP processing needs to recover the clock information from the data stream at the receiving end. It is required that the clock of the receiving end can recover the clock of the sending end, that is, clock recovery is performed. Since the processing rate of 100G DSP often has short-term bursts, the recovery clock rate must be stable. , in the long run, the data source rate must be accurately tracked to achieve smooth and continuous data processing. The processing method in the related art is: integrating the amount of data in a period of time, including: collecting the time interval arriving in a clock recovery period, processing the time interval with a filter, and estimating the frequency of the recovered clock of the data at the sender. The above methods usually have the following problems: long extraction clock time; unstable operation for a long time; relying on data cache, which is easy to cause problems such as resource consumption.

SUMMARY OF THE INVENTION

The following is an overview of the topics detailed in this article. This summary is not intended to limit the scope of protection of the claims.

Embodiments of the present invention provide a method and device for realizing clock recovery, which can shorten the time for obtaining the recovered clock and reduce the consumption of cache resources.

An embodiment of the present invention provides a method for implementing clock recovery, including:

Calculate the amount of input data according to the time error of the input data;

Calculate the amount of output data using the frequency of the recovered clock;

Comparing the difference between the input data amount and the output data amount obtained by the calculation to obtain the first data amount difference;

The frequency of the recovered clock is updated according to the obtained first data amount difference.

Optionally, the method further includes:

Calculate the difference between the actual input data amount and the actual output data amount to obtain the second data amount difference;

The calculated input data volume is adjusted according to the calculated second data volume difference.

Optionally, the adjusting the calculated input data amount according to the calculated second data amount difference includes:

Perform filtering processing on the second data amount difference obtained by calculation;

Determine whether the data cache water level is lower than a preset expected value according to the filtered second data volume difference;

When it is determined that the data cache water level is lower than the preset expected value, the amount of the input data obtained by calculation is reduced according to the first preset strategy; when it is determined that the data cache water level is higher than the preset expected value, the amount of the input data obtained by calculation is increased according to the second preset strategy. the amount of input data.

Optionally, the calculating the amount of input data according to the time error of the input data includes:

Extract the time error after performing phase detection on the input data, and calculate the phase detection result according to the extracted time error;

After filtering the phase detection result obtained by calculation, a corresponding phase detection value is obtained, and the adjustment instruction information for adding or deleting the input data is determined according to the obtained phase detection value;

The amount of input data is calculated according to the determined adjustment instruction information.

Optionally, the frequency of updating the recovered clock according to the obtained first data amount difference includes:

performing filtering processing on the first data amount difference obtained by comparison;

converting the first data amount difference after the filtering process into an analog voltage amount;

The frequency of the recovered clock is updated by the converted analog voltage quantity.

Optionally, the method further includes:

Phase adjustment is performed on the input data according to the obtained phase detection value.

Optionally, the method further includes:

Data output is performed according to the updated frequency of the recovered clock.

On the other hand, an embodiment of the present invention also provides an apparatus for implementing clock recovery, including: a first calculation unit, a second calculation unit, a first difference unit, and an update unit; wherein,

The first calculation unit is used for: calculating the input data amount according to the time error of the input data, and sending the calculated input data amount to the first difference unit;

The second calculation unit is used for: calculating the output data amount using the frequency of the recovered clock, and sending the output data amount obtained by the calculation to the first difference unit;

The first difference unit is used for: comparing the difference between the input data amount and the output data amount obtained by the calculation to obtain the first data amount difference;

The updating unit is configured to: update the frequency of the recovered clock according to the obtained first data amount difference.

Optionally, the device further includes: a second difference unit and an adjustment unit; wherein,

The second difference unit is used to: calculate the difference between the actual input data amount and the actual output data amount, and obtain the second data amount difference;

The adjustment unit is configured to: adjust the input data amount obtained by calculation according to the difference value of the second data amount obtained by calculation.

Optionally, the adjustment unit includes a first filter module and an adjustment module; wherein,

The first filtering module is used for: filtering the second data amount difference obtained by calculation;

The adjustment module is used to: determine whether the data cache water level is lower than a preset expected value according to the second data volume difference after filtering processing; when it is determined that the data cache water level is lower than the preset expected value, reduce the number of times according to the first preset strategy. The amount of input data received by a difference unit; when it is determined that the data buffer water level is higher than a preset expected value, the amount of input data received by the first difference unit is increased according to a second preset strategy.

Optionally, the first calculation unit includes a phase detection module and a second filter module; wherein,

The phase detection module is used to: extract the time error after performing phase detection on the input data, and calculate the phase detection result according to the extracted time error;

The second filtering module is used for: filtering the obtained phase detection result to obtain the corresponding phase detection value, and determining the adjustment instruction information for adding and deleting the input data according to the obtained phase detection value; according to the determined adjustment instruction information Calculate the amount of data entered.

Optionally, the update unit includes a third filter module, a digital-to-analog conversion module, and a voltage-controlled oscillation module; wherein,

The third filtering module is used for: filtering the first data amount difference obtained by comparison;

The digital-to-analog conversion module is used for: converting the difference of the first data amount after the filtering process into an analog voltage amount;

The voltage-controlled oscillation module is used for: updating the frequency of the recovered clock through the analog voltage obtained by conversion.

Optionally, the apparatus further includes a phase adjustment unit, configured to perform phase adjustment on the input data according to the obtained phase detection value.

Optionally, the apparatus includes an output unit configured to output data according to the updated frequency of the recovered clock.

Compared with the related art, the technical solution of the present application includes: calculating the amount of input data according to the time error of the input data; calculating the amount of output data by using the frequency of the recovered clock; Data volume difference; update the frequency of the recovered clock according to the obtained first data volume difference. According to the amount of input data and the amount of output data obtained by calculation, the embodiment of the present invention shortens the time for obtaining the recovered clock and reduces the consumption of cache resources; further, the embodiment of the present invention is based on the amount of actual input data and the amount of actual output data. The calculation of the second data volume difference adjusts the input data volume obtained by calculation, thereby improving the precision of the recovered clock obtained by calculation.

Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the description, claims and drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the specification. They are used to explain the technical solutions of the present invention together with the embodiments of the present application, and do not limit the technical solutions of the present invention.

1 is a flowchart of a method for implementing clock recovery according to an embodiment of the present invention;

FIG. 2 is a structural block diagram of an apparatus for implementing clock recovery according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, the embodiments in the present application and the features in the embodiments may be arbitrarily combined with each other if there is no conflict.

The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.

FIG. 1 is a flowchart of a method for implementing clock recovery according to an embodiment of the present invention, as shown in FIG. 1 , including:

Step 100: Calculate the amount of input data according to the time error of the input data;

Optionally, calculating the amount of input data according to the time error of the input data in this embodiment of the present invention includes:

Extract the time error after performing phase detection on the input data, and calculate the phase detection result according to the extracted time error;

After filtering the phase detection result obtained by calculation, a corresponding phase detection value is obtained, and the adjustment instruction information for adding or deleting the input data is determined according to the obtained phase detection value;

The amount of input data is calculated according to the determined adjustment instruction information.

It should be noted that due to the difference between the local reference clock and the reference clock of the transmitting end, sampling errors will occur when the data is sampled by the local reference clock. Therefore, the input data can be extracted and processed for the time error; the calculated phase detection result is filtered. , which can eliminate high-frequency jitter and track time error changes, so that the open-loop clock recovery is equivalent to the closed-loop clock recovery effect without loop delay. The adjustment indication information in the embodiment of the present invention may include: +1, -1, 0; wherein, +1 indicates that the output data is added by one sampling point, -1 indicates that the output data deletes one sampling point, and 0 indicates that the output data sampling point The number does not change.

Step 101, using the frequency of the recovered clock to calculate the amount of output data;

It should be noted that the initial value of the frequency of the recovered clock in this embodiment of the present invention may be set as a default frequency value with reference to the related art; when the updated frequency of the recovered clock is obtained, the output data amount is calculated using the updated frequency of the recovered clock. The recovered clock in the embodiment of the present invention includes the recovered clock of the receiving end.

Step 102: Comparing the difference between the input data volume and the output data volume obtained by the calculation to obtain a first data volume difference;

It should be noted that, the comparison in the embodiment of the present invention may be performed according to the virtual cache, so the consumption of cache resources can be reduced. The write side of the virtual cache in the embodiment of the present invention is the adjusted data rate, the read side and the read side of the data cache have the same rate, and the virtual cache is represented as an asynchronous first-in-first-out (FIFO) with no storage volatile random access memory (RAM). The control logic is essentially an up-down counter, and the count result shows the data rate difference between the read and write sides, as well as the difference between the recovered clock and the original transmit clock. The input data volume of the virtual buffer is controlled by the filtering result of the data buffer loop, so as to realize the response to the data buffer loop control.

Step 103: Update the frequency of the recovered clock according to the obtained first data amount difference.

Optionally, in this embodiment of the present invention, the frequency of updating the recovered clock according to the obtained first data amount difference includes:

performing filtering processing on the first data amount difference obtained by comparison;

converting the first data amount difference after the filtering process into an analog voltage amount;

The frequency of the recovered clock is updated by the converted analog voltage quantity.

It should be noted that, when filtering the first data amount difference obtained by comparison, high-frequency jitter can be eliminated and error changes can be tracked, especially slow drift. The filtering process can support multiple sets of coefficients to distinguish coarse capture, fine capture, tracking and other states to achieve rapid convergence and stable tracking. The frequency of updating the recovered clock by the analog voltage obtained by conversion in this embodiment of the present invention may be implemented by using a voltage-controlled oscillator. Assuming that the voltage-controlled oscillator operates at the target frequency f, its adjustable range is ±X, and X should be Greater than the maximum variation range of the data source clock, the analog voltage determines the frequency of the VCO. When the analog voltage is the largest, it corresponds to the frequency point f+X, and when the analog voltage is the smallest, it corresponds to fX, and the analog voltage has a linear relationship with the output frequency of the VCO. Therefore, the higher the precision of the analog voltage, the higher the precision of the voltage-controlled oscillator that can be controlled. If the digital quantity before digital-to-analog conversion is N bits, the control precision is (2X/ ^2N ), that is, the first difference filtered The bit width of the result.

Optionally, the method according to the embodiment of the present invention further includes:

Calculate the difference between the actual input data amount and the actual output data amount to obtain the second data amount difference;

The calculated input data volume is adjusted according to the calculated second data volume difference.

Optionally, in this embodiment of the present invention, adjusting the amount of input data obtained by calculation according to the difference in the second data amount obtained by calculation includes:

Perform filtering processing on the second data amount difference obtained by calculation;

Determine whether the data cache water level is lower than a preset expected value according to the filtered second data volume difference;

When it is determined that the data cache water level is lower than the preset expected value, the amount of the input data obtained by calculation is reduced according to the first preset strategy; when it is determined that the data cache water level is higher than the preset expected value, the amount of the input data obtained by calculation is increased according to the second preset strategy. the amount of input data.

Optionally, the method according to the embodiment of the present invention further includes:

Phase adjustment is performed on the input data according to the obtained phase detection value.

Optionally, the method according to the embodiment of the present invention further includes:

Data output is performed according to the frequency of the updated recovered clock.

Compared with the related art, the technical solution of the present application includes: calculating the amount of input data according to the time error of the input data; calculating the amount of output data by using the frequency of the recovered clock; Data volume difference; update the frequency of the recovered clock according to the obtained first data volume difference. According to the amount of input data and the amount of output data obtained by calculation, the embodiment of the present invention shortens the time for obtaining the recovered clock and reduces the consumption of cache resources; further, the embodiment of the present invention is based on the amount of actual input data and the amount of actual output data. The calculation of the second data volume difference adjusts the input data volume obtained by calculation, thereby improving the precision of the recovered clock obtained by calculation.

FIG. 2 is a structural block diagram of an apparatus for implementing clock recovery according to an embodiment of the present invention. As shown in FIG. 2 , it includes: a first calculation unit, a second calculation unit, a first difference unit, and an update unit; wherein,

The first calculation unit is used for: calculating the input data amount according to the time error of the input data, and sending the calculated input data amount to the first difference unit;

Optionally, the first calculation unit in this embodiment of the present invention includes a phase detection module and a second filter module; wherein,

The phase detection module is used to: extract the time error after performing phase detection on the input data, and calculate the phase detection result according to the extracted time error;

The second filtering module is used for: filtering the obtained phase detection result to obtain the corresponding phase detection value, and determining the adjustment instruction information for adding and deleting the input data according to the obtained phase detection value; according to the determined adjustment instruction information Calculate the amount of data entered.

It should be noted that the adjustment indication information in the embodiment of the present invention may include: +1, -1, 0; wherein, +1 indicates that the output data is added by one sampling point, -1 indicates that the output data deletes one sampling point, and 0 indicates that the output The number of data sampling points remains unchanged. When filtering the phase detection result in the embodiment of the present invention, how to select and set the filter according to the phase detection result can be determined by those skilled in the art according to the phase detection result and the accuracy requirements of adding, deleting and adjusting the input data.

The second calculation unit is used for: calculating the output data amount using the frequency of the recovered clock, and sending the output data amount obtained by the calculation to the first difference unit;

It should be noted that, for the initial value of the frequency of the recovered clock in the embodiment of the present invention, a default value may be set with reference to the related art.

The first difference unit is used for: comparing the difference between the input data amount and the output data amount obtained by the calculation to obtain the first data amount difference;

It should be noted that the comparison in the embodiment of the present invention can be performed according to the virtual cache, that is, it is only necessary to compare the amount of input data and the amount of output data obtained by the calculation, thereby reducing the consumption of cache resources;

The updating unit is configured to: update the frequency of the recovered clock according to the obtained first data amount difference.

Optionally, the update unit in this embodiment of the present invention includes a third filter module, a digital-to-analog conversion module, and a voltage-controlled oscillation module; wherein,

The third filtering module is used for: filtering the first data amount difference obtained by comparison;

The digital-to-analog conversion module is used for: converting the difference of the first data quantity after filtering and processing to an analog voltage quantity;

The voltage-controlled oscillator module is used to update the frequency of the recovered clock through the analog voltage obtained by conversion.

It should be noted that, in the embodiment of the present invention, when filtering the obtained first data amount difference, how to select and set the filter can be determined by those skilled in the art according to the accuracy requirements for obtaining the recovered clock. The update of the frequency of the recovered clock according to the analog voltage can be determined by analyzing and determining the relationship between the analog voltage and the frequency of the recovered clock in the related art.

Optionally, the device according to the embodiment of the present invention further includes: a second difference unit and an adjustment unit; wherein,

The second difference unit is used to: calculate the difference between the actual input data amount and the actual output data amount, and obtain the second data amount difference;

The adjustment unit is configured to: adjust the input data amount obtained by calculation according to the difference value of the second data amount obtained by calculation.

Optionally, the adjustment unit in this embodiment of the present invention includes a first filtering module and an adjustment module; wherein,

The first filtering module is used for: filtering the second data amount difference obtained by calculation;

The adjustment module is used to: determine whether the data cache water level is lower than a preset expected value according to the second data volume difference after filtering processing; when it is determined that the data cache water level is lower than the preset expected value, reduce the number of times according to the first preset strategy. The amount of input data received by a difference unit; when it is determined that the data buffer water level is higher than a preset expected value, the amount of input data received by the first difference unit is increased according to a second preset strategy. Here, the cache water level is an existing definition in the related art, and the expected value may be 50% of the total amount of cached data.

Optionally, the apparatus according to the embodiment of the present invention further includes a phase adjustment unit, configured to perform phase adjustment on the input data according to the obtained phase detection value.

It should be noted that the phase adjustment of the input data according to the phase detection value is a conventional technical means for those skilled in the art, and details are not described here.

Optionally, the apparatus according to the embodiment of the present invention includes an output unit, configured to output data according to the updated frequency of the recovered clock.

Compared with the related art, the technical solution of the present application includes: calculating the amount of input data according to the time error of the input data; calculating the amount of output data by using the frequency of the recovered clock; Data volume difference; update the frequency of the recovered clock according to the obtained first data volume difference. According to the amount of input data and the amount of output data obtained by calculation, the embodiment of the present invention shortens the time for obtaining the recovered clock and reduces the consumption of cache resources; further, the embodiment of the present invention is based on the amount of actual input data and the amount of actual output data. The calculation of the second data volume difference adjusts the input data volume obtained by calculation, thereby improving the precision of the recovered clock obtained by calculation.

In another aspect, an embodiment of the present invention further provides a computer storage medium, where computer-executable instructions are stored in the computer storage medium, and the computer-executable instructions are used to execute the above method for implementing clock recovery.

In another aspect, an embodiment of the present invention further provides a terminal for implementing clock recovery, including: a memory and a processor; wherein,

the processor is configured to execute program instructions in the memory;

Program instructions are read by the processor to do the following:

Calculate the amount of input data according to the time error of the input data;

Calculate the amount of output data using the frequency of the recovered clock;

Comparing the difference between the input data amount and the output data amount obtained by the calculation to obtain the first data amount difference;

The frequency of the recovered clock is updated according to the obtained first data amount difference.

Those of ordinary skill in the art can understand that all or part of the steps in the above method can be completed by instructing relevant hardware (such as a processor) through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk or an optical disk Wait. Optionally, all or part of the steps in the above embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the above-mentioned embodiments may be implemented in the form of hardware, for example, an integrated circuit to implement its corresponding function, or it may be implemented in the form of a software function module, for example, a processor executes a function stored in a memory. program/instruction to achieve its corresponding function. The present invention is not limited to any particular form of combination of hardware and software.

Although the embodiments disclosed in the present invention are as above, the described contents are only the embodiments adopted to facilitate the understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art to which the present invention belongs, without departing from the spirit and scope disclosed by the present invention, can make any modifications and changes in the form and details of the implementation, but the scope of the patent protection of the present invention still needs to be The scope defined by the appended claims shall prevail.

Claims (10)

1. a method for realizing clock recovery, is characterized in that, comprises: Calculate the amount of input data according to the time error of the input data; Calculate the amount of output data using the frequency of the recovered clock; Comparing the difference between the input data amount and the output data amount obtained by the calculation to obtain the first data amount difference; The frequency of updating the recovered clock according to the obtained first data amount difference, The method also includes: Calculate the difference between the actual input data amount and the actual output data amount to obtain the second data amount difference; Adjusting the input data amount obtained by calculation according to the difference value of the second data amount obtained by calculation, The adjusting the calculated input data amount according to the calculated second data amount difference includes: Perform filtering processing on the second data amount difference obtained by calculation; Determine whether the data cache water level is lower than a preset expected value according to the filtered second data volume difference; When it is determined that the data cache water level is lower than the preset expected value, the amount of the input data obtained by calculation is reduced according to the first preset strategy; when it is determined that the data cache water level is higher than the preset expected value, the amount of the input data obtained by calculation is increased according to the second preset strategy. the amount of input data. 2. The method according to claim 1, wherein the calculating the amount of input data according to the time error of the input data comprises: Extract the time error after performing phase detection on the input data, and calculate the phase detection result according to the extracted time error; After filtering the phase detection result obtained by calculation, a corresponding phase detection value is obtained, and the adjustment instruction information for adding or deleting the input data is determined according to the obtained phase detection value; The amount of input data is calculated according to the determined adjustment instruction information. 3. The method according to claim 1, wherein the frequency of updating the recovered clock according to the obtained first data amount difference comprises: performing filtering processing on the first data amount difference obtained by comparison; converting the first data amount difference after the filtering process into an analog voltage amount; The frequency of the recovered clock is updated by the converted analog voltage quantity. 4. The method according to claim 2, wherein the method further comprises: Phase adjustment is performed on the input data according to the obtained phase detection value. 5. The method according to claim 1, wherein the method further comprises: Data output is performed according to the updated frequency of the recovered clock. 6. A device for realizing clock recovery, comprising: a first calculation unit, a second calculation unit, a first difference unit and an update unit; wherein, The first calculation unit is used for: calculating the input data amount according to the time error of the input data, and sending the calculated input data amount to the first difference unit; The second calculation unit is used for: calculating the output data amount using the frequency of the recovered clock, and sending the output data amount obtained by the calculation to the first difference unit; The first difference unit is used for: comparing the difference between the input data amount and the output data amount obtained by the calculation to obtain the first data amount difference; The updating unit is used for: updating the frequency of the recovered clock according to the obtained first data amount difference; The device further includes: a second difference unit and an adjustment unit; wherein, The second difference unit is used to: calculate the difference between the actual input data amount and the actual output data amount, and obtain the second data amount difference; The adjusting unit is configured to: adjust the input data amount obtained by calculation according to the difference value of the second data amount obtained by calculation; The adjustment unit includes a first filter module and an adjustment module; wherein, The first filtering module is used for: filtering the second data amount difference obtained by calculation; The adjustment module is used to: determine whether the data cache water level is lower than a preset expected value according to the second data volume difference after filtering processing; when it is determined that the data cache water level is lower than the preset expected value, reduce the number of times according to the first preset strategy. The amount of input data received by a difference unit; when it is determined that the data buffer water level is higher than a preset expected value, the amount of input data received by the first difference unit is increased according to a second preset strategy. 7. The device according to claim 6, wherein the first calculation unit comprises a phase detection module and a second filter module; wherein, The phase detection module is used to: extract the time error after performing phase detection on the input data, and calculate the phase detection result according to the extracted time error; The second filtering module is used for: filtering the obtained phase detection result to obtain the corresponding phase detection value, and determining the adjustment instruction information for adding and deleting the input data according to the obtained phase detection value; according to the determined adjustment instruction information Calculate the amount of data entered. 8. The device according to claim 6, wherein the update unit comprises a third filter module, a digital-to-analog conversion module and a voltage-controlled oscillation module; wherein, The third filtering module is used for: filtering the first data amount difference obtained by comparison; The digital-to-analog conversion module is used for: converting the difference of the first data amount after the filtering process into an analog voltage amount; The voltage-controlled oscillation module is used for: updating the frequency of the recovered clock through the analog voltage obtained by conversion. 9 . The device according to claim 7 , wherein the device further comprises a phase adjustment unit, configured to perform phase adjustment on the input data according to the obtained phase detection value. 10 . 10 . The apparatus according to claim 6 , wherein the apparatus comprises an output unit for outputting data according to the updated frequency of the recovered clock. 11 .

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