CN102301639B - Method and device for correcting clock jitter - Google Patents

Abstract

Embodiments of the present invention provide a method and device for correcting clock jitter. The method comprises: inputting received data into a buffer according to an Ethernet clock recovered from the received data, the received data including an Ethernet frame and an inter-frame space between adjacent Ethernet frames; reading the received data from the buffer according to a local clock During the process, if the amount of received data buffered in the buffer exceeds the first threshold, the first predetermined amount of invalid data is deducted in the inter-frame interval, or, if the amount of received data buffered in the buffer is lower than the first threshold two thresholds, a second predetermined amount of invalid data is inserted in the inter-frame space to obtain output data output from the buffer, wherein the local clock is synchronized with the Ethernet clock. Based on the above technical solution, the impact of the clock jitter introduced by the Ethernet on the subsequent system processing can be reduced, so that the limitation requirements on the clock jitter can be met, and the clock jitter can be limited within an acceptable range of the index.

Description

Method and device for correcting clock jitter

technical field

The present invention relates to the field of communication, and more particularly, to a method and device for correcting clock jitter in the field of communication.

Background technique

The Common Public Radio Interface (CPRI) defines the interface relationship between the radio equipment controller (Radio Equipment Controller, REC) and the radio equipment (Radio Equipment, RE), and constitutes a remote system of the base station.

Currently there are not only non-packet CPRI transmissions, but also packet CPRI transmissions. In packet CPRI transmission, the CPRI basic frame is encapsulated in an Ethernet frame for transmission, and at this time, the CPRI basic frame will pass through the Ethernet to reach the receiving end.

For example, when REC sends CPRI basic frames to RE through Ethernet, REC generates CPRI basic frames under the action of CPRI master clock, each CPRI basic frame has a length of 260.4ns, and there is no interval. In order to send the CPRI basic frame to the Ethernet, it is necessary to convert the CPRI clock into an Ethernet clock and carry the data of the CPRI basic frame in the Ethernet frame. The frame header distance between adjacent Ethernet frames is expected to be kept at 260.4 ns. However, after the Ethernet frame is output to the Ethernet link, the clocks of the two communication parties are isolated through the forwarding of the Ethernet switch, and a large clock jitter is introduced for the Ethernet frame, so that the frame header distance of the Ethernet frame received by the RE is Large jitter occurs. After the RE converts the Ethernet clock into a CPRI slave clock through clock domain conversion, for the CPRI base frame obtained from the Ethernet frame, the length of each CPRI base frame has a large jitter, and it is difficult to meet the REC master clock required by the CPRI system The jitter between the RE slave clock and the RE slave clock is less than 0.002ppm, making it difficult for the RE slave clock to lock to the REC master clock, which will adversely affect subsequent CPRI basic frame processing.

It can be seen that when the Ethernet frame carrying the CPRI basic frame data is transmitted in the Ethernet, due to the existence of clock jitter, although the Ethernet frame output from the REC has an equal inter-frame interval, the Ethernet frame received by the RE There is jitter in the inter-frame interval, and the spacing of the Ethernet frames becomes haphazard. Due to the jitter of the inter-frame interval between Ethernet frames, the CPRI base frame extracted from the Ethernet frame jitters, and the interval between CPRI base frames varies from time to time, which cannot meet the jitter index required by the CPRI system. The real-time and fast processing of frames has caused great difficulties, and even caused the subsequent collapse of CPRI basic frame processing.

Contents of the invention

Embodiments of the present invention provide a method and device for correcting clock jitter, which can reduce the impact of clock jitter introduced by Ethernet on subsequent system processing, so that the limitation requirements for clock jitter can be met, and the clock jitter can be limited within an acceptable range of indicators .

One aspect of the present invention provides a method for correcting clock jitter, including: inputting the received data into a buffer according to the Ethernet clock recovered from the received data, the received data including the difference between an Ethernet frame and adjacent Ethernet frames In the process of reading the received data from the buffer according to the local clock, if the data volume of the received data buffered in the buffer exceeds the first threshold, the inter-frame interval will be deducted A first predetermined amount of invalid data, or, if the amount of received data buffered in the buffer is lower than a second threshold, inserting a second predetermined amount of invalid data in the inter-frame space, obtained from the buffer Output data output where the local clock is synchronized to the Ethernet clock.

Another aspect of the present invention provides a device for correcting clock jitter, including: a clock recovery module, used to recover the Ethernet clock from received data, the received data includes Ethernet frames and the time between adjacent Ethernet frames The interframe interval; the buffer, used for buffering the received data input according to the Ethernet clock; the local clock, used for providing the clock frequency for reading the received data from the buffer; the jitter correction module, used for During the process of reading the received data from the buffer according to the local clock, if the amount of received data buffered in the buffer exceeds a first threshold, deduct a first predetermined number of invalid data, or, if the amount of received data buffered in the buffer is lower than a second threshold, inserting a second predetermined amount of invalid data in the inter-frame space to obtain output data output from the buffer, Wherein the local clock is synchronized with the Ethernet clock.

Based on the above technical scheme, the received data is input into the buffer according to the Ethernet clock, and output into the buffer according to the local clock synchronized with the Ethernet clock. Interval data is removed and inserted, so that the clock jitter introduced by Ethernet can be corrected, so that the output data output from the buffer has a stable data flow form, which can reduce the impact of clock jitter introduced by Ethernet on subsequent system processing, and can Limit clock jitter to an acceptable range for subsequent system processing.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without any creative work.

FIG. 1 is a schematic diagram of an example of an application scenario.

Fig. 2 is a flowchart of a method for correcting clock jitter according to an embodiment of the present invention.

FIG. 3 is a flowchart of a method for correcting clock jitter by subtracting and inserting invalid data according to an embodiment of the present invention.

Fig. 4 is a flowchart of a method for synchronizing a local clock with an Ethernet clock according to an embodiment of the present invention.

Fig. 5 is an implementation block diagram of a method for synchronizing a local clock with an Ethernet clock according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a specific example of implementing the method shown in FIG. 5 .

Fig. 7 is an implementation block diagram of a specific example of a method for correcting clock jitter according to an embodiment of the present invention.

Fig. 8 is a structural block diagram of an apparatus for correcting clock jitter according to an embodiment of the present invention.

Fig. 9 is a structural block diagram of another device for correcting clock jitter according to an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions of the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

First, a specific scenario of using the method for correcting clock jitter provided by the embodiment of the present invention will be described with reference to FIG. 1 . This specific scene is just an example, and does not constitute any limitation to the protection scope of the present invention.

In the application scenario shown in FIG. 1 , the sending end may be a REC, and the receiving end is an RE at this time; or, the sending end may also be an RE, and the receiving end is an REC at this time. For simplicity of description, the following description will be made by taking the REC as the sending end and the RE as the receiving end as an example.

For example, the REC generates CPRI basic frames according to the CPRI clock, and each CPRI basic frame may be 260.4 ns. In order to transmit the CPRI basic frame through the Ethernet, after clock domain conversion processing and frame conversion processing, valid data in the CPRI basic frame is encapsulated in the Ethernet frame. Among them, the clock domain conversion in REC can convert the CPRI clock into an Ethernet clock, and the frame conversion in REC can extract the valid data from the CPRI base frame by decomposing it, and then carry the valid data in the Ethernet frame to form a Ethernet frame, each Ethernet frame plus the interval between frames is 260.4ns. However, due to the small random jitter A introduced by the clock domain conversion, the inter-frame interval after adding each Ethernet frame is 260.4ns+A.

During the transmission of Ethernet frames via Ethernet, large random jitter B is introduced into the Ethernet frames due to the influence of Ethernet switches. Therefore, the frame header interval of the Ethernet frames received by the RE is 260.4ns+A+B, Exceeded the limit index of 0.002ppm.

If the CPRI base frame is obtained directly from the Ethernet frame received by the RE, the CPRI base frame will have a large clock jitter, which cannot meet the requirements of the CPRI standard to maintain the clock jitter within the range of 0.002ppm. The subsequent processing of the CPRI base frame Will be affected, and even cause the system to crash. Therefore, clock jitter needs to be corrected for the Ethernet frames received by the RE.

The method for correcting clock jitter according to the embodiment of the present invention is used in the clock jitter correction module in the RE, so that the Ethernet frames with large clock jitter received by the RE can be sorted out, so that the distance between the frame headers of adjacent Ethernet frames Maintain at 260.4ns+C, C is random jitter with variance less than 0.002ppm. After clock domain conversion processing and frame conversion processing, the CPRI basic frame with a length of 260.4 ns+D can be output for a system that subsequently processes the CPRI basic frame. The clock domain conversion in the RE can convert the Ethernet clock into a CPRI clock, and the frame conversion in the RE can extract the valid data of the CPRI basic frame from the Ethernet frame, and then compose the valid data into a CPRI basic frame. Since the jitter newly brought by the clock domain conversion process is very small, the jitter D of the CPRI base frame obtained in the RE can still be maintained within a random jitter of less than 0.002ppm. Therefore, for the CPRI basic frame sent by the REC and the CPRI basic frame received by the RE, the clock jitter can be controlled within 0.002ppm, thereby meeting the clock jitter index requirement of the CPRI standard and facilitating subsequent system processing. In addition, since the Ethernet clock and the CPRI clock used in the RE are generated based on the local clock, if the local clock is a high-stable clock, the Ethernet clock and the CPRI clock are both high-stable clocks.

Next, a method for correcting clock jitter according to an embodiment of the present invention will be described in detail with reference to FIG. 2 .

As shown in Figure 2, the method in Figure 2 includes:

In S210, the received data is input into the buffer according to the Ethernet clock recovered from the received data, and the received data includes an Ethernet frame and an inter-frame space between adjacent Ethernet frames.

As an example, the received data may be the aforementioned Ethernet frame transmitted through the high-speed Ethernet; and the Ethernet frame may be used to carry CPRI frame data.

In S220, during the process of reading the received data from the buffer according to the local clock, if the data volume of the received data buffered in the buffer exceeds the first threshold, deduct the first predetermined amount of invalid data in the inter-frame interval, if If the amount of received data buffered in the buffer is lower than the second threshold, a second predetermined amount of invalid data is inserted into the inter-frame space to obtain output data output from the buffer, wherein the local clock is synchronized with the Ethernet clock.

Wherein, for a buffer that buffers received data, the write clock of the buffer is an Ethernet clock, which can be recovered from the received data, and the read clock of the buffer is a local clock, and the local clock needs to be synchronized with the Ethernet clock. The Ethernet domain is isolated from the local clock domain by buffers. The buffer may be a storage space opened up in the memory, which is used to buffer the received data, and helps to correct the clock jitter during the input and output of the received data.

The received data buffered by the buffer includes the Ethernet frame and the inter-frame space. Data under other protocols can be carried in the Ethernet frame. For example, the data under the CPRI protocol can be carried in the Ethernet frame, and the CPRI frame data is transmitted through the Ethernet frame.

According to an embodiment of the present invention, the local clock may be a high-stable clock. In this way, the local clock has better stability, which is beneficial to subsequent system processing.

Correction of clock jitter can be realized by performing more deductions and less supplements on invalid data in the inter-frame interval in S220.

In the following, a flowchart of a method for correcting clock jitter by subtracting and inserting data according to an embodiment of the present invention will be described in detail with reference to FIG. 3 .

The received data is continuously input into the buffer under the effect of the recovered Ethernet clock, and the received data is continuously read from the buffer according to the local clock. In order to correct the clock jitter in the process of reading the received data from the buffer, the invalid data in the inter-frame interval can be processed with more deductions and less supplements, as follows.

In S310, the data volume of the received data buffered in the buffer is counted.

In S320, it is judged whether the amount of received data buffered in the buffer is greater than a first threshold.

The first threshold may be the sum of the fixed value M and the predetermined number of samples Th1 included in the Ethernet frame. Th1 may be a predetermined number of samples included in an Ethernet frame of known length ideally. For example, in a CPRI system, Th1 may be the frequency of an Ethernet clock multiplied by an Ethernet frame encapsulated with CPRI data. The fixed value M may be equal to Th1, and in this case the first threshold is 2Th1. When the data cached in the cache exceeds the first threshold, it means that the speed of writing the cache is greater than the speed of reading the cache, and it is necessary to subtract invalid data from the inter-frame interval, so proceed to S330; when the data cached in the cache When the first threshold is not exceeded, go to S340. Of course, the first threshold may also be other values. It only needs that the size of the buffer is not lower than the first threshold.

In S330, when the amount of data in the buffer is greater than the first threshold, deduct invalid data in the inter-frame space, and the deducted number is the first predetermined number.

The inter-frame space data can have a fixed format. For example, the inter-frame space data can start with a Terminate symbol, followed by an idle (Idle) symbol, so the receiving end can easily determine which part of the received data belongs to the inter-frame space. interval.

The deducted invalid data may be an idle character, which does not affect the basic structure of the inter-frame space. When deducting invalid data each time, only one invalid data may be deducted, that is, the invalid data read within one local clock cycle is deducted. In this way, the effect of smoothly deducting invalid data can be achieved, and the extra deviation introduced by too many deducted numbers can be avoided.

In S340, it is judged whether the amount of received data buffered in the buffer is lower than a second threshold.

The second threshold may be the difference between the fixed value M and the predetermined number of samples Th1 included in the Ethernet frame. The meaning of Th1 is as described above. The fixed value M may be equal to Th1, and the second threshold is 0 at this time. When the data cached in the buffer is lower than the first threshold, it means that the speed of writing the buffer is lower than the speed of reading the buffer, and there is no data buffered in the buffer, and it is necessary to insert invalid data into the inter-frame interval, so proceed to S350: When the data cached in the buffer is not lower than the first threshold, proceed to S310. Certainly, the second threshold may also be other values.

For example, assume that the first threshold is the sum of M and TT, the second threshold is the difference between M and TT, and assume that TT is an integer multiple of the maximum Ethernet frame length. If M is larger and TT is larger, the fixed delay will be greater. Considering that the delay is as small as possible, TT can be set to the length of an Ethernet frame. Since the second threshold cannot be a negative number, and considering that storing M data means a fixed delay of M clock cycles, it is hoped that M should be as small as possible, and M can be set to TT. Therefore, both M and TT can be set to the length of an Ethernet frame.

In S350, when the amount of data in the buffer is smaller than the second threshold, insert invalid data into the inter-frame interval, and the inserted number is a second predetermined number.

The inserted invalid data may be an idle symbol, which does not affect the basic structure of the inter-frame space. Each time invalid data is inserted, only one invalid data may be inserted, that is, one invalid data is inserted within one local clock cycle. In this way, the effect of smoothly inserting invalid data can be achieved, and additional deviation can be avoided when the number of inserted data is too large.

In addition, the local clock needs to be synchronized with the Ethernet clock in the process of over-substituting and under-compensating the invalid data in the inter-frame interval. The manner of synchronizing the local clock and the Ethernet clock may adopt the existing manner of synchronizing two clocks, or may adopt the synchronization method described in conjunction with FIG. 4 .

In the method for synchronizing the local clock with the Ethernet clock shown in Figure 4, the output data output from the buffer is used. Since more deductions and less supplements are carried out in the process of reading data from the buffer, the slave buffer The output data of the output is the received data after more deductions and less supplements.

In the method shown in FIG. 4, the local clock is synchronized with the Ethernet clock based on the output data output from the buffer.

In S410, frame synchronization is performed on the output data, the number of Ethernet frames included in the output data is determined, and a first count value is obtained.

Since the Ethernet frame has a fixed frame header format, it is possible to determine how many Ethernet frames are included in the output data by performing frame synchronization on the output data. The initial value of the counter for recording the number of Ethernet frames is 0, and the count of the counter is increased by 1 every time an Ethernet frame header is synchronized. In this document, the count value recorded in the counter is referred to as the first count value, denoted by sum1.

In S420, based on the local clock, the number of Ethernet frames is counted according to a predetermined time length between frame headers of adjacent Ethernet frames, to obtain a second count value.

Since the time length between the frame headers of adjacent Ethernet frames can be preset, the local clock can be used as the criterion. When the predetermined time length expires, it is considered that an Ethernet frame has passed. For example, in the application scenario shown in FIG. 1 , the predetermined time length between headers of adjacent Ethernet frames is 260.4 ns, and every time the local clock counts 260.4 ns, it is considered that an Ethernet frame has passed.

In the case of determining the number of Ethernet frames by counting the predetermined time length, the initial value of the counter for recording the number of Ethernet frames is also 0, and whenever the predetermined time length is counted by the local clock, the count of the counter is added. 1. Herein, the count value recorded in the counter is called the second count value, denoted by sum2.

In S430, based on the first count value and the second count value, the local clock is adjusted to be synchronized with the Ethernet clock.

According to the embodiment of the present invention, a fuzzy control algorithm can be used to determine the adjustment amount of the local clock, and the frequency of the local clock is adjusted according to the adjustment amount to gradually converge to make the local clock and the Ethernet clock synchronized. The specific adjustment process can be combined with the description made with reference to FIG. 6 . In the example of adjusting the local clock shown in Figure 6, based on the first count value and the second count value, a fuzzy control algorithm is used to obtain a digital signal; the digital signal is converted into an analog signal and then input into a phase-locked loop (Phase- LockedLoop, PLL) includes an oven-controlled oscillator, where the phase-locked loop generates a local clock based on a local crystal.

next. First, a block diagram of a method for synchronizing a local clock with an Ethernet clock is described with reference to FIG. 5 , and then how to adjust the local clock is described through a specific example in FIG. 6 .

In Fig. 5, the initial value of the first count value sum1 of counter 1 and the second count value sum2 of counter 2 is 0, and both start counting at the same time, for example, from the beginning of receiving the first Ethernet frame, counter 1 and Counter 2 counts simultaneously.

The output data Din outputted from the buffer after deducting more and complementing less is input to the frame synchronization module. Frame synchronization is performed on the Ethernet frame in the frame synchronization module, and the first count value sum1 of the counter 1 is increased by 1 every time an Ethernet frame is synchronized.

The second count value sum2 of the counter 2 is timed under the drive of the local clock, and the second count value sum2 is incremented by 1 every time the predetermined time length between headers of adjacent Ethernet frames is counted. For example, in the application scenario shown in FIG. 1 , the counter 2 is driven by the local clock and takes the CPRI basic frame period as a unit, and adds 1 to the second count value sum2 every time the CPRI basic frame period is completed.

Compare sum1 and sum2, input the comparison result to the fuzzy control system, and adjust the frequency of the local clock through the output generated by the fuzzy control system. The fuzzy control system is a control system using fuzzy control algorithm. The larger the input, the greater the correction, so as to realize the rapid convergence of the output.

A specific example of synchronizing the local clock with the Ethernet clock is shown in FIG. 6 .

As described with reference to FIG. 5 , the first count value sum1 is obtained by frame-synchronizing the output data Din output from the buffer, and the second count value sum2 is obtained by counting a predetermined time length based on the local clock.

Calculate the difference between sum1 and sum2 at a fixed calculation time period to obtain Xn, where n represents the nth calculation time period. In addition, Xn is cached in two levels, and the relative difference between the counter difference in this cycle and the counter difference in the previous cycle is calculated, that is, ΔX=Xn−Xn−1. If the Ethernet clock is higher than the local clock, ΔX increases positively; if the Ethernet clock is lower than the local clock, ΔX increases negatively.

In each calculation time period, ΔX and Xn are input into the fuzzy control system under the enabling of the timer. The fuzzy control system performs table look-up calculation according to the values of Xn and ΔX, and obtains the adjustment value L used to adjust the local clock frequency, and the adjustment value L is a digital signal. The adjustment value L can be obtained by looking up the fuzzy control table shown in Table 1.

Table 1

If the obtained adjustment value L is 0, it indicates that the frequency of the local clock and the Ethernet clock have been synchronized. If the adjustment value L is not 0, the digital signal needs to be sent to a digital-to-analog converter (Digital-to-Analog Converter, DAC). The DAC converts the digital signal into an analog signal, and inputs the analog signal to the Oven Controlled Crystal Oscillator (OCXO) contained in the phase-locked loop that generates the local clock based on the local crystal oscillator, so that the local clock generated by the phase-locked loop can be adjusted. frequency.

According to the method for correcting clock jitter provided by the embodiment of the present invention, the received data is input into the buffer according to the Ethernet clock, and the buffer is output according to the local clock synchronized with the Ethernet clock, and the relationship between the amount of data buffered in the buffer and the threshold is used , to remove and insert the inter-frame interval data in the received data, so that the clock jitter introduced by Ethernet can be corrected, so that the output data output from the buffer has a stable data flow form, thereby reducing the clock jitter introduced by Ethernet The impact on subsequent system processing can limit the clock jitter within the acceptable range of subsequent system processing. In addition, because the clock jitter in the output data output from the buffer can be removed, a more stable data flow can be obtained, which is beneficial to subsequent real-time processing of the data flow and reduces storage space overhead required for subsequent processing.

Next, an implementation block diagram of a specific example of a method for correcting clock jitter according to an embodiment of the present invention will be described with reference to FIG. 7 . In this specific example, not only the stability adjustment part for correcting the clock jitter is included, but also the accuracy adjustment part for synchronizing the local clock with the Ethernet clock is included.

The specific example shown in FIG. 7 may be located in the clock jitter correction module at the receiving end in the application scenario shown in FIG. 1 . In the example shown in Figure 7, take REC as the transmitter and RE as the receiver, and both REC and RE use a clock source with a frequency stability better than the CPRI standard, that is, both REC and RE can use a high-stable clock .

The RE may include a 10GE PHY unit, a PLL, a XAUI (10GigabitAttachmentUnit Interface, 10 Gigabit Ethernet connection unit interface) unit, a buffer, a local clock, a stability adjustment part, and an accuracy adjustment part.

The 10GE PHY unit is the physical layer interface of 10GE Ethernet. In addition to providing the data signal, it also provides the clock signal recovered from the network card. The recovered clock signal is the Ethernet clock, and the clock is used as the clock reference for the XAUI unit to read data. and the write clock for the buffer.

PLL is a hardware phase-locked loop. By referring to the local clock, it adjusts the clock recovered from the 10GE PHY unit to filter out high-frequency components in the recovered Ethernet clock.

The XAUI unit is an extension of the XGMII (10Gigabit Media Independent Interface, media-independent 10 Gigabit interface) that works in the Ethernet model to connect the physical layer and the media access control layer. Here, XAUI requires both a clock signal from the PLL and a data signal from the 10GE PHY unit.

The buffer is used to isolate the Ethernet clock domain and the local clock domain, which can ensure that no overflow or underflow occurs when the received data traverses different clock domains. At the same time, the register can be used as a data access container for more deduction and less replenishment operations, which is beneficial to realize frequency stability adjustment.

The frequency stability of the local clock itself is better than the specification requirement. Both REC and RE can use a high-stable clock as the local clock to avoid introducing large clock jitter.

For the operation of the stability adjustment part, reference may be made to the description in conjunction with FIG. 3 . When performing stability adjustment, that is, correcting clock jitter, if the amount of data buffered in the buffer exceeds the first threshold, invalid data is deducted from the inter-frame interval; if the amount of data buffered in the buffer is lower than the second threshold, then in Invalid data is inserted in the interframe space.

The accuracy adjustment part may include a counter counting module and a fuzzy control system, and the operation of the accuracy adjustment part may refer to the description in conjunction with FIG. 5 and FIG. 6 . When performing accuracy adjustment, that is, synchronizing the local clock and the Ethernet clock, the first count value and the second count value can be obtained by counting the two counters respectively, the first count value is obtained through frame synchronization, and the second count value is obtained through the Timed by the local clock. Use the fuzzy control algorithm to obtain the frequency adjustment signal for the two count values, quantize the frequency adjustment signal into a digital signal and send it to the DAC (as shown in Figure 6), and then input the analog signal output by the DAC to the frequency adjustment of the OCXO of the PLL that generates the local clock port to adjust the local clock.

The stability adjustment part and the accuracy adjustment part operate alternately, that is, the local clock after the accuracy adjustment is used as the read clock of the buffer to continue reading the received data from the buffer, and in the process of reading, more deductions and less supplements are made. The clock jitter introduced by the Ethernet is corrected, and the data after more deductions and less complements is used as the input data for accuracy adjustment to continue to help the accuracy adjustment of the local clock.

In addition, the output data output from the buffer is sent to the subsequent processing system for processing. For example, in the application scenario in Figure 1, the Ethernet frame output from the buffer has a stable inter-frame interval due to clock jitter correction, and after decapsulation and other operations, a stable CPRI base frame can be obtained for subsequent processing. Since the subsequent processing of the Ethernet frame output by the buffer is the same as that of the prior art, it is not repeated here for simplicity.

Above, the method for correcting clock jitter according to the embodiment of the present invention has been described. In the following, an apparatus for correcting clock jitter according to an embodiment of the present invention will be described with reference to FIG. 8 and FIG. 9 .

Fig. 8 is a structural block diagram of an apparatus 800 for correcting clock jitter according to an embodiment of the present invention.

The apparatus 800 includes a clock recovery module 810 , a buffer 820 , a local clock 830 and a jitter correction module 840 . The apparatus 800 may be located in the receiving end device, and the apparatus 800 receives data from the Ethernet, and sends the Ethernet frame output from the buffer to a subsequent processing module such as decapsulation. The clock recovery module 810 can be a network card, and can recover a clock from received data. The jitter correction module 840 may be a processor, which performs more subtraction and less complement operations on the output data of the buffer.

Wherein, the clock recovery module 810 can be used to recover the Ethernet clock from the received data, and the received data includes an Ethernet frame and an inter-frame space between adjacent Ethernet frames. Buffer 820 may be used to buffer received data input according to the Ethernet clock. The local clock 830 may be used to provide a clock frequency for reading received data from the buffer 820 . The jitter correction module 840 can be used to deduct the first predetermined amount of data in the inter-frame interval if the data amount of the received data buffered in the buffer 820 exceeds the first threshold during the process of reading the received data from the buffer 820 according to the local clock. or, if the amount of received data buffered in the buffer 820 is lower than the second threshold, a second predetermined amount of invalid data is inserted into the inter-frame space to obtain the output data output from the buffer 820, wherein The local clock is synchronized with the Ethernet clock.

For the above and other operations and/or functions of the clock recovery module 810, the buffer 820, the local clock 830 and the jitter correction module 840, reference may be made to the corresponding description in the method of FIG.

According to the device for correcting clock jitter provided by the embodiment of the present invention, by inputting the received data into the buffer according to the Ethernet clock and outputting the buffer according to the local clock synchronized with the Ethernet clock, the data buffered in the buffer can be used The relationship between the amount of data and the threshold, remove and insert the inter-frame interval data in the received data, so that the clock jitter introduced by Ethernet can be corrected, so that the output data output from the buffer has a stable data flow form, which can reduce The impact of the clock jitter introduced by the Ethernet on the subsequent system processing, so that the clock jitter can be limited within the acceptable range of the subsequent system processing.

Fig. 9 is a structural block diagram of an apparatus 900 for correcting clock jitter according to an embodiment of the present invention.

The clock recovery module 910 , buffer 920 , local clock 930 and jitter correction module 940 of the device 900 are basically the same as the clock recovery module 810 , buffer 820 , local clock 830 and jitter correction module 840 of the device 800 .

According to an embodiment of the present invention, the device 900 may further include a synchronization module 950 . The synchronization module 950 can be used to synchronize the local clock with the Ethernet clock based on the output data.

For example, the synchronization module 950 may include a first counter unit 952 , a second counter unit 954 and an adjustment unit 956 . The first counter unit 952 can be used to perform frame synchronization on the output data, determine the number of Ethernet frames included in the output data, and obtain a first count value. The second counter unit 952 may be configured to count the number of Ethernet frames according to a predetermined time length between frame headers of adjacent Ethernet frames based on a local clock, to obtain a second count value. The adjustment unit 956 is configured to adjust the local clock to be synchronized with the Ethernet clock based on the first count value and the second count value.

According to an embodiment of the present invention, the adjustment unit 956 may include a calculation subunit 956-1, a digital-to-analog converter 956-2, and a phase-locked loop 956-3. The calculation subunit 956-1 can be used to obtain a digital signal based on the first count value and the second count value by using a fuzzy control algorithm. The digital-to-analog converter 956-2 can be used to convert the digital signal to an analog signal, and input the analog signal to the oven-controlled oscillator included in the phase-locked loop. A phase locked loop 956-3 may be used to generate a local clock based on a local crystal.

According to an embodiment of the present invention, the local clock 930 may be a high-stable clock.

According to an embodiment of the present invention, the first threshold may be a sum of a fixed value and a predetermined number of samples included in an Ethernet frame, and the second threshold may be a difference between a fixed value and a predetermined number of samples included in an Ethernet frame.

According to an embodiment of the present invention, the first predetermined quantity is 1, and the second predetermined quantity is 1.

The above and other operations and/or functions of the first counter unit 952, the second counter unit 954, the adjustment unit 956, the calculation subunit 956-1, the digital-to-analog converter 956-2 and the phase-locked loop 956-3 can refer to the above-mentioned figures 2 to the corresponding descriptions in FIG. 6 , in order to avoid repetition, they are not repeated here.

According to the device for correcting clock jitter provided by the embodiment of the present invention, the clock jitter introduced by Ethernet can be effectively corrected by deducting more and less supplementing the invalid data in the inter-frame interval, so that a more stable data flow can be obtained, which is beneficial to Subsequent real-time processing of the data stream reduces the storage space overhead required for subsequent processing.

Those skilled in the art can realize that, in combination with the various method steps and units described in the embodiments disclosed herein, they can be realized by electronic hardware, computer software, or a combination of the two. Alternatively, in the above description, the steps and components of each embodiment have been generally described in terms of functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may implement the described functionality using different methods for each particular application, but such implementation should not be considered as exceeding the scope of the present invention.

The method steps described in connection with the embodiments disclosed herein may be implemented by hardware, software programs executed by a processor, or a combination of both. The software program may reside in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or technical field Any other known storage medium.

Although some embodiments of the present invention have been shown and described, it should be understood by those skilled in the art that various modifications can be made to these embodiments without departing from the principles and spirit of the invention, and such modifications shall fall within into the scope of the present invention.

Claims (10)

1. A method for correcting clock jitter, comprising: inputting the received data into a buffer according to the Ethernet clock recovered from the received data, the received data including an Ethernet frame and an interframe space between adjacent Ethernet frames; In the process of reading the received data from the buffer according to the local clock, if the data amount of the received data buffered in the buffer exceeds the first threshold, deducting a first predetermined number of invalid values in the inter-frame interval data, or, if the amount of received data buffered in the buffer is lower than a second threshold, inserting a second predetermined amount of invalid data in the inter-frame space to obtain output data output from the buffer, wherein the local clock is synchronized with the Ethernet clock; Wherein, synchronizing the local clock with the Ethernet clock includes: synchronizing the local clock with the Ethernet clock based on the output data; The synchronizing the local clock with the Ethernet clock based on the output data includes: Carrying out frame synchronization to the output data, determining the number of Ethernet frames contained in the output data, and obtaining a first count value; Based on the local clock, count the number of Ethernet frames according to the predetermined time length between adjacent Ethernet frame headers to obtain a second count value; The local clock is adjusted to be synchronized with the Ethernet clock based on the first count value and the second count value. 2. The method according to claim 1, wherein the adjusting the local clock based on the first count value and the second count value comprises: Obtaining a digital signal by using a fuzzy control algorithm based on the first count value and the second count value; After the digital signal is converted into an analog signal, it is input to a constant temperature oscillator included in a phase-locked loop, wherein the phase-locked loop generates the local clock based on a local crystal oscillator. 3. The method according to claim 1 or 2, wherein the first threshold is the sum of a fixed value and the number of predetermined samples contained in an Ethernet frame, and the second threshold is the sum of the fixed value and the The difference between the predetermined number of samples contained in an Ethernet frame. 4. The method according to claim 3, wherein the fixed value is a predetermined number of samples included in the Ethernet frame. 5. The method according to claim 1 or 2, wherein the first predetermined number is one, and the second predetermined number is one. 6. A device for correcting clock jitter, comprising: A clock recovery module, configured to recover an Ethernet clock from received data, the received data including an Ethernet frame and an interframe space between adjacent Ethernet frames; a buffer for buffering received data input according to the Ethernet clock; a local clock for providing a clock frequency for reading said received data from said buffer; A jitter correction module, configured to, during the process of reading the received data from the buffer according to the local clock, if the data amount of the received data buffered in the buffer exceeds a first threshold, at the inter-frame interval Deducting a first predetermined amount of invalid data, or, if the amount of received data buffered in the buffer is lower than a second threshold, inserting a second predetermined amount of invalid data in the inter-frame space, obtained from the output data output by a buffer, wherein the local clock is synchronized with the Ethernet clock; It also includes: a synchronization module, configured to synchronize the local clock with the Ethernet clock based on the output data; Wherein, the synchronization module includes: The first counter unit is configured to perform frame synchronization on the output data, determine the number of Ethernet frames contained in the output data, and obtain a first count value; The second counter unit is used to count the number of Ethernet frames according to the predetermined time length between the frame headers of adjacent Ethernet frames based on the local clock, to obtain a second count value; An adjustment unit, configured to adjust the local clock to be synchronized with the Ethernet clock based on the first count value and the second count value. 7. The device according to claim 6, wherein the adjustment unit comprises: A calculation subunit, configured to obtain a digital signal by using a fuzzy control algorithm based on the first count value and the second count value; A digital-to-analog converter for converting the digital signal into an analog signal, and inputting the analog signal into the constant temperature oscillator included in the phase-locked loop; The phase-locked loop is configured to generate the local clock based on a local crystal oscillator. 8. The device according to claim 6 or 7, wherein the first threshold is the sum of a fixed value and a predetermined number of samples contained in an Ethernet frame, and the second threshold is the sum of the fixed value and the The difference between the predetermined number of samples contained in an Ethernet frame. 9. The device according to claim 8, wherein the fixed value is a predetermined number of samples included in the Ethernet frame. 10. The device according to claim 6 or 7, wherein the first predetermined number is one, and the second predetermined number is one.