CN109412740B - Method and device for processing delay jitter - Google Patents

Abstract

A method and device for processing delay jitter, comprising: acquiring processing rate information of data; and processing data according to the acquired processing rate information. The embodiment of the present invention reduces delay jitter and improves data transmission quality.

Description

A method and device for processing delay jitter

technical field

This article relates to, but is not limited to, optical communication technology, especially a method and device for processing delay jitter.

Background technique

In the development of transmission technology, optical fiber is an indispensable medium. In order to transmit the most abundant information with the least amount of optical fiber, the development of optical transmission has gone through the following stages: space division multiplexing (SDM), time division multiplexing (TDM) and wavelength division multiplexing (WDM) .

At present, the cable transmission is still dominated by wavelength division multiplexing; commercial wavelength division transmission has gradually evolved from 40 gigabits (G) to 100G and 400G. In addition, the data transmission distance is also constantly expanding; the rapid growth of data services also puts forward higher requirements for the transmission network: large capacity, low cost, fast and flexible service scheduling, strong expansion capability and high reliability.

Delay jitter is an important aspect that affects the quality of signal transmission in optical communication systems. With the increase of transmission rate and transmission distance, the impact of delay jitter on optical communication quality can not be ignored more and more. In the optical transport network (OTN) system, the delay jitter in the sending link and the receiving link will cause the transmission damage of the client signal, which will affect the reliability and performance of the entire system. The current mainstream DSP chips in the industry have no special effect on this. processing. In 100G/400G services, 100G/400G pass-through services and 100G/400G loopback services, the reliability and performance of the system will be affected, and services with special requirements for delay, such as 100G/400G services, will not be able to meet the Reliability requirements affect the application of 100G/400G DSP chips in the market.

SUMMARY OF THE INVENTION

The following is an overview of the topics detailed in this article. This summary is not intended to limit the scope of protection of the claims.

Embodiments of the present invention provide a method and device for processing delay jitter, which can reduce delay jitter.

An embodiment of the present invention provides a method for processing delay jitter, including:

Obtain data processing rate information;

Data is processed according to the acquired processing rate information.

Optionally, the data processing according to the acquired processing rate information includes:

When the processing rate information includes the write clock frequency and the write clock frequency, the data in the first FIFO is read and written according to the read clock frequency and the write clock frequency;

When the processing rate information includes the traffic information of the link ingress and the link egress, the processing of inserting the data to be sent into a preset data frame is performed according to the traffic information.

Optionally, the reading and writing data in the first FIFO according to the read clock frequency and the write clock frequency include:

Calculate a duty cycle according to the read clock frequency and the write clock frequency;

Whether to read or write data in the first FIFO is determined according to the calculated duty cycle and the preset FIFO buffer water level threshold, so as to control the delay fluctuation within the preset interval according to the FIFO buffer water level.

Optionally, the reading and writing data in the first FIFO according to the read clock frequency and the write clock frequency include:

An enable signal for whether to read and write data in the first FIFO is generated by a preset state machine, so as to read and write data in the first FIFO according to the generated enable signal.

Optionally, the process of inserting the data to be sent into the preset data frame includes:

Calculate the number of interval frames

According to the calculation to obtain the number of interval frames X, insert the preset data frame;

为向上取整。Wherein, the V_ge is the traffic value of the link ingress in the optical Ethernet GE mode; the gain_ge is the data gain after the link ingress is processed by the optical conversion unit OTU; the V_out is the traffic value of the link ingress in the mode; the data gain of the forward error correction FEC decoding device of the gain_gfec;

to round up.

Optionally, the inserting of the preset data frame according to the calculation to obtain the number of interval frames X includes:

Insert the preset data frame after the interval frame number X TPC frames; or,

When the water level of the second FIFO composed of random access memory RAM is lower than the preset storage water level threshold, the preset data frame is inserted after the interval frame number X TPC frames; when the water level of the second FIFO is greater than the preset storage water level When the water level threshold is set, the preset data frame is inserted after adding 1 TPC frame to the number of interval frames X.

Optionally, the calculation interval frame number X includes:

The number X of the interval frames is calculated according to a preset period.

Optionally, the preset data frame includes:

an empty frame of a data frame of a pseudo-random binary sequence PRBS comprising a first preset length of an empty frame identification code and a second preset length; or,

A data frame with the same frame length as the TPC frame in a preset format;

Wherein, the sum of the first preset length and the second preset length is the same as the TPC frame length.

Optionally, before the data to be sent is inserted into a preset data frame, the method further includes:

Cross-clock domain processing is performed on the data to be sent.

On the other hand, an embodiment of the present invention further provides an apparatus for processing delay jitter, including: an acquisition unit and a processing unit; wherein,

The obtaining unit is used for: obtaining the processing rate information of the data;

The processing unit is used for: processing data according to the acquired processing rate information.

Optionally, the processing unit includes a read-write control module and a frame insertion module; wherein,

The read-write control module is used for: when the processing rate information obtained by the obtaining unit includes the write clock frequency and the write clock frequency, read and write the data in the first FIFO according to the read clock frequency and the write clock frequency;

The frame inserting module is configured to: when the processing rate information obtained by the obtaining unit includes the traffic information of the link ingress and the link egress, perform processing of inserting the data to be sent out into a preset data frame according to the traffic information.

Optionally, the read-write control module is specifically used for:

Calculate a duty cycle according to the read clock frequency and the write clock frequency;

According to the calculated duty cycle and the preset FIFO buffer water level threshold, it is determined whether to read or write the data in the first FIFO, so as to control the delay fluctuation within the preset interval according to the FIFO buffer water level.

Optionally, the read-write control module is specifically configured to: generate an enable signal for whether to read and write data in the first FIFO by using a preset state machine, so as to control the data in the first FIFO according to the generated enable signal. Data is read and written.

Optionally, the frame insertion module is specifically used for:

Calculate the number of interval frames

According to the calculation to obtain the number of interval frames X, insert the preset data frame;

为向上取整。Wherein, the V_ge is the traffic value of the link ingress in the optical Ethernet GE mode; the gain_ge is the data gain after the link ingress is processed by the optical conversion unit OTU; the V_out is the traffic value of the link ingress in the mode; the data gain of the forward error correction FEC decoding device of the gain_gfec;

to round up.

Optionally, the frame insertion module is used to obtain the interval frame number X according to the calculation to perform the insertion of the preset data frame, including:

Insert the preset data frame after the interval frame number X TPC frames; or,

When the water level of the second FIFO composed of random access memory RAM is lower than the preset storage water level threshold, the preset data frame is inserted after the interval frame number X TPC frames; when the water level of the second FIFO is greater than the preset storage water level When the water level threshold is set, the preset data frame is inserted after adding 1 TPC frame to the number of interval frames X.

Optionally, the frame insertion module is used to calculate the number X of interval frames including:

The number X of the interval frames is calculated according to a preset period.

Optionally, the preset data frame includes:

an empty frame of a data frame of a pseudo-random binary sequence PRBS comprising a first preset length of an empty frame identification code and a second preset length; or,

A data frame with the same frame length as the TPC frame in a preset format;

Wherein, the sum of the first preset length and the second preset length is the same as the TPC frame length.

Optionally, the apparatus further includes a cross-clock domain processing unit configured to perform cross-clock domain processing on the data to be sent before inserting the data into a preset data frame.

In another aspect, an embodiment of the present invention further provides a computer storage medium, where computer-executable instructions are stored in the computer storage medium, and the computer-executable instructions are used to execute the above method for processing delay jitter.

In another aspect, an embodiment of the present invention further provides a terminal, including: a memory and a processor; wherein,

the processor is configured to execute program instructions in the memory;

Program instructions are read by the processor to do the following:

Obtain data processing rate information;

Data is processed according to the acquired processing rate information.

Compared with the related art, the technical solution of the present application includes: acquiring processing rate information of data; and processing data according to the acquired processing rate information. The embodiments of the present invention reduce delay jitter and improve data transmission quality.

Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the description, claims and drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the specification. They are used to explain the technical solutions of the present invention together with the embodiments of the present application, and do not limit the technical solutions of the present invention.

1 is a flowchart of a method for processing delay jitter according to an embodiment of the present invention;

2 is a structural block diagram of an apparatus for processing delay jitter according to an embodiment of the present invention;

3 is a schematic diagram of a state machine of an application example of the present invention;

Figure 4 is a schematic diagram of the connection of the state machine in the 100G DSP for this application example;

FIG. 5 is a schematic diagram of the composition structure of an empty frame according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, the embodiments in the present application and the features in the embodiments may be arbitrarily combined with each other if there is no conflict.

The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.

FIG. 1 is a flowchart of a method for processing delay jitter according to an embodiment of the present invention. As shown in FIG. 1 , the method includes:

Step 100, obtaining processing rate information of the data;

Optionally, the processing rate information in this embodiment of the present invention includes: write clock frequency, write clock frequency, traffic information of link ingress and link egress, and the like.

Step 101: Perform data processing according to the acquired processing rate information.

Optionally, the processing of data according to the acquired processing rate information in this embodiment of the present invention includes:

When the processing rate information includes the write clock frequency and the write clock frequency, read and write data in the first FIFO according to the read clock frequency and the write clock frequency;

When the processing rate information includes the traffic information of the link ingress and the link egress, the processing of inserting the data to be sent into the preset data frame is performed according to the traffic information.

Optionally, in this embodiment of the present invention, reading and writing data in the first FIFO according to the read clock frequency and the write clock frequency includes:

Calculate a duty cycle according to the read clock frequency and the write clock frequency;

Whether to read or write data in the first FIFO is determined according to the calculated duty cycle and the preset FIFO buffer water level threshold, so as to control the delay fluctuation within the preset interval according to the FIFO buffer water level.

It should be noted that in this embodiment of the present invention, the FIFO buffer water level is determined by the FIFO buffer water level threshold. According to the FIFO buffer water level, those skilled in the art can determine whether to read or write the data in the FIFO, so as to control the delay within a preset interval. Internal volatility

Optionally, in this embodiment of the present invention, reading and writing data in the first FIFO according to the read clock frequency and the write clock frequency includes:

An enable signal for whether to read and write data in the first FIFO is generated by a preset state machine, so as to read and write data in the first FIFO according to the generated enable signal.

Optionally, the process of inserting the data to be sent into the preset data frame includes:

Calculate the number of interval frames

According to the calculation to obtain the number of interval frames X, insert the preset data frame;

为向上取整。Wherein, the V_ge is the traffic value of the link ingress in the optical Ethernet GE mode; the gain_ge is the data gain after the link ingress is processed by the optical conversion unit OTU; the V_out is the traffic value of the link ingress in the mode; the data gain of the forward error correction FEC decoding device of the gain_gfec;

to round up.

Optionally, the embodiment of the present invention performs the insertion of the preset data frame according to the number X of interval frames obtained by calculation, including:

Insert the preset data frame after the interval frame number X TPC frames; or,

When the water level of the second FIFO composed of random access memory (RAM) is lower than the preset storage water level threshold, the preset data frame is inserted after the number of interval frames X TPC frames; when the water level of the second FIFO is greater than the preset storage water level threshold When the storage water level threshold is set, the preset data frame is inserted after the interval frame number X plus 1 TPC frame.

Optionally, calculating the number X of interval frames in this embodiment of the present invention includes:

The number X of the interval frames is calculated according to a preset period.

Optionally, the preset data frame in this embodiment of the present invention includes:

an empty frame of a data frame of a pseudo-random binary sequence PRBS comprising a first preset length of an empty frame identification code and a second preset length; or,

A data frame with the same frame length as the TPC frame in a preset format;

Wherein, the sum of the first preset length and the second preset length is the same as the TPC frame length.

Optionally, before performing the process of inserting the data to be sent into the preset data frame, the method according to the embodiment of the present invention further includes: performing cross-clock domain processing on the data to be sent.

Compared with the related art, the technical solution of the present application includes: acquiring processing rate information of data; and processing data according to the acquired processing rate information. The embodiments of the present invention reduce delay jitter and improve data transmission quality.

FIG. 2 is a structural block diagram of an apparatus for processing delay jitter according to an embodiment of the present invention. As shown in FIG. 2 , it includes: an acquisition unit and a processing unit; wherein,

The obtaining unit is used for: obtaining the processing rate information of the data;

The processing unit is used for: processing data according to the acquired processing rate information.

Optionally, the processing unit in the embodiment of the present invention includes a read-write control module and a frame insertion module; wherein,

The read-write control module is used for: when the processing rate information obtained by the obtaining unit includes the write clock frequency and the write clock frequency, read and write the data in the first FIFO according to the read clock frequency and the write clock frequency;

The frame inserting module is configured to: when the processing rate information obtained by the obtaining unit includes the flow information of the link ingress and the link egress, insert the preset data frame into the data to be sent according to the flow information.

Optionally, the read-write control module in the embodiment of the present invention is specifically used for:

Calculate a duty cycle according to the read clock frequency and the write clock frequency;

According to the calculated duty cycle and the preset FIFO buffer water level threshold, it is determined whether to read or write the data in the first FIFO, so as to control the delay fluctuation within the preset interval according to the FIFO buffer water level.

Optionally, the read-write control module in the embodiment of the present invention is specifically configured to: generate an enable signal for whether to read and write data in the first FIFO by using a preset state machine, so as to control the first FIFO according to the generated enable signal. read and write data in.

Optionally, the frame insertion module is specifically used for:

Calculate the number of interval frames

According to the calculation to obtain the number of interval frames X, insert the preset data frame;

为向上取整。Wherein, the V_ge is the traffic value of the link ingress in the optical Ethernet GE mode; the gain_ge is the data gain after the link ingress is processed by the optical conversion unit OTU; the V_out is the traffic value of the link ingress in the mode; the data gain of the forward error correction FEC decoding device of the gain_gfec;

to round up.

Optionally, the frame insertion module is used to obtain the interval frame number X according to the calculation to perform the insertion of the preset data frame, including:

Insert the preset data frame after the interval frame number X TPC frames; or,

When the water level of the second FIFO in the random access memory (RAM) is smaller than the preset storage water level threshold, the preset data frame is inserted after the interval frame number X TPC frames; when the water level of the second FIFO is greater than the preset storage water level threshold When storing the water level threshold, the preset data frame is inserted after adding 1 TPC frame to the number of interval frames X.

Optionally, the frame insertion module is used to calculate the number X of interval frames including:

The number X of the interval frames is calculated according to a preset period.

Optionally, the preset data frame in this embodiment of the present invention includes:

an empty frame of a data frame of a pseudo-random binary sequence PRBS comprising a first preset length of an empty frame identification code and a second preset length; or,

A data frame with the same frame length as the TPC frame in a preset format;

Wherein, the sum of the first preset length and the second preset length is the same as the TPC frame length.

Optionally, the apparatus according to the embodiment of the present invention further includes a cross-clock domain processing unit, configured to perform cross-clock domain processing on the data to be sent before the data to be sent is inserted into the preset data frame.

An embodiment of the present invention further provides a computer storage medium, where computer-executable instructions are stored in the computer storage medium, and the computer-executable instructions are used to execute the above method for processing delay jitter.

An embodiment of the present invention further provides a terminal, including: a memory and a processor; wherein,

the processor is configured to execute program instructions in the memory;

Program instructions are read by the processor to do the following:

Obtain data processing rate information;

Data is processed according to the acquired processing rate information.

The methods of the embodiments of the present invention will be clearly and detailedly described below through application examples, which are only used to describe the present invention, and are not used to limit the protection scope of the present invention.

Application example

The application example takes 100 gigabit (G) digital signal processing (DSP) as an example to introduce the method of processing delay jitter at the originating end. The application example has 64*10 Serdes (serializer) inputs, each input is 64 bits (bit) data.

Referring to the related art, the serializer data is converted to the clock domain of DSP work, and the parallelism is converted from 640 to 320; among them, the first-in-first-out queue (FIFO) size of the clock domain conversion is 32x64bit, a total of 10; the above processing method passes Asynchronous FIFO implementation. When the receiving FIFO of the originating end is full, the read and write pointer and enable of the FIFO need to be cleared. At the same time, when the reading is empty or the writing is full, it needs to be reported to the central processing unit (CPU) respectively, and an abnormal alarm will be generated.

When the processing rate information includes the write clock frequency and the write clock frequency, read and write the data in the first FIFO (the receiving FIFO of the sender) according to the read clock frequency and the write clock frequency;

Optionally, this application example reads and writes data in the first FIFO according to the read clock frequency and the write clock frequency, including:

Calculate the duty cycle according to the read clock frequency and the write clock frequency;

Whether to read or write the data in the first FIFO is determined according to the calculated duty cycle and the preset FIFO buffer water level threshold, so as to control the delay fluctuation within the preset interval according to the FIFO buffer water level.

Optionally, in this embodiment of the present invention, reading and writing data in the first FIFO according to the read clock frequency and the write clock frequency includes:

An enable signal for whether to read and write data in the first FIFO is generated by a preset state machine, so as to read and write data in the first FIFO according to the generated enable signal.

The state machine preset in this application example generates an enable signal for whether to read or write data in the first FIFO. Figure 3 is a schematic diagram of the state machine of the application example of the present invention. As shown in Figure 3, the FIFO buffer water level threshold of this application example is It is half of the water level of the first FIFO, this application example is referred to as half water level; in this application example, when the duty cycle is equal to 2, 3, the state machine outputs enable in the S_0 state, and outputs 0 in the other states; when the duty cycle is equal to 4 , 6, 7, the state machine outputs 0 in the S_0 state, and the output of other states is enabled. When the duty cycle is 0, it means that the read enable is not controlled by the duty cycle, and the water level is half full, and it is read, and it is not read when it is less than half full. The specific work of the state machine includes:

When the system is reset or cleared, the state machine enters the initial state (IDLE); in this state, when it is judged that the first FIFO read water level is greater than or equal to the half water level, the state machine enters the S_0 state.

In the S_0 state, the state machine unconditionally jumps to S_1;

In the S_1 state, when it is judged that the first FIFO read water level is greater than or equal to the half water level, and the duty cycle is 2, the state machine jumps to the S_0 state; it is judged that the first FIFO read water level is less than the half water level or the duty cycle is not equal to 2, the state machine jumps to the S_2 state;

In the S_2 state, when it is judged that the first FIFO read water level is greater than or equal to the half water level and the duty cycle is 3 or 2, the state machine jumps to the S_0 state; it is judged that the first FIFO read water level is less than the half water level or the duty cycle When not equal to 2 and 3, the state machine jumps to the S_3 state;

In the S_3 state, when it is judged that the first FIFO read water level is less than the half water level and the duty cycle is 4 or 3, the state machine jumps to the S_0 state; it is judged that the first FIFO read water level is greater than or equal to the half water level, or the duty cycle When not 3 and 4, the state machine jumps to the S_4 state;

In the S_4 state, the state machine unconditionally jumps to the S_5 state;

In the S_5 state, when it is judged that the first FIFO read water level is less than the half water level and the duty cycle is 6 or 4, the state machine jumps back to the S_0 state; it is judged that the first FIFO read water level is greater than or equal to the half water level, or the duty cycle is 6 or 4. When the ratio is not equal to 6 and 4, the state machine jumps to the S_6 state;

In the S_6 state, when it is judged that the first FIFO read water level is less than the half water level and the duty cycle is 7, the state machine jumps back to the S_0 state; it is judged that the first FIFO read water level is greater than or equal to the half water level, or the duty cycle is not When equal to 7, the state machine jumps to the S_7 state;

In the S_7 state, when it is judged that the duty cycle is 7, the state machine jumps back to the S_0 state; when it is judged that the duty cycle is not equal to 7, the state machine jumps to the S_8 state;

In the S_8 state, the state machine unconditionally jumps to the S_0 state.

In this application example, the data in the first FIFO is read according to the read enable of different states of the state machine, so that the delay fluctuation within the preset interval is controlled according to the buffer water level of the first FIFO.

This application example selects the data of the output FIFO according to the related technology. If it is 10 channels, select the output data of all 10 channel FIFOs; if it is 4 channels, select the read data of the lower 4 FIFOs. Because the output data is only 256bit with 4 channels, it is necessary to supplement 64bits with high bits on the optical transmission processing device, so that it is unified into 320bits with 10 channels.

By using the enable generated by the state machine, data is read from the first FIFO, and the even distribution of the read enable enables the data to flow out evenly, reducing delay jitter. Referring to the data read enable processing of the first FIFO in this application example, the data is read out to the optical transmission processing device and the turbo product code encoding processing device for data stream processing; Figure 4 is a schematic diagram of the connection of the state machine in the 100GDSP for this application example, as shown in the figure As shown in 4, the state machine is connected to the read port of the first FIFO for sending out a read enable signal, and the read data is sent to the optical transmission processing device and the turbo product code encoding processing device.

In this application example, frame insertion can be performed before the sender sends data. The data can come from the output data of the turbo product code encoding (TPCE) device, or the Pseudo-Random Binary Sequence (PRBS) data generated by the sender. Before frame insertion, The above data are processed as follows: inserting frame headers and training sequences, performing pulse shaping and pre-emphasis filtering on the modulated signal, nonlinear pre-compensation, and register configuration, that is, data selection.

Because the data rate, i.e., the flow, of the link ingress rate of the 100G DSP originating end is different in 100 Ethernet (GE) mode/100G mode/OTU pass-through, but it is sent at a custom fixed rate at the link egress originating from the 100G DSP; resulting in 100G The link traffic at the originating end of the DSP does not match, resulting in unstable internal storage (such as FIFO water level, etc.), and long-term accumulation will cause read empty or overflow (FIFO will appear empty), which will lead to link instability and delay. jitter, which affects the quality of data transmission.

This application example determines whether to insert a preset data frame according to the traffic information of the link ingress and link egress, that is, whether to insert a preset data frame when the data is insufficient; the preset data frame can be an empty frame, whether to insert an empty frame Can be turned on or off. FIG. 5 is a schematic structural diagram of a null frame according to an embodiment of the present invention. As shown in FIG. 5 , the null frame includes a null frame identification code of a first preset length and a pseudo-random binary sequence (PRBS) of a second preset length. For example, the beginning of a null frame is a 192-bit long null frame identifier, followed by a 31-order PRBS, and the total data length of the null frame is 432 beats, which is consistent with the TPC frame size. The optical signal data is divided into two in-phase (I) and quadrature (Q) polarization state data by the polarization beam splitter (PBS); and then mixed with the local vibration laser machine to output the in-phase real part (XI) signal, in-phase The signal of the imaginary part (YI), the signal of the quadrature real part (XQ), the signal of the quadrature imaginary part (YQ); in this application example, the empty frame identification codes of the two channels XI and YI are the same; The empty frame identification code is the same, and the empty frame identification code can be configured. The following is an example of an empty frame identifier,

Empty frame identification code of channel XI:

011011000101011011010100001100011000000001100101100100111100001001010110100100001111000101100111011111101111001101011001101001110010010111110110100110010110010110110111001000010011010101011000；

Empty frame identification code of XQ road:

0011001000000111000000110011011010101010011000011000111101011000000001111011010010010010001010111011001100110010010010011001111111111111111111111100111111111001111001111001111111100

The receiver performs differential decoding according to the empty frame structure and deletes the empty frame.

In this application example, the PRBS inserted in the empty frame is of order 31, and the four-way interleaving is allocated to the four-way, as shown in Table 1:

XI prbs[255], prbs[251], ...prbs[3] XQ prbs[254], prbs[250], ... prbs[2] YI prbs[253], prbs[249], ...prbs[1] YQ prbs[252], prbs[248], ...prbs[0]

Table 1

The empty frame inserted in this application example needs to do constellation mapping, and the mapping method is a bit inversion operation. In this application example, the number of interval frames X is calculated according to a preset period, and the preset period may be a fixed period or a dynamically changing period. For example, the first calculation of the number of interval frames X is obtained by those skilled in the art based on verification analysis , after calculating the number of interval frames X, the number of interval frames X obtained by the latest calculation is used as the next preset period;

Optionally, the process of inserting the data to be sent into the preset data frame includes:

Calculate the number of interval frames

According to the calculation to obtain the number of interval frames X, insert the preset data frame;

为向上取整。Among them, V_ge is the traffic value of the link ingress in the Ethernet (GE) mode; gain_ge is the data gain after the link ingress is processed by the optical conversion unit (OTU); V_out is the traffic value of the link ingress in the mode; gain_gfec forward The data gain of the error correction (FEC) decoding device;

to round up.

This application example is for 100 gigabit (G) digital signal processing (DSP),

TPC frame ratio n=V_100ge*gain_100ge/(V_otu*gain_fec);

The ratio of empty frames is 1-n;

TPC frame and empty frame ratio rate_np2100ge=n/(1-n);

The number of interval frames X is the upward rounding of the value of rate_np2100ge;

Among them, V_100ge is: in 100GE mode, the data traffic at the link ingress of the 100G DSP originating end; gain_100ge is: in 100GE mode, the data gain of the originating link ingress data after OTU processing; V_out is: in OTU mode, 100G The data flow at the entry of the link sent by the DSP; gain_gfec is: the data gain of the FEC decoding module.

Optionally, the embodiment of the present invention performs the insertion of the preset data frame according to the number X of the interval frames obtained by calculation, including:

Insert a preset data frame after the interval frame number X TPC frames; or,

When the water level of the second FIFO composed of random access memory (RAM) is lower than the preset storage water level threshold, the preset data frame is inserted after the interval frame number X TPC frames; when the water level of the second FIFO is greater than the preset storage water level When the water level threshold is set, the preset data frame is inserted after the interval frame number X plus 1 TPC frame.

Optionally, calculating the number X of interval frames in this embodiment of the present invention includes:

The number X of the interval frames is calculated according to a preset period.

Since the empty frame and the data to be sent belong to the asynchronous clock, before inserting the preset data frame, this application example performs cross-clock domain processing on the data. The cross-clock domain processing method may include the existing implementation methods in the related art, here I won't go into details.

Those of ordinary skill in the art can understand that all or part of the steps in the above method can be completed by instructing relevant hardware (such as a processor) through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk or an optical disk Wait. Optionally, all or part of the steps in the above embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the above-mentioned embodiments can be implemented in the form of hardware, for example, an integrated circuit to implement its corresponding function, or it can be implemented in the form of a software function module, for example, a processor executes a function stored in a memory. program/instruction to achieve its corresponding function. The present invention is not limited to any particular form of combination of hardware and software.

Although the embodiments disclosed in the present invention are as above, the described contents are only the embodiments adopted to facilitate the understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art to which the present invention belongs, without departing from the spirit and scope disclosed by the present invention, can make any modifications and changes in the form and details of the implementation, but the scope of the patent protection of the present invention still needs to be The scope defined by the appended claims shall prevail.

Claims (14)

1. A method of handling delay jitter, comprising:

acquiring processing rate information of data;

calculating a duty ratio according to the read clock frequency and the write clock frequency when the processing rate information comprises the read clock frequency and the write clock frequency; determining whether to read and write data in the first FIFO according to the calculated duty ratio and a preset FIFO cache water level threshold value so as to control the delay to fluctuate in a preset interval according to the FIFO cache water level;

when the processing rate information comprises the flow information of a link inlet and a link outlet, inserting preset data frames into data to be sent according to the flow information;

the processing of inserting the preset data frame into the data to be sent out includes:

calculating the number of interval frames

Inserting the preset data frame according to the number X of the interval frames obtained by calculation;

wherein, V _ GE is the flow value of the link entrance under the GE mode; gain _ ge is data gain of the link entrance after being processed by the optical switching unit OTU; v _ OTU is the flow value of the link entrance in the OTU mode; gain-fec forward error correction FEC data gain of the decoding device;

is rounded up.

2. The method of claim 1, wherein reading and writing data in the first FIFO comprises:

and generating an enabling signal whether to read and write the data in the first FIFO through a preset state machine so as to read and write the data in the first FIFO according to the generated enabling signal.

3. The method according to claim 1, wherein said inserting the predetermined data frame according to the calculated number X of the interval frames comprises:

inserting the preset data frame after X TPC frames are spaced; or,

when the water level of a second FIFO (first in first out) consisting of a Random Access Memory (RAM) is smaller than a preset storage water level threshold value, inserting a preset data frame after X TPC (transmit power control) frames are spaced by the number of frames; and when the water level of the second FIFO is greater than a preset storage water level threshold, inserting the preset data frame after adding 1 TPC frame to the number X of the interval frames.

4. The method of claim 1, wherein said calculating the number X of inter frames comprises:

and calculating the number X of the interval frames according to a preset period.

5. The method of claim 1, 3 or 4, wherein the default data frame comprises:

the null frame comprises a null frame identification code with a first preset length and a data frame of a pseudo random binary sequence PRBS with a second preset length; or,

presetting a data frame with the same format as the TPC frame;

wherein the sum of the first preset length and the second preset length is the same as the TPC frame length.

6. The method according to claim 1, 2, 3 or 4, wherein before the processing of inserting the preset data frame into the data to be sent out, the method further comprises:

and performing clock domain crossing processing on the data to be sent.

7. An apparatus for processing delay jitter, comprising: an acquisition unit and a processing unit; wherein,

the acquisition unit is used for: acquiring processing rate information of data;

the processing unit is used for: processing data according to the acquired processing rate information;

the processing unit comprises a read-write control module and a frame insertion module; wherein,

the read-write control module is used for: when the processing rate information acquired by the acquisition unit comprises a read clock frequency and a write clock frequency, reading and writing data in the first FIFO according to the read clock frequency and the write clock frequency;

the frame insertion module is used for: when the processing rate information acquired by the acquisition unit includes flow information of a link inlet and a link outlet, performing processing of inserting a preset data frame into data to be transmitted according to the flow information;

the read-write control module is specifically configured to:

calculating a duty cycle from the read clock frequency and the write clock frequency;

determining whether to read and write data in the first FIFO according to the calculated duty ratio and a preset FIFO cache water level threshold value so as to control the delay to fluctuate in a preset interval according to the FIFO cache water level;

the frame insertion module is specifically configured to:

calculating the number of interval frames

Inserting the preset data frame according to the number X of the interval frames obtained by calculation;

wherein, V _ GE is the flow value of the link entrance under the GE mode; gain _ ge is data gain of the link entrance after being processed by the optical switching unit OTU; v _ OTU is the flow value of the link entrance in the OTU mode; the data gain of the gain _ FEC FEC decoding device;

is rounded up.

8. The apparatus of claim 7, wherein the read-write control module is specifically configured to: and generating an enabling signal whether to read and write the data in the first FIFO through a preset state machine so as to read and write the data in the first FIFO according to the generated enabling signal.

9. The apparatus of claim 7, wherein the frame insertion module is configured to insert the preset data frame according to the number X of the interval frames obtained by calculation includes:

inserting the preset data frame after X TPC frames are spaced; or,

when the water level of a second FIFO (first in first out) consisting of a Random Access Memory (RAM) is smaller than a preset storage water level threshold value, inserting a preset data frame after X TPC (transmit power control) frames are spaced by the number of frames; and when the water level of the second FIFO is greater than a preset storage water level threshold, inserting the preset data frame after adding 1 TPC frame to the number X of the interval frames.

10. The apparatus of claim 7, wherein the frame interpolation module is configured to calculate the number X of inter frames comprises:

and calculating the number X of the interval frames according to a preset period.

11. The apparatus of claim 8, 9 or 10, wherein the predetermined data frame comprises:

the null frame comprises a null frame identification code with a first preset length and a data frame of a pseudo random binary sequence PRBS with a second preset length; or,

presetting a data frame with the same format as the TPC frame;

wherein the sum of the first preset length and the second preset length is the same as the TPC frame length.

12. The apparatus according to claim 8, 9 or 10, further comprising a clock domain crossing processing unit, configured to perform clock domain crossing processing on the data to be sent before performing processing for inserting a preset data frame on the data to be sent.

13. A computer storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement a method of handling delay jitter as claimed in any one of claims 1 to 6.

14. A terminal, comprising: a memory and a processor; wherein,

the processor is configured to execute program instructions in the memory;

the program instructions read on the processor to perform the following operations:

acquiring processing rate information of data;

calculating a duty ratio according to the read clock frequency and the write clock frequency when the processing rate information comprises the read clock frequency and the write clock frequency; determining whether to read and write data in the first FIFO according to the calculated duty ratio and a preset FIFO cache water level threshold value so as to control the delay to fluctuate in a preset interval according to the FIFO cache water level;

when the processing rate information comprises the flow information of a link inlet and a link outlet, inserting preset data frames into data to be sent according to the flow information;

the processing of inserting the preset data frame into the data to be sent out includes:

calculating the number of interval frames

Inserting the preset data frame according to the number X of the interval frames obtained by calculation;

wherein, V _ GE is the flow value of the link entrance under the GE mode; gain _ ge is data gain of the link entrance after being processed by the optical switching unit OTU; v _ OTU is the flow value of the link entrance in the OTU mode; the data gain of the gain _ FEC FEC decoding device;

is rounded up.

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