CN119300401A - Tunnel gate HEMT device, preparation method, chip and electronic device - Google Patents

Abstract

The application discloses a tunneling gate HEMT device, a preparation method, a chip and electronic equipment, wherein the device structure comprises a substrate layer, a transition layer, a buffer layer, a channel layer and a barrier layer which are sequentially arranged on the substrate layer, a p-GaN layer arranged on the barrier layer, an isolation structure arranged on the side wall of the HEMT device, wherein the isolation structure penetrates through the barrier layer and the channel layer and is arranged on the buffer layer, a passivation layer arranged on the side wall of the p-GaN layer and on the barrier layer, a tunneling layer arranged at the bottom and the side part of a gate opening area of the passivation layer, a gate penetrating through the passivation layer and arranged on the tunneling layer, and a source electrode and a drain electrode respectively arranged on different sides of the p-GaN layer, wherein the source electrode and the drain electrode respectively penetrate through the passivation layer and are arranged on the barrier layer. Compared with the related art, the method has the advantages that a thin dielectric layer is deposited inside the gate slot to serve as a tunneling layer, so that the gate breakdown voltage of the HEMT device is effectively improved.

Description

Tunnel gate HEMT device, preparation method, chip and electronic device

Technical Field

The present application relates to the technical field of semiconductor devices, and in particular to a tunnel gate HEMT device, a preparation method, a chip and an electronic device.

Background Art

As a representative material of the third-generation semiconductors, GaN has the advantages of high breakdown voltage, wide bandgap and high electron mobility. The High Electron Mobility Transistor (HEMT) device prepared using it has the advantages of low cost and high performance compared to traditional Si-based power devices, and has great potential in high-voltage and high-power electronic power applications.

At present, the solution of using p-GaN cap layer as gate to realize enhancement mode device has been basically commercialized. However, in practical applications, the gate breakdown voltage of the p-GaN gate device used is not high enough, and the overshoot signal in the circuit can easily burn the device, which greatly threatens the reliability of the entire circuit system during the switching process.

Summary of the invention

The purpose of the present application is to provide a tunnel gate HEMT device, a preparation method, a chip and an electronic device to solve the problem in the related art that the gate breakdown voltage of a conventional p-GaN gate device is not high enough and is easily burned by an overshoot signal in the circuit.

In order to achieve the above objectives, this application provides the following technical solutions:

In a first aspect, the present application provides a tunnel gate HEMT device, comprising:

A substrate layer, a transition layer, a buffer layer, a channel layer and a barrier layer sequentially disposed on the substrate layer;

A p-GaN layer located on the barrier layer;

an isolation structure, located on a sidewall of the HEMT device, wherein the isolation structure penetrates the barrier layer and the channel layer and is located on the buffer layer;

a passivation layer, located on the side wall of the p-GaN layer and on the barrier layer, wherein the thickness of the passivation layer ranges from 50 nm to 400 nm, and the passivation layer comprises: a first passivation sublayer and a second passivation sublayer, the first passivation sublayer is located below the second passivation sublayer, the first passivation sublayer material comprises: at least one of AlN, SiON, SiN, AlON, Al ₂ O ₃ , HfO ₂ , ZrO ₂ and Y ₂ O ₃ , and the second passivation sublayer material comprises: at least one of SiO ₂ , SiN and SiON;

A tunneling layer, located at the bottom and side of the gate opening region of the passivation layer, wherein the thickness of the tunneling layer is in the range of 0.5 nm to 5 nm, and the material of the tunneling layer includes at least one of SiN, SiON, AlN, AlON and Al ₂ O ₃ ;

A gate, which penetrates the passivation layer and is located on the tunneling layer;

A source electrode, located on one side of the p-GaN layer, wherein the source electrode penetrates the passivation layer and is located on the barrier layer;

A drain electrode is located on the other side of the p-GaN layer, wherein the drain electrode penetrates the passivation layer and is located on the barrier layer.

Furthermore, the thickness of the p-GaN layer is in the range of 50 nm-500 nm; and the Mg doping concentration of the p-GaN layer is in the range of 10 ¹⁸ cm ^-3 -10 ²⁰ cm ^-3 .

Further, the thickness range of the transition layer is 10 nm-500 nm, and the material of the transition layer includes: at least one of AlN, AlGaN and GaN; the thickness range of the buffer layer is 300 nm-6000 nm, and the material of the buffer layer includes: at least one of high-resistance GaN and high-resistance AlGaN; the thickness range of the channel layer is 50 nm-500 nm, and the material of the channel layer includes: unintentionally doped GaN; the thickness range of the barrier layer is 10 nm-40 nm, and the material of the barrier layer includes: Al _x Ga _1-x N, wherein the value range of x is 0.1-0.5.

Furthermore, the isolation structure includes: any one of a mesa isolation structure and an ion implantation structure.

In a second aspect, the present application further provides a method for preparing a tunnel gate HEMT device, comprising:

providing a substrate layer;

Growing a transition layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer in sequence on the substrate layer;

Depositing TiN metal and SiN dielectric in sequence on the upper surface of the p-GaN layer to form a TiN protective layer and a SiN protective layer;

An isolation structure is formed on the upper surface of the SiN protective layer and outside the active region of the device, wherein the isolation structure penetrates the SiN protective layer, the TiN protective layer, the p-GaN layer, the barrier layer and the channel layer;

forming a gate region on the upper surface of the SiN protective layer, and etching the SiN protective layer, the TiN protective layer and the p-GaN layer outside the gate region to a depth reaching the upper surface of the barrier layer;

Removing the SiN protective layer and the TiN protective layer on the upper surface of the HEMT device by a wet method;

A dielectric material is deposited on the upper surface of the barrier layer, the upper surface of the p-GaN layer and the sidewall of the p-GaN layer to form a passivation layer, wherein the thickness of the passivation layer ranges from 50 nm to 400 nm, and the passivation layer comprises: a first passivation sublayer and a second passivation sublayer, the first passivation sublayer is located below the second passivation sublayer, the material of the first passivation sublayer comprises: at least one of AlN, SiON, SiN, AlON, Al ₂ O ₃ , HfO ₂ , ZrO ₂ and Y ₂ O ₃ , and the material of the second passivation sublayer comprises: at least one of SiO ₂ , SiN and SiON;

A gate opening region is formed on the upper surface of the passivation layer in the gate region, and the dielectric layer in the gate opening region is etched away until the upper surface of the p-GaN layer, and a tunneling dielectric is deposited on the sidewall and bottom of the gate opening region to form a tunneling layer, wherein the thickness of the tunneling layer is in the range of 0.5 nm to 5 nm, and the material of the tunneling layer includes at least one of SiN, SiON, AlN, _AlON and _Al2O3 ;

forming a gate metal region on the upper surface of the tunneling layer, and depositing a gate metal to form a gate;

A source region and a drain region are respectively formed on the upper surface of the passivation layer, and the passivation layers of the source region and the drain region are etched until the upper surface of the barrier layer to form a source etching region and a drain etching region, and metal is deposited in the source etching region and the drain etching region to form a source and a drain.

Furthermore, the step of sequentially growing a transition layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer on the substrate layer comprises:

A metal organic chemical vapor deposition process is adopted to sequentially grow a transition layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer on the substrate layer.

Furthermore, the step of sequentially depositing TiN metal and SiN dielectric on the upper surface of the p-GaN layer to form a TiN protective layer and a SiN protective layer includes:

Depositing TiN metal on the upper surface of the p-GaN layer using a physical vapor deposition process to form a TiN protective layer;

A SiN medium is deposited on the upper surface of the TiN protective layer by using a chemical vapor deposition process to form a SiN protective layer.

Further, the step of depositing a dielectric material on the upper surface of the barrier layer, the upper surface of the p-GaN layer and the sidewall of the p-GaN layer to form a passivation layer includes:

By using any one of a plasma enhanced atomic layer deposition process, an atomic layer deposition process, a plasma enhanced chemical vapor deposition process and a low pressure chemical vapor deposition process, a dielectric material is deposited on the upper surface of the barrier layer, the upper surface of the p-GaN layer and the side wall of the p-GaN layer to form a passivation layer.

Furthermore, forming a gate opening region on the upper surface of the passivation layer in the gate region, etching the dielectric layer in the gate opening region until the upper surface of the p-GaN layer, and depositing a tunneling dielectric on the sidewall and bottom of the gate opening region to form a tunneling layer includes:

By adopting any one of plasma enhanced atomic layer deposition process, atomic layer deposition process, plasma enhanced chemical vapor deposition process and low pressure chemical vapor deposition process, a gate opening area is formed on the upper surface of the passivation layer in the gate area, and the dielectric layer in the gate opening area is etched away until the upper surface of the p-GaN layer, and a tunneling medium is deposited on the side wall and the bottom of the gate opening area to form a tunneling layer.

In a third aspect, the present application further provides a chip, comprising: a tunneling gate HEMT device as described in any one of the above.

In a fourth aspect, the present application also provides an electronic device, which includes: the chip as described above.

The present application provides a tunnel gate HEMT device, a preparation method, a chip and an electronic device, which have the following beneficial effects:

1. The tunneling gate HEMT device provided in the present application deposits a thin dielectric layer as a tunneling layer inside the gate groove. The thin dielectric tunneling layer controls current transmission through the quantum tunneling effect. The precisely controlled deposited thin dielectric layer can optimize the tunneling probability, so that under normal working conditions, only a small number of electrons can tunnel through the dielectric layer, thereby effectively reducing the gate leakage current.

2. This application can change the energy band structure of the device by selecting appropriate dielectric materials and accurately deposited tunneling layers, increasing the barrier height for electrons to transfer from the source to the drain. When the gate voltage does not reach a certain threshold, it is difficult for electrons to cross this barrier, thereby increasing the threshold voltage of the device. This makes the device in the off state at a lower gate voltage, enhancing the switching characteristics of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of a tunnel gate HEMT device according to an embodiment of the present application;

2a-2i are detailed schematic diagrams of a preparation process of a tunnel gate HEMT device according to an embodiment of the present application;

FIG3 is a schematic flow chart of a method for preparing a tunnel gate HEMT device according to an embodiment of the present application;

FIG. 4 is a schematic diagram of actual test results of a gate breakdown voltage of a tunneling gate HEMT device provided in an embodiment of the present application.

Figure numerals: 1, substrate layer; 2, transition layer; 3, buffer layer; 4, channel layer; 5, barrier layer; 6, drain; 7, source; 8, isolation structure; 91, p-GaN layer; 92, tunneling layer; 93, gate; 94, TiN protective layer; 95, SiN protective layer; 100, passivation layer; 10, first passivation sublayer; 11, second passivation sublayer.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include: one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

The terms used in one or more embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of the present application. The singular forms "a", "said" and "the" used in one or more embodiments of the present application are also intended to include: plural forms, unless the context clearly indicates other meanings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of the template are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and/or" used herein includes any and all combinations of one or more of the related listed items.

It should be understood that, although the terms first, second, etc. may be used to describe various information in one or more embodiments of the present application, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of the present application, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when the time of".

At present, the gate breakdown voltage of existing p-GaN gate devices is not high enough, and they are easily broken down by overshoot signals in the circuit, causing the device to burn out, which greatly threatens the reliability of the entire circuit system during the switching process.

The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes are not repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

Referring to FIG. 1 , an embodiment of the present application provides a tunnel gate HEMT device, comprising: a substrate layer 1, a transition layer 2, a buffer layer 3, a channel layer 4 and a barrier layer 5 sequentially located on the substrate layer 1; a p-GaN layer 91 located on the barrier layer 5; an isolation structure 8 located on the side wall of the HEMT device, wherein the isolation structure 8 penetrates the barrier layer 5 and the channel layer 4 and is located on the buffer layer 3; a passivation layer 100 located on the side wall of the p-GaN layer 91 and on the barrier layer 5, wherein the thickness of the passivation layer 100 ranges from 50 nm to 400 nm, and the passivation layer 100 comprises: a first passivation sublayer 10 and a second passivation sublayer 11, wherein the first passivation sublayer 10 is located below the second passivation sublayer 11, and the material of the first passivation sublayer 10 comprises: AlN, SiON, SiN, AlON, Al ₂ O ₃ , HfO ₂ , ZrO ₂ and Y ₂ O ₃ , the material of the second passivation sublayer 11 includes: at least one of SiO ₂ , SiN and SiON; a tunneling layer 92, located at the bottom and side of the gate opening area of the passivation layer 100, wherein the thickness of the tunneling layer 92 ranges from 0.5 nm to 5 nm, and the material of the tunneling layer 92 includes: at least one of SiN, SiON, AlN, AlON and Al ₂ O ₃ ; a gate 93, penetrating the passivation layer 100 and located on the tunneling layer 92; a source electrode 7, located on one side of the p-GaN layer 91, wherein the source electrode 7 penetrates the passivation layer 100 and is located on the barrier layer 5; a drain electrode 6, located on the other side of the p-GaN layer 91, wherein the drain electrode 6 penetrates the passivation layer 100 and is located on the barrier layer 5.

In the above scheme, a thin dielectric layer is deposited inside the slot of the gate 93 as a tunneling layer 92. The thin dielectric tunneling layer 92 controls current transmission through the quantum tunneling effect. The precisely controlled deposited thin dielectric layer can optimize the tunneling probability, so that under normal working conditions, only a small number of electrons can tunnel through the passivation layer 100, thereby effectively reducing the leakage current of the gate 93. Through this application, the problem that the breakdown voltage of the gate 93 of the traditional p-GaN gate device is not high enough and is easily burned by the overshoot signal in the circuit can be solved. The above-mentioned structures are described in detail below in conjunction with the accompanying drawings.

As shown in FIG1 , a substrate layer 1 is provided, and the substrate layer 1 can be any one of a sapphire substrate, a Si substrate, a SiC substrate, a diamond substrate, a glass substrate, a ceramic substrate and a polymer substrate, as a support structure and carrier structure of the HEMT device. As shown in FIG1 , a transition layer 2, a buffer layer 3, a channel layer 4 and a barrier layer 5 are formed on the substrate layer 1; when determining the material of the transition layer 2, the material of the transition layer 2 can be at least one of AlN, AlGaN and GaN. It should be noted that the thickness of the transition layer 2 can range from 10 nm to 500 nm to ensure better regulation of the stress between the substrate layer 1 and the buffer layer 3.

Please continue to refer to Figure 1. A buffer layer 3, a channel layer 4 and a barrier layer 5 are also formed on the transition layer 2. When determining the material of the buffer layer 3, the material of the buffer layer 3 in this example can be at least one of high-resistance GaN and high-resistance AlGaN, and the thickness of the buffer layer 3 can be controlled in the range of 300 nm-6000 nm, so that the buffer layer 3 can grow normally and will not be longitudinally broken down.

Please continue to refer to FIG. 1 . A channel layer 4 and a barrier layer 5 are formed on the buffer layer 3 . When determining the materials of the channel layer 4 and the barrier layer 5 , the material of the channel layer 4 in this embodiment may be unintentionally doped GaN, and the material of the barrier layer 5 may be Al _x Ga _1-x N, where x ranges from 0.1 to 0.5.

It should be noted that, in this embodiment, the thickness range of the channel layer 4 can be controlled between 50 nm and 500 nm, and the thickness range of the barrier layer 5 can be controlled between 10 nm and 40 nm, so as to ensure that the channel layer 4 and the barrier layer 5 can cooperate with each other to generate two-dimensional electron gas (2DEG) by utilizing the polarization effect.

It can be understood that the channel layer 4 provides a suitable space for the formation of two-dimensional electron gas (2DEG). Due to the polarization effect, a strong electric field is generated near the interface between AlGaN and GaN. This electric field causes the electrons in the GaN channel layer 4 to be attracted to the interface.

The presence of the barrier layer 5 is crucial to the formation of 2DEG. Due to the polarization difference between AlGaN and GaN, polarization charges are generated at the interface. These polarization charges form a high electric field region near the interface, and because the band gap of AlGaN is wider than that of GaN, an energy barrier is formed at the interface. This barrier can effectively limit the movement of electrons in the direction perpendicular to the interface, confining electrons near the interface between the GaN channel layer 4 and the AlGaN barrier layer 5, so that electrons can only move in a two-dimensional plane parallel to the interface, thereby promoting the formation of 2DEG. At the same time, the barrier layer 5 can also block the interference of impurities and the like on the 2DEG in the channel layer 4, thereby improving the stability and electrical properties of 2DEG.

Please continue to refer to FIG. 1 . A p-GaN layer 91 is grown on the barrier layer 5 . In this example, the doping concentration range of Mg in the p-GaN layer 91 can be controlled between 10 ¹⁸ cm ^-3 and 10 ²⁰ cm ^-3 , and the thickness range of the p-GaN layer 91 can be controlled between 50 nm and 500 nm, so that the p-GaN layer 91 can deplete the two-dimensional electron gas under the gate 93 .

Please continue to refer to FIG. 1 . The sidewall of the HEMT device further includes an isolation structure 8 . The isolation structure 8 runs through the barrier layer 5 and the channel layer 4 and is located on the buffer layer 3 . It can be understood that by providing the isolation structure 8 on the sidewall of the HEMT device, an isolation region can be formed and parasitic effects can be reduced.

In a specific embodiment, the isolation structure 8 includes: any one of a mesa isolation structure and an ion implantation structure.

Specifically, the mesa isolation structure refers to an isolation structure formed in the mesa area of the device through etching and other processes during the manufacturing process of semiconductor devices. It is used to achieve electrical isolation between different device areas, reduce leakage, crosstalk and other problems, and improve device performance and reliability.

Ion implantation structure refers to a doping structure that uses an ion implanter to accelerate and implant impurity ions into semiconductor materials. By controlling the type, energy, dose, angle and other parameters of the implanted ions, the electrical properties of semiconductor materials, such as carrier concentration, conductivity type, etc., can be precisely changed, thereby achieving regulation of semiconductor device performance.

Please continue to refer to FIG. 1 . A passivation layer 100 is grown on the sidewall of the p-GaN layer 91 and on the barrier layer 5 . It can be understood that the passivation layer 100 can improve the electrical performance of the HEMT device and protect the surface of the device.

Specifically, in HEMT devices, the density of states at the semiconductor surface and interface has a significant impact on the electrical properties of the device. The passivation layer 100 can reduce the density of surface states and interface states. When there is no passivation layer 100, the surface states and interface states will capture or release carriers (electrons or holes), resulting in increased carrier scattering and decreased mobility, which seriously affects the dynamic characteristics of the device. For example, in AlGaN/GaN HEMT devices, the passivation layer 100 can fill defects on the surface and interface, reduce the unintended capture and scattering of carriers at these locations, thereby increasing electron mobility and improving the device's transconductance and output current and other performance.

During the operation of the device, the distribution of the electric field inside the semiconductor material and on the surface and interface is critical. For example, near the gate 93 of the HEMT, the change in the electric field strength will affect the injection and transport of carriers. The presence of the passivation layer 100 can adjust the distribution of the electric field on the surface, making it more uniform and stable, avoiding problems such as device breakdown caused by electric field concentration, and is also conducive to improving the reliability and stability of the device.

Continuing to refer to FIG. 1 , the HEMT device further includes: a tunneling layer 92 formed at the bottom and side of the gate opening region of the passivation layer 100 . In the present embodiment, the material of the tunneling layer 92 may include: at least one of SiN, SiON, AlN, AlON and Al ₂ O _{3 .} The thickness of the tunneling layer 92 may be controlled within a range of 0.5 nm to 5 nm.

Please refer to FIG. 4 . It can be seen from FIG. 4 that after the tunneling layer 92 is added, the breakdown voltage of the gate 93 gradually increases. The Schottky in FIG. 4 represents a Schottky contact.

The present application provides a tunnel gate HEMT device, a preparation method, a chip and an electronic device, which have the following beneficial effects:

1. The tunneling gate HEMT device provided in the present application deposits a thin dielectric layer as a tunneling layer 92 inside the gate groove. The tunneling layer 92 controls current transmission through the quantum tunneling effect. The precisely controlled deposited thin dielectric layer can optimize the tunneling probability, so that under normal working conditions, only a small number of electrons can tunnel through the dielectric layer, thereby effectively reducing the gate leakage current.

2. The present application can change the energy band structure of the device by selecting suitable dielectric materials and a precisely deposited tunneling layer 92, so that the voltage division at the gate metal, tunneling layer 92, and p-GaN layer 91 is larger (the Schottky junction becomes a MIS junction), and the effective voltage for opening the channel (p-GaN, AlGaN, and GaN) is reduced, so a higher gate voltage is required to open the channel, thereby increasing the threshold voltage of the device.

Please refer to FIGS. 2a-2i and 3 . The present application also provides a method for preparing a tunnel gate HEMT device, which is applied to prepare the above-mentioned tunnel gate HEMT device and at least comprises the following steps:

S10, providing a substrate layer 1.

Specifically, the substrate layer 1 may be any one of a sapphire substrate, a Si substrate, a SiC substrate, a diamond substrate, a glass substrate, a ceramic substrate, and a polymer substrate.

S20 , sequentially growing a transition layer 2 , a buffer layer 3 , a channel layer 4 , a barrier layer 5 and a p-GaN layer 91 on the substrate layer 1 .

Specifically, referring to FIG. 2 a , in this example, a transition layer 2 , a buffer layer 3 , a channel layer 4 , a barrier layer 5 and a p-GaN layer 91 are sequentially grown on the substrate layer 1 by a metal organic chemical vapor deposition process.

In a specific embodiment, a transition layer 2 with a thickness of 10 nm-500 nm, a high-resistance AlGaN buffer layer 3 with a thickness of 300 nm-6000 nm, an unintentionally doped GaN channel layer 4 with a thickness of 50 nm-500 nm, an Al _x Ga _1-x N barrier layer 5 with a thickness of 10 nm-40 nm, and a p-GaN layer 91 with a thickness of 50 nm-500 nm and a Mg doping concentration of 10 ¹⁸ cm ^-3 -10 ²⁰ cm ^-3 are sequentially grown on a substrate layer 1 by using a metal organic chemical vapor deposition process; wherein the value range of x is 0.1-0.5.

S30 , depositing TiN metal and SiN dielectric in sequence on the upper surface of the p-GaN layer 91 to form a TiN protective layer 94 and a SiN protective layer 95 .

Specifically, please refer to FIG. 2b. Before the subsequent etching process of the p-GaN layer 91, the surface is first protected to prevent the surface from being contaminated. For example, when the isolation structure 8 is generated by ion implantation, the surface of the HEMT device will be bombarded by high-energy ions and become rough. Therefore, a protective layer is required to absorb the bombardment of the surface to prevent the semiconductor surface from being damaged. In addition, since _SiH4 is usually used as a source when depositing SiN, H is easily introduced during growth. The Mg in p-GaN is easily passivated by H to form a Mg-H complex, which affects the device performance. Therefore, TiN is used as an intermediate layer to block the penetration of H.

In a specific embodiment, TiN metal is deposited on the upper surface of the p-GaN layer 91 by physical vapor deposition process to form a TiN protective layer 94 ; SiN dielectric is deposited on the upper surface of the TiN protective layer 94 by chemical vapor deposition process to form a SiN protective layer 95 .

S40, forming an isolation structure 8 on the upper surface of the SiN protection layer 95 and outside the active area of the HEMT device, wherein the isolation structure 8 penetrates the SiN protection layer 95, the TiN protection layer 94, the p-GaN layer 91, the barrier layer 5 and the channel layer 4.

Specifically, in this embodiment, the isolation structure 8 can be any one of a mesa isolation structure and an ion implantation structure. By way of example, taking the ion implantation structure as an example, please refer to FIG. 2c. N ions are implanted at both ends of the upper surface of the passivation layer 100 using a plasma implantation process to form an N ion implantation area. The implantation depth is controlled to the upper surface of the buffer layer 3 to achieve planar device isolation.

S50 , forming a gate region on the upper surface of the SiN protective layer 95 , etching away the SiN protective layer 95 , the TiN protective layer 94 and the p-GaN layer 91 outside the gate region, and etching to a depth reaching the upper surface of the barrier layer 5 .

Specifically, please refer to Figure 2d. In this embodiment, photolithography and development technology are used to form a gate region on the upper surface of the TiN protective layer 94 using photoresist as a mask layer, and the SiN protective layer 95, TiN protective layer 94, and p-GaN layer 91 outside the gate region are etched away until the upper surface of the barrier layer 5.

S60 , removing the SiN protective layer 95 and the TiN protective layer 94 on the upper surface of the HEMT device by a wet method.

Specifically, please refer to Figure 2e. In this embodiment, an inorganic solution such as hydrofluoric acid and BOE is used to etch away the SiN protective layer 95 on the surface of the material, and a solution such as TMAH and SPM is used to etch away the TiN protective layer 94 on the surface. The purpose of this step is mainly to remove the surface protective layer.

S70. Deposit a dielectric material on the upper surface of the barrier layer 5, the upper surface of the p-GaN layer 91 and the sidewall of the p-GaN layer 91 to form a passivation layer 100, wherein the thickness of the passivation layer 100 is in the range of 50 nm-400 nm, and the passivation layer 100 comprises: a first passivation sublayer 10 and a second passivation sublayer 11, the first passivation sublayer 10 is located below the second passivation sublayer 11, the material of the first passivation sublayer 10 comprises: at least one of AlN, SiON, SiN, AlON, Al ₂ O ₃ , HfO ₂ , ZrO ₂ and Y ₂ O ₃ , and the material of the second passivation sublayer 11 comprises: at least one of SiO ₂ , SiN and SiON.

It should be noted that the passivation layer 100 in the present embodiment can be a passivation layer produced by a single-layer dielectric, or a multi-layer passivation layer produced by multiple dielectrics. By way of example, taking two-layer passivation layers as an example, please refer to FIG. 2f. In the present embodiment, any one of plasma enhanced atomic layer deposition (PEALD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), and low pressure chemical vapor deposition (LPCVD) processes is used to deposit dielectric materials on the upper surface of the barrier layer 5 and the p-GaN layer 91 and the sidewalls of the p-GaN layer 91 to form _a first passivation sublayer 10 with a thickness of 10nm-50nm, wherein the dielectric material includes at least one of AlN, SiON, SiN, AlON, _Al2O3 , _HfO2 , _ZrO2 , and _Y2O3 , and then a second passivation sublayer 11 with a thickness of _10nm -500nm is deposited, wherein the dielectric material includes _SiO2 or SiN.

S80, forming a gate opening area on the upper surface of the passivation layer 100 in the gate area, and etching the passivation layer 100 in the gate opening area until the upper surface of the p-GaN layer 91, and depositing a tunneling medium on the sidewall and bottom of the gate opening area to form a tunneling layer 92, wherein the thickness of the tunneling layer 92 is in the range of 0.5 nm _- 5 nm, and the material of the tunneling layer 92 includes: at least one of SiN, SiON, AlN, AlON and _Al2O3 .

Specifically, referring to FIG. 2g , in this embodiment, a gate region is formed on the upper surface of the passivation layer 100 on the p-GaN layer 91 by using photolithography and development technology, using photoresist as a mask layer, and the passivation layer 100 at the gate region is etched away until the upper surface of the p-GaN layer 91 , and a tunneling medium is deposited on the upper surface of the p-GaN layer 91 and the side of the groove of the passivation layer 100 to form a tunneling layer 92.

In a specific embodiment, any one of a plasma enhanced atomic layer deposition process, an atomic layer deposition process, a plasma enhanced chemical vapor deposition process and a low pressure chemical vapor deposition process is used to form a gate opening area on the upper surface of the passivation layer 100 in the gate area, and the dielectric layer in the gate opening area is etched away until the upper surface of the p-GaN layer 91, and a tunneling medium is deposited on the sidewalls and bottom of the gate opening area to form a tunneling layer 92.

S90 , forming a gate metal region on the upper surface of the tunneling layer 92 , and depositing a gate metal to form a gate 93 .

Specifically, referring to FIG. 2h, in this example, photolithography and development technology are used to form a gate region on the tunneling layer 92 using a photoresist as a mask layer, and magnetron sputtering or electron beam evaporation technology is used to deposit the gate metal.

S100, forming a source region and a drain region on the upper surface of the passivation layer 100 respectively, etching the passivation layer 100 in the source region and the drain region until the upper surface of the barrier layer is reached to form a source etching region and a drain etching region, and depositing metal in the source etching region and the drain etching region to form a source 7 and a drain 6.

Specifically, please refer to Figure 2i. In this embodiment, photolithography and development technology are used, with photoresist as a mask layer, to form a drain 6 region and a source 7 region on the upper surface of the passivation layer 100 adjacent to the isolation structure 8, respectively, and the passivation layer 100 at the drain 6 region is etched away, and a drain metal is deposited on the barrier layer 5 to form a drain 6. At the same time, the passivation layer 100 at the source 7 region is etched away, and a source metal is deposited on the barrier layer 5 to form a source 7. Finally, the entire device is annealed to achieve ohmic contact between the source 7 and the drain 6.

The present application also provides a chip, wherein the chip comprises: a tunneling gate HEMT device as described in any one of the above.

The present application also provides an electronic device, which includes: the chip as described above.

In all examples shown and described herein, any specific values should be interpreted as merely exemplary and not as limiting, and thus other examples of the exemplary embodiments may have different values.

It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include: one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims (11)

1. A tunnel gate HEMT device, comprising: A substrate layer, a transition layer, a buffer layer, a channel layer and a barrier layer sequentially disposed on the substrate layer; A p-GaN layer located on the barrier layer; an isolation structure, located on a sidewall of the HEMT device, wherein the isolation structure penetrates the barrier layer and the channel layer and is located on the buffer layer; a passivation layer, located on the side wall of the p-GaN layer and on the barrier layer, wherein the thickness of the passivation layer ranges from 50 nm to 400 nm, and the passivation layer comprises: a first passivation sublayer and a second passivation sublayer, the first passivation sublayer is located below the second passivation sublayer, the first passivation sublayer material comprises: at least one of AlN, SiON, SiN, AlON, Al ₂ O ₃ , HfO ₂ , ZrO ₂ and Y ₂ O ₃ , and the second passivation sublayer material comprises: at least one of SiO ₂ , SiN and SiON; A tunneling layer, located at the bottom and side of the gate opening region of the passivation layer, wherein the thickness of the tunneling layer is in the range of 0.5 nm to 5 nm, and the material of the tunneling layer includes at least one of SiN, SiON, AlN, AlON and Al ₂ O ₃ ; A gate, which penetrates the passivation layer and is located on the tunneling layer; A source electrode, located on one side of the p-GaN layer, wherein the source electrode penetrates the passivation layer and is located on the barrier layer; A drain electrode is located on the other side of the p-GaN layer, wherein the drain electrode penetrates the passivation layer and is located on the barrier layer. 2 . The tunneling gate HEMT device according to claim 1 , wherein the thickness of the p-GaN layer is in the range of 50 nm to 500 nm; and the Mg doping concentration of the p-GaN layer is in the range of 10 ¹⁸ cm ⁻³ to 10 ²⁰ cm ⁻³ . 3. The tunneling gate HEMT device according to claim 1, characterized in that the thickness of the transition layer ranges from 10 nm to 500 nm, and the material of the transition layer includes: at least one of AlN, AlGaN and GaN; the thickness of the buffer layer ranges from 300 nm to 6000 nm, and the material of the buffer layer includes: at least one of high-resistance GaN and high-resistance AlGaN; the thickness of the channel layer ranges from 50 nm to 500 nm, and the material of the channel layer includes: unintentionally doped GaN; the thickness of the barrier layer ranges from 10 nm to 40 nm, and the material of the barrier layer includes: Al _x Ga _1-x N, wherein the value range of x is 0.1-0.5. 4 . The tunneling gate HEMT device according to claim 1 , wherein the isolation structure comprises: any one of a mesa isolation structure and an ion implantation structure. 5. A method for preparing a tunnel gate HEMT device, comprising: providing a substrate layer; Growing a transition layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer in sequence on the substrate layer; Depositing TiN metal and SiN dielectric in sequence on the upper surface of the p-GaN layer to form a TiN protective layer and a SiN protective layer; An isolation structure is formed on the upper surface of the SiN protective layer and outside the active region of the device, wherein the isolation structure penetrates the SiN protective layer, the TiN protective layer, the p-GaN layer, the barrier layer and the channel layer; forming a gate region on the upper surface of the SiN protective layer, and etching the SiN protective layer, the TiN protective layer and the p-GaN layer outside the gate region to a depth reaching the upper surface of the barrier layer; Removing the SiN protective layer and the TiN protective layer on the upper surface of the HEMT device by a wet method; A dielectric material is deposited on the upper surface of the barrier layer, the upper surface of the p-GaN layer and the sidewall of the p-GaN layer to form a passivation layer, wherein the thickness of the passivation layer is in the range of 50 nm-400 nm, and the passivation layer comprises: a first passivation sublayer and a second passivation sublayer, the first passivation sublayer is located below the second passivation sublayer, the material of the first passivation sublayer comprises: at least one of AlN, SiON, SiN, AlON, Al ₂ O ₃ , HfO ₂ , ZrO ₂ and Y ₂ O ₃ , and the material of the second passivation sublayer comprises: at least one of SiO ₂ , SiN and SiON; A gate opening region is formed on the upper surface of the passivation layer in the gate region, and the dielectric layer in the gate opening region is etched away until the upper surface of the p-GaN layer, and a tunneling dielectric is deposited on the sidewall and bottom of the gate opening region to form a tunneling layer, wherein the thickness of the tunneling layer is in the range of 0.5 nm to 5 nm, and the material of the tunneling layer includes: at least one of SiN, SiON, AlN, _AlON and _Al2O3 ; forming a gate metal region on the upper surface of the tunneling layer, and depositing a gate metal to form a gate; A source region and a drain region are respectively formed on the upper surface of the passivation layer, and the passivation layers of the source region and the drain region are etched until the upper surface of the barrier layer to form a source etching region and a drain etching region, and metal is deposited in the source etching region and the drain etching region to form a source and a drain. 6. The method for preparing a tunnel gate HEMT device according to claim 5, characterized in that the step of sequentially growing a transition layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer on the substrate layer comprises: A metal organic chemical vapor deposition process is adopted to sequentially grow a transition layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer on the substrate layer. 7. The method for preparing a tunnel gate HEMT device according to claim 5, characterized in that the step of sequentially depositing TiN metal and SiN dielectric on the upper surface of the p-GaN layer to form a TiN protective layer and a SiN protective layer comprises: Depositing TiN metal on the upper surface of the p-GaN layer using a physical vapor deposition process to form a TiN protective layer; A SiN medium is deposited on the upper surface of the TiN protective layer by using a chemical vapor deposition process to form a SiN protective layer. 8. The method for preparing a tunnel gate HEMT device according to claim 5, characterized in that the step of depositing a dielectric material on the upper surface of the barrier layer, the upper surface of the p-GaN layer and the sidewall of the p-GaN layer to form a passivation layer comprises: By using any one of a plasma enhanced atomic layer deposition process, an atomic layer deposition process, a plasma enhanced chemical vapor deposition process and a low pressure chemical vapor deposition process, a dielectric material is deposited on the upper surface of the barrier layer, the upper surface of the p-GaN layer and the side wall of the p-GaN layer to form a passivation layer. 9. The method for preparing a tunneling gate HEMT device according to claim 5, characterized in that the forming of a gate opening region on the upper surface of the passivation layer in the gate region, etching away the dielectric layer in the gate opening region until the upper surface of the p-GaN layer, and depositing a tunneling dielectric on the sidewall and bottom of the gate opening region to form a tunneling layer comprises: By adopting any one of plasma enhanced atomic layer deposition process, atomic layer deposition process, plasma enhanced chemical vapor deposition process and low pressure chemical vapor deposition process, a gate opening area is formed on the upper surface of the passivation layer in the gate area, and the dielectric layer in the gate opening area is etched away until the upper surface of the p-GaN layer, and a tunneling medium is deposited on the side wall and the bottom of the gate opening area to form a tunneling layer. 10. A chip, characterized in that the chip comprises: a tunneling gate HEMT device according to any one of claims 1 to 4. 11. An electronic device, characterized in that the electronic device comprises: the chip according to claim 10.